MC10EP445FAR2 [ONSEMI]
3.3V/5VECL 8-Bit Serial/Parallel Converter; 3.3V / 5V ？ ECL 8位串行/并行转换器
| 型号： | MC10EP445FAR2 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V/5VECL 8-Bit Serial/Parallel Converter |
| 文件： | 总16页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP445, MC100EP445
3.3V/5VꢀECL 8−Bit
Serial/Parallel Converter
The MC10/100EP445 is an integrated 8–bit differential serial to
parallel data converter with asynchronous data synchronization. The
device has two modes of operation. CKSEL HIGH mode is designed
to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode
is designed to operate at twice the internal clock data rate of up to
5.0 Gb/s. The conversion sequence was chosen to convert the first
serial bit to Q0, the second bit to Q1, etc. Two selectable differential
serial inputs, which are selected by SINSEL, provide this device with
loop-back testing capability. The MC10/100EP445 has a SYNC pin
which, when held high for at least two consecutive clock cycles, will
swallow one bit of data shifting the start of the conversion data from
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MARKING
DIAGRAM*
MCXXX
EP445
AWLYYWW
D to D . Each additional shift requires an additional pulse to be
n
n+1
LQFP-32
FA SUFFIX
CASE 873A
applied to the SYNC pin.
Control pins are provided to reset and disable internal clock
32
circuitry. Additionally, V pin is provided for single-ended input
1
BB
condition.
XXX = 10 OR 100
The 100 Series contains temperature compensation.
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• 300 ps Propagation Delay
• 5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode
• Differential Clock and Serial Inputs
*For additional information, see Application Note
AND8002/D
• V Output for Single-Ended Input Applications
BB
• Asynchronous Data Synchronization (SYNC)
• Asynchronous Master Reset (RESET)
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
ORDERING INFORMATION
CC
with V = -3.0 V to -5.5 V
EE
Device
Package
Shipping
• Open Input Default State
MC10EP445FA
LQFP-32
250 Units/Tray
• CLK ENABLE Immune to Runt Pulse Generation
MC10EP445FAR2 LQFP-32 2000/Tape & Reel
MC100EP445FA LQFP-32 250 Units/Tray
MC100EP445FAR2 LQFP-32 2000/Tape & Reel
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
November, 2002 - Rev. 7
MC10EP445/D
MC10EP445, MC100EP445
PIN DESCRIPTION
FUNCTION
PIN
24 23 22 21 20 19 18 17
SINA*, SINA*
ECL Differential Serial Data Input A
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
SINSEL
V
EE
SINB*, SINB*
SINSEL*
ECL Differential Serial Data Input B
ECL Serial Input Selector Pin
Q3
Q4
SINB
SINB
Q0-Q7
ECL Parallel Data Outputs
ECL Differential Clock Inputs
MC10EP445
MC100EP445
V
EE
V
CC
CC
CLK*, CLK*
V
BB0
V
PCLK, PCLK
SYNC*
ECL Differential Parallel Clock Output
ECL Conversion Synchronizing Input
ECL Clock Input Selector Pin
SINA
SINA
Q5
Q6
Q7
CKSEL*
CKEN*
ECL Clock Enable Pin
ECL Reset Pin
V
CC
RESET*
1
2
3
4
5
6
7
8
V
V
, V
Output Reference Voltage
Positive Supply
BB0 BB1
CC
EE
V
Negative Supply
*
Pins will default logic LOW or differential logic LOW
when left open.
Warning: All V and V pins must be externally
CC
EE
connected to Power Supply to guarantee proper
operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
TRUTH TABLE
FUNCTION
High
Low
Select SINA Input
PIN
SINSEL Select SINB Input
CKSEL
Q: PCLK = 8:1
CLK: Q = 1:2
Q: PCLK = 8:1
CLK: Q = 1:1
CLK
Q
CLK
Q
CKEN
Synchronously Disable Internal Clock Circuitry
Synchronously Enable Internal
Clock Circuitry
RESET
SYNC
Asynchronous Master Reset
Synchronous Enable
Asynchronously Applied to Swallow a Data Bit
Normal Conversion Process
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2
MC10EP445, MC100EP445
SINA
V
EE
SINA
SINB
Q0
Q4
1:2
DEMUX
1:2
DEMUX
1:2
DEMUX
SINB
SINSEL
Q2
Q6
Q1
1:2
DEMUX
CKEN
T
Q
Q
C
1:2
1:2
R
R
DEMUX
DEMUX
Q5
Q3
T
1:2
DEMUX
C
SYNC
Q7
Control
Logic
PCLK
PCLK
DIV2
DIV2
CLK
CLK
CKSEL
RESET
Figure 2. Logic Diagram
Characteristics
ATTRIBUTES
Value
75 kW
N/A
Internal Input Pulldown Resistor
Internal Input Pull-up Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Level 2
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
993 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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3
MC10EP445, MC100EP445
MAXIMUM RATINGS (Note 2)
Symbol Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
6
EE
= 0 V
-6
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
V
V
EE
I
CC
V ꢁ V
-6
CC
I
EE
I
I
Output Current
Continuous
Surge
50
mA
mA
out
100
V
BB
Sink/Source
± 0.5
mA
°C
BB
TA
Operating Temperature Range
-40 to +85
-65 to +150
T
Storage Temperature Range
°C
stg
q
Thermal Resistance (Junction-to-Ambient)
0 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JA
500 LFPM
q
Thermal Resistance (Junction-to-Case)
Wave Solder
std bd
32 LQFP
12 to 17
265
°C/W
°C
JC
T
sol
< 2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 3)
CC
EE
-40 °C
Typ
25°C
85°C
Min
Max
143
Min
Typ
122
Max
146
Min
100
Typ
125
Max
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
95
119
98
150
2540
1740
2540
1815
2115
3.3
V
V
V
V
V
V
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
2165
1365
2090
1365
1790
2.0
2290
1490
2415
1615
2415
1690
1990
3.3
2230
1430
2155
1460
1855
2.0
2355
1555
2480
1680
2480
1755
2055
3.3
2290
1490
2215
1490
1915
2.0
2415
1615
OH
OL
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
IH
IL
1890
1955
2015
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
m A
m A
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with V . V can vary +0.3 V to -2.2 V.
CC
EE
4. All loading with 50 W to V - 2.0 volts.
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC10EP445, MC100EP445
10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 6)
CC
EE
-40 °C
Typ
25°C
Typ
85°C
Typ
Min
Max
143
Min
98
Max
146
Min
100
Max
150
Symbol
Characteristic
Power Supply Current (Note 7)
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
95
119
122
125
V
V
V
V
V
V
3865
3065
3790
3065
3490
2.0
3990
3190
4115
3315
4115
3390
3690
5.0
3930
3130
3855
3130
3555
2.0
4055
3255
4180
3380
4180
3455
3755
5.0
3990
3190
3915
3190
3615
2.0
4115
3315
4240
3440
4240
3515
3815
5.0
OH
OL
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
IH
IL
3590
3655
3715
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 9)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
m A
m A
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with V . V can vary +2.0 V to -0.5 V.
CC
EE
7. Required 500 lfpm air flow when using +5 V power supply. For (V - V ) >3.3 V, 5 W to 10 W in line with V required for maximum thermal
CC
EE
EE
protection at elevated temperatures. Recommend V -V
operation at ꢀ 3.3 V.
CC
EE
8. All loading with 50 W to V -2.0 volts.
CC
9. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10EP DC CHARACTERISTICS, NECL V = 0 V, V = -5.5 V to -3.0 V (Note 10)
CC
EE
-40 °C
Typ
25°C
Typ
85°C
Typ
Min
Max
143
Min
98
Max
146
Min
100
Max
150
Symbol
Characteristic
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
Power Supply Current (Note 11)
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
95
119
122
125
V
V
V
V
V
V
-1135 -1010
-885
-1070
-945
-820
-1010
-885
-760
OH
-1935 -1810 -1685 -1870 -1745 -1620 -1810 -1685 -1560
OL
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
-1210
-1935
-885
-1145
-820
-1085
-760
IH
-1610 -1870
-1545 -1810
-1485
IL
-1510 -1410 -1310 -1445 -1345 -1245 -1385 -1285 -1185
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 13)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
m A
m A
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10.Input and output parameters vary 1:1 with V
.
CC
11. Required 500 lfpm air flow when using -5 V power supply. For (V - V ) >3.3 V, 5 W to 10 W in line with V required for maximum thermal
CC
EE
EE
protection at elevated temperatures. Recommend V -V
operation at ꢀ 3.3 V.
CC
EE
12.All loading with 50 W to V -2.0 volts.
CC
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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5
MC10EP445, MC100EP445
100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 14)
CC
EE
-40 °C
Typ
25°C
Typ
85°C
Typ
Min
Max
143
Min
98
Max
146
Min
100
Max
150
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
95
119
122
125
V
V
V
V
V
V
Output HIGH Voltage (Note 15)
Output LOW Voltage (Note 15)
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
OH
OL
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
IH
IL
1875
1875
1875
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 16)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
m A
m A
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14.Input and output parameters vary 1:1 with V . V can vary +0.3 V to -2.2 V.
CC
EE
15.All loading with 50 W to V -2.0 volts.
CC
16.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 17)
CC
EE
-40 °C
Typ
25°C
Typ
85°C
Typ
Min
Max
143
Min
98
Max
146
Min
100
Max
150
Symbol
Characteristic
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
Power Supply Current (Note 18)
Output HIGH Voltage (Note 19)
Output LOW Voltage (Note 19)
95
119
122
125
V
V
V
V
V
V
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
OH
OL
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
IH
IL
3575
3575
3575
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
m A
m A
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
17.Input and output parameters vary 1:1 with V . V can vary +2.0 V to -0.5 V.
CC
EE
18.Required 500 lfpm air flow when using +5 V power supply. For (V - V ) >3.3 V, 5 W to 10 W in line with V required for maximum thermal
CC
EE
EE
protection at elevated temperatures. Recommend V -V
operation at ꢀ 3.3 V.
CC
EE
19.All loading with 50 W to V -2.0 volts.
CC
20.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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6
MC10EP445, MC100EP445
100EP DC CHARACTERISTICS, NECL V = 0 V, V = -5.5 V to -3.0 V (Note 21)
CC
EE
-40 °C
25°C
Typ
122
85°C
Typ
125
Min
Typ
Max
143
Min
Max
146
Min
Max
150
Symbol
Characteristic
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
Power Supply Current (Note 22)
Output HIGH Voltage (Note 23)
Output LOW Voltage (Note 23)
95
119
98
100
V
V
V
V
V
V
-1145 -1020
-895
-1145 -1020
-895
-1145 -1020
-895
OH
OL
-1945 -1820 -1695 -1945 -1820 -1695 -1945 -1820 -1695
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
-1225
-1945
-880
-1225
-880
-1225
-880
IH
-1625 -1945
-1625 -1945
-1625
IL
-1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 24)
V
EE
+ 2.0
0.0
V
EE
+ 2.0
0.0
V + 2.0
EE
0.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
m A
m A
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
21.Input and output parameters vary 1:1 with V
.
CC
22.Required 500 lfpm air flow when using -5 V power supply. For (V - V ) > 3.3 V, 5 W to 10 W in line with V required for maximum thermal
CC
EE
EE
protection at elevated temperatures. Recommend V -V
operation at v 3.3 V.
CC
EE
23.All loading with 50 W to V
- 2.0 volts.
CC
24.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
AC CHARACTERISTICS V = 0 V; V = -3.0 V to -5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 25)
CC
EE
CC
EE
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
f
Maximum Input CLK Frequency CKSEL = LOW
2.0
2.8
2.5
3.3
2.0
2.8
2.5
3.3
1.7
2.8
2.2
3.3
GHz
max
(See Figure 12. F
/JITTER)
CKSEL = HIGH
max
t
t
,
Propagation Delay to
Output Differential
CLK to Q 1230 1450 1660 1300 1530 1760 1400 1650 1900
CLK TO PCLK 1000 1240 1490 1050 1310 1580 1140 1420 1710
ps
ps
ps
PLH
PHL
ts
Setup Time
SINA, B+ TO CLK+ (Figure 4) -300 -400
-300 -400
-300 -400
CKEN+ TO CLK- (Figure 5) 100
50
100
50
100
50
t
h
Hold Time
CLK+ TO SINA, B- (Figure 4) 650
550
-35
675
45
575
-35
725
45
625
-35
CLK- TO CKEN (Figure 5)
45
350
t
t
t
/t
Reset Recovery (Figure 3)
Minimum Pulse Width
Cycle-to-Cycle Jitter
180
350
400
180
350
400
180
ps
ps
ps
RR RR2
RESET 400
PCLK
PW
0.2
< 1
0.2
< 1
0.2
< 1
JITTER
(See Figure 12. F
/JITTER)
max
V
PP
Input Voltage Swing (Differential)
(Note 26)
150
800 1200 150
800 1200 150
800 1200 mV
t
r
t
f
Output Rise/Fall Times
(20% - 80%)
Q
100
180
250
100
200
300
125
230
325
ps
25.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V
- 2.0 V.
CC
26.V (min) is the minimum input swing for which AC parameters are guaranteed.
PP
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MC10EP445, MC100EP445
t
RR
Reset
CLK
CLK
Figure 3. Reset Recovery
CLK
Data Setup Time
Data Hold Time
+
-
t
s
+
-
t
h
Figure 4. Data Setup and Hold Time
CLK
+
-
CKEN Setup Time
CKEN Hold Time
t
s
-
+
t
h
Figure 5. CKEN Setup and Hold Time
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MC10EP445, MC100EP445
APPLICATION INFORMATION
The MC10/100EP445 is an integrated 1:8 serial to parallel
The two selectable serial data paths can be used for
loop-back testing as well as the bit error testing.
Upon power-up, the internal flip-flops will attain a
random state. To synchronize multiple flip–flops in the
device, the Reset (pin 1) must be asserted. The reset pin will
disable the internal clock signal irrespective of the CKEN
state (CKEN disables the internal clock circuitry). The
device will grab the first stream of data after the falling edge
of RESETÀ, followed by the falling edge of CLKÁ, on
second rising edge of CLKÂ in either CKSEL modes. (See
Figure 6)
converter with two modes of operation selected by
CKSEL (Pin 7). CKSEL HIGH mode only latches data on
the rising edge of the input CLK and CKSEL LOW mode
latches data on both the rising and falling edge of the input
CLK. CKSEL LOW is the open default state. Either of the
two differential input serial data path provided for this
device, SINA and SINB, can be chosen with the SINSEL pin
(pin 25). SINA is the default input path when SINSEL pin
is left floating. Because of internal pull-downs on the input
pins, all input pins will default to logic low when left open.
RESET
(Asynchronous Reset)
RESET
(Synchronous ENABLE)
Â
Á
CLK
RESET
PCLK
À
Figure 6. Reset Timing Diagram
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MC10EP445, MC100EP445
For CKSEL LOW operation, the data is latched on both
the rising edge and the falling edge of the clock and the time
from when the serial data is latchedÀ to when the data is seen
on the parallel outputÁ is 6 clock cycles (see Figure 7).
Number of Clock Cycles from Data Latch to Q
1
2
3
4
5
6
À
CLK
SINA
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
RESET
CKEN
CKSEL
PCLK
Á
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D8
D9
D16
D17
D18
D19
D20
D21
D22
D23
D1
D2
D3
D4
D5
D6
D7
D10
D11
D12
D13
D14
D15
Figure 7. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL LOW
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MC10EP445, MC100EP445
Similarly, for CKSEL HIGH operation, the data is latched
only on the rising edge of the clock and the time from when
the serial data is latchedÀ to when the data is seen on the
parallel outputÁ is 12 clock cycles (see Figure 8).
Number of Clock Cycles from Data Latch to Q
1
2
3
4
5
6
7
8
9
10
11
12
À
CLK
SINA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
RESET
CKEN
CKSEL
PCLK
Á
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL HIGH
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11
MC10EP445, MC100EP445
To allow the user to synchronize the output byte data
correctly, the start bit for conversion can be moved using the
SYNC input pin (pin 2). Asynchronously asserting the
SYNC pin will force the internal clock to swallow a clock
clock cycles shifts the start bit for conversion from Q to
n
Q
n- 1
. The bit is swallowed following the two clock cycle
pulse width of SYNCÀ on the next triggering edge of
clockÁ (either on the rising or the falling edge of the clock).
Each additional shift requires an additional pulse to be
applied to the SYNC pin. (See Figure 9)
pulse, effectively shifting a bit from the Q to the Q output
n
n- 1
as shown in Figure 9 and Figure 10. For CKSEL LOW, a
single pulse applied asynchronously for two consecutive
2 Clock Cycles for SYNC
Next Triggering Edge of Clock
Bit D8 is Swallowed
1
2
Á
CLK
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
SINA
CKSEL
PCLK
À
SYNC
Q0
D0
D1
D2
D3
D4
D5
D6
D7
D9
D17
D18
D19
D20
D21
D22
D23
D24
Q1
D10
D11
D12
D13
D14
D15
D16
Q2
Q3
Q4
Q5
Q6
Q7
Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL LOW
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12
MC10EP445, MC100EP445
For CKSEL HIGH, a single pulse applied asynchronously
for three consecutive clock cycles shifts the start bit for
conversion from Q to Q . The bit is swallowed following
triggering edge of clockÁ (on the rising edge of the clock
only). Each additional shift requires an additional pulse to be
applied to the SYNC pin. (See Figure 10)
n
n- 1
the three clock cycle pulse width of SYNCÀ on the next
3 Clock Cycles for Sync
Next Triggering Edge of Clock
Bit D8 is Swallowed
1
2
3
Á
CLK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
SINA
À
SYNC
PCLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
Figure 10. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL HIGH
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13
MC10EP445, MC100EP445
The synchronous CKEN (pin 3) applied with at least one
edge of CLK will suspend all activities. The first data bit will
clock on the rising edge, since the falling edge of CKEN
followed by the falling edge of the incoming clock triggers
the enabling of the internal process. (See Figure 11)
clock cycle pulse length will disable the internal clock
signal. The synchronous CKEN will suspend all of the
device activities and prevent runt pulses from being
generated. The rising edge of CKEN followed by the falling
Internal Clock
Disabled
Internal Clock
Enabled
CLK
CKEN
PCLK
CKSEL
Figure 11. Timing Diagram with CKEN with CKSEL HIGH
The differential PCLK output (pins 22 and 23) is a word
framer and can help the user to synchronize the parallel data
outputs. During CKSEL LOW operation, the PCLK will
provide a divide by 4-clock frequency, which frames the
serial data in period of PCLK output. Likewise during
CKSEL HIGH operation, the PCLK will provide a divide by
8-clock frequency.
conditions, the unused differential input is connected to
VBB as a switching reference voltage. V may also rebias
BB
AC coupled inputs. When used, decouple V and V via
BB
CC
a 0.01 Fmcapacitor, which will limit the current sourcing or
sinking to 0.5mA. When not used, V should be left open.
BB
Also, both outputs of the differential pair must be terminated
(50 W to V = V – 2 V) even if only one output is used.
TT
CC
The V pin, an internally generated voltage supply, is
BB
available to this device only. For single–ended input
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14
MC10EP445, MC100EP445
1000
900
800
700
600
500
400
300
200
100
0
10
9
CKSEL HIGH
8
7
6
CKSEL LOW
5
4
3
2
1
(JITTER)
1500
0
500
1000
2000
2500
3000
3500
INPUT CLK FREQUENCY (MHz)
Figure 12. Fmax/Jitter
Q
Q
D
D
Receiver
Device
Driver
Device
50
TT
50
W
W
V
TT
V
V
=
- 2.0 V
CC
Figure 13. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1504
AN1568
AN1650
AN1672
AND8001
AND8002
AND8009
AND8020
-
-
-
-
-
-
-
-
-
-
-
ECLinPS Circuit Performance at Non-Standard V Levels
IH
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
Using Wire-OR Ties in ECLinPS Designs
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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15
MC10EP445, MC100EP445
PACKAGE DIMENSIONS
LQFP
FA SUFFIX
32-LEAD PLASTIC PACKAGE
CASE 873A-02
ISSUE A
4X
A
A1
0.20 (0.008) AB T−U
Z
32
25
BASE
METAL
1
N
-U-
V
-T-
B
F
D
AE
AE
B1
DETAIL Y
-Z-
P
V1
17
8
J
9
4X
SECTION AE-AE
DETAIL Y
0.20 (0.008) AC T−U
Z
9
S1
S
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED
AT DATUM PLANE −AB−.
G
MILLIMETERS
DIM MIN MAX
7.000 BSC
3.500 BSC
INCHES
MIN
MAX
-AB-
-AC-
A
A1
B
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
SEATING
PLANE
7.000 BSC
3.500 BSC
0.10 (0.004) AC
B1
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
D
0.300
1.350
0.300
0.012
0.053
0.012
E
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −AC−.
_
8X M
F
R
G
H
0.800 BSC
0.031 BSC
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
0.050
0.090
0.500
0.150
0.200
0.700
0.002
0.004
0.020
0.006
0.008
0.028
J
K
_
12 REF
_
12 REF
M
N
E
C
0.090
0.160
0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5_
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
W
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
_
Q
H
K
X
V1
W
X
DETAIL AD
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MC10EP445/D
相关型号：
MC10EP445MNR4G
10E SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQCC32, LEAD FREE, LQFN-32
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