MC10H100FN [ONSEMI]
Quad 2 - input NOR GATE With strobe; 四2 - 输入或非门选通
| 型号： | MC10H100FN |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2 - input NOR GATE With strobe |
| 文件： | 总4页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC10H100 is a quad NOR gate. Each gate has 3 inputs, two of
which are independent and one of which is tied common to all four
gates.
http://onsemi.com
• Propagation Delay, 1.0 ns Typical
• 25 mW Typ/Gate (No Load)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
MARKING
DIAGRAMS
16
• Voltage Compensated
• MECL 10K–Compatible
CDIP–16
L SUFFIX
CASE 620
MC10H100L
AWLYYWW
LOGIC DIAGRAM
1
4
16
2
5
PDIP–16
P SUFFIX
CASE 648
MC10H100P
AWLYYWW
6
3
7
9
1
1
10
14
11
PLCC–20
FN SUFFIX
CASE 775
10H100
12
15
13
AWLYYWW
V
= PIN 1
= PIN 16
= PIN 8
2 = 4 + 5 + 9
CC1
V
CC2
V
EE
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
DIP
PIN ASSIGNMENT
ORDERING INFORMATION
V
V
CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
Device
Package
Shipping
D
OUT
A
OUT
MC10H100L
CDIP–16
25 Units/Rail
C
OUT
B
OUT
D
IN
A
IN
MC10H100P
PDIP–16
PLCC–20
25 Units/Rail
46 Units/Rail
D
IN
A
IN
MC10H100FN
C
IN
B
IN
C
IN
B
IN
COMMON
INPUT
V
EE
(A, B, C, D)
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 6
MC10H100/D
MC10H100
MAXIMUM RATINGS
Symbol
Characteristic
Rating
Unit
Vdc
Vdc
mA
V
EE
Power Supply (V
= 0)
= 0)
–8.0 to 0
CC
V
I
Input Voltage (V
CC
0 to V
50
EE
I
Output Current– Continuous
– Surge
out
100
T
Operating Temperature Range
0 to +75
°C
°C
A
T
stg
Storage Temperature Range – Plastic
–55 to +150
–55 to +165
– Ceramic
ELECTRICAL CHARACTERISTICS (V
= –5.2 V ±5%) (See Note 1.)
0°
EE
25°
75°
Max
29
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Unit
mA
µA
I
E
–
29
–
26
–
I
Input Current High
Pin 9
All Other Inputs
inH
–
–
900
500
–
–
560
310
–
–
560
310
I
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
0.5
–
0.5
–
0.3
–
µA
inL
V
–1.02
–1.95
–1.17
–1.95
–0.84
–1.63
–0.84
–1.48
–0.98
–1.95
–1.13
–1.95
–0.81
–1.63
–0.81
–1.48
–0.92
–1.95
–1.07
–1.95
–0.735
–1.60
–0.735
–1.45
Vdc
Vdc
Vdc
Vdc
OH
V
OL
V
IH
V
IL
AC PARAMETERS
t
pd
Propagation Delay
Pin 9 Only
Exclude Pin 9
ns
0.65
0.4
1.6
1.3
0.7
0.45
1.7
1.35
0.7
0.5
1.8
1.5
t
Rise Time
Fall Time
0.5
0.5
2.0
2.0
0.5
0.5
2.1
2.1
0.5
0.5
2.2
2.2
ns
ns
r
t
f
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts.
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2
MC10H100
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
M
S
S
0.007 (0.180)
T L–M
N
B
Y BRK
–M–
–N–
M
S
S
0.007 (0.180)
T L–M
N
U
D
D
–L–
Z
W
20
1
S
S
S
0.010 (0.250)
T L–M
N
G1
X
V
A
VIEW D–D
M
M
S
S
S
S
0.007 (0.180)
0.007 (0.180)
T L–M
N
N
M
S
S
0.007 (0.180)
T L–M
N
H
Z
T L–M
R
K1
K
C
E
M
S
S
0.007 (0.180)
T L–M
N
F
0.004 (0.100)
VIEW S
G
–T– SEATING
PLANE
J
VIEW S
NOTES:
INCHES
MILLIMETERS
G1
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
DIM MIN
MAX
0.395
0.395
0.180
0.110
0.019
MIN
9.78
9.78
4.20
2.29
0.33
MAX
10.03
10.03
4.57
2.79
0.48
S
S
S
0.010 (0.250)
T L–M
N
A
B
C
E
0.385
0.385
0.165
0.090
0.013
F
G
H
J
0.050 BSC
1.27 BSC
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
0.026
0.020
0.025
0.350
0.350
0.042
0.042
0.042
–––
0.032
–––
–––
0.356
0.356
0.048
0.048
0.056
0.020
10
0.66
0.51
0.64
8.89
8.89
1.07
1.07
1.07
–––
2
0.81
–––
–––
9.04
9.04
1.21
1.21
1.42
0.50
10
K
R
U
V
W
X
Y
Z
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
2
G1 0.310
K1 0.040
0.330
–––
7.88
1.02
8.38
–––
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3
MC10H100
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
DIM MIN MAX
0.750 0.785 19.05 19.93
MILLIMETERS
MIN MAX
A
B
C
D
E
0.240 0.295
––– 0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
6.10
–––
0.39
1.27 BSC
1.40
2.54 BSC
0.21
3.18
7.62 BSC
0
7.49
5.08
0.50
–T–
SEATING
PLANE
K
N
F
1.65
G
H
K
L
M
N
M
E
0.38
4.31
F
J 16 PL
G
M
S
0.25 (0.010)
T B
0
15
15
1.01
D 16 PL
0.020 0.040
0.51
M
S
0.25 (0.010)
T A
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
ISSUE R
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.770 18.80
MILLIMETERS
MIN
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
G
H
J
K
L
M
S
0.740
0.250
0.145
0.015
0.040
0.100 BSC
0.050 BSC
0.008
C
L
0.270
0.175
0.021
0.70
6.35
3.69
0.39
1.02
SEATING
PLANE
–T–
2.54 BSC
1.27 BSC
K
M
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
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MC10H100/D
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