MC14007UBDR2G [ONSEMI]

Dual Complementary Pair Plus Inverter; 双互补对加变频器
MC14007UBDR2G
型号: MC14007UBDR2G
厂家: ONSEMI    ONSEMI
描述:

Dual Complementary Pair Plus Inverter
双互补对加变频器

栅极 逻辑集成电路 光电二极管
文件: 总9页 (文件大小:155K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
MC14007UB  
Dual Complementary Pair  
Plus Inverter  
The MC14007UB multipurpose device consists of three NChannel  
and three PChannel enhancement mode devices packaged to provide  
access to each device. These versatile parts are useful in inverter  
circuits, pulseshapers, linear amplifiers, high input impedance  
amplifiers, threshold detectors, transmission gating, and functional  
gating.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
Features  
PDIP14  
P SUFFIX  
CASE 646  
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Lowpower TTL Loads or One Lowpower  
Schottky TTL Load Over the Rated Temperature Range  
PinforPin Replacement for CD4007A or CD4007UB  
This device has 2 outputs without ESD Protection. Antistatic  
precautions must be taken.  
MC14007UBCP  
AWLYYWWG  
1
14  
SOIC14  
D SUFFIX  
CASE 751A  
14007UG  
AWLYWW  
PbFree Packages are Available  
1
14  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
SOEIAJ14  
F SUFFIX  
CASE 965  
MC14007UB  
ALYWG  
Symbol  
Parameter  
Value  
0.5 to +18.0  
Unit  
V
V
DC Supply Voltage Range  
DD  
1
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V +0.5  
V
DD  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
I , I  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
in out  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
WW, W = Work Week  
= PbFree Indicator  
G
T
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
A
T
stg  
PIN ASSIGNMENT  
T
Lead Temperature  
(8 second Soldering)  
L
DP  
SP  
1
2
3
4
5
6
7
14  
V
DD  
B
B
B
B
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating:  
13 DP  
A
GATE  
SN  
12 OUT  
C
11 SP  
C
Plastic “P and D/DW” Packages: – 7.0 mW/°C from 65°C 5o 125°C.  
DN  
10 GATE  
C
B
GATE  
9
8
SN  
C
A
V
DN  
A
SS  
D = DRAIN  
S = SOURCE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
October, 2006 Rev. 8  
MC14007UB/D  
 
MC14007UB  
A
B
A
B
12  
1
9
2
4
C
3
5
INPUT  
V
DD  
14  
C
11  
13  
8
INPUT OUTPUT CONDITION  
INPUT  
6
10  
1
0
A = C, B = OPEN  
A = B, C = OPEN  
7
V
SS  
Substrates of PChannel devices internally  
connected to V ; substrates of NChannel  
DD  
devices internally connected to V  
.
SS  
Figure 1. Typical Application: 2Input Analog Multiplexer  
14 13  
2
1
11  
6
12  
7
8
3
4
5
10  
9
V
V
= PIN 14  
= PIN 7  
DD  
SS  
Figure 2. Schematic  
http://onsemi.com  
2
 
MC14007UB  
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V  
)
SS  
55°C  
25°C  
125°C  
Typ  
(Note 2)  
V
Vdc  
DD  
Min  
Max  
Min  
Max  
Min  
Max  
Symbol  
Characteristic  
Output Voltage  
Unit  
V
“0” Level  
“1” Level  
“0” Level  
5.0  
10  
15  
0.05  
0.05  
0.05  
0
0
0
0.05  
0.05  
0.05  
0.05  
0.05  
0.05  
Vdc  
OL  
V
in  
= V or 0  
DD  
V
5.0  
10  
15  
4.95  
9.95  
14.95  
4.95  
9.95  
14.95  
5.0  
10  
15  
4.95  
9.95  
14.95  
Vdc  
Vdc  
V
in  
= 0 or V  
OH  
DD  
V
Input Voltage  
(V = 4.5 Vdc)  
IL  
5.0  
10  
15  
1.0  
2.0  
2.5  
2.25  
4.50  
6.75  
1.0  
2.0  
2.5  
1.0  
2.0  
2.5  
O
(V = 9.0 Vdc)  
O
(V = 13.5 Vdc)  
O
V
5.0  
10  
15  
4.0  
8.0  
12.5  
4.0  
8.0  
12.5  
2.75  
5.50  
8.25  
4.0  
8.0  
12.5  
Vdc  
(V = 0.5 Vdc)  
“1” Level  
Source  
Sink  
IH  
O
(V = 1.0 Vdc)  
O
(V = 1.5 Vdc)  
O
I
Output Drive Current  
mAdc  
OH  
(V  
(V  
(V  
(V  
= 2.5 Vdc)  
= 4.6 Vdc)  
= 9.5 Vdc)  
= 13.5 Vdc)  
5.0  
5.0  
10  
–3.0  
–0.64  
–1.6  
–2.4  
–0.51  
1.3  
3.4  
–5.0  
–1.0  
–2.5  
–10  
–1.7  
0.36  
–0.9  
OH  
OH  
OH  
OH  
15  
–4.2  
2.4  
I
(V = 0.4 Vdc)  
5.0  
10  
15  
0.64  
1.6  
4.2  
0.51  
1.3  
3.4  
1.0  
2.5  
10  
0.36  
0.9  
2.4  
mAdc  
OL  
OL  
(V = 0.5 Vdc)  
OL  
(V = 1.5 Vdc)  
OL  
I
Input Current  
Input Capacitance  
15  
±0.1  
±0.00001  
±0.1  
±1.0  
mAdc  
in  
C
5.0  
7.5  
pF  
in  
(V = 0)  
in  
I
Quiescent Current  
(Per Package)  
5.0  
10  
15  
0.25  
0.5  
1.0  
0.0005  
0.0010  
0.0015  
0.25  
0.5  
1.0  
7.5  
15  
30  
mAdc  
mAdc  
DD  
I
Total Supply Current (Notes 3 and 4)  
(Dynamic plus Quiescent,  
5.0  
10  
15  
I
I
I
= (0.7 mA/kHz) f + I /6  
DD  
T
T
T
T
= (1.4 mA/kHz) f + I /6  
DD  
Per Gate) (C = 50 pF)  
= (2.2 mA/kHz) f + I /6  
L
DD  
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.  
3. The formulas given are for the typical characteristics only at 25°C.  
4. To calculate total supply current at loads other than 50 pF: I (C ) = I (50 pF) + (C 50) Vfk  
T
L
T
L
where: I is in mA (per package), C in pF, V = (V V ) in volts, f in kHz is input frequency, and k = 0.003.  
T
L
DD  
SS  
http://onsemi.com  
3
 
                                          
                                           
12  
16  
20  
                                           
                                           
                                                
0
                                                                     
1
8.0  
−ꢀ6.0  
−ꢀ4.0  
−ꢀ2.0  
−ꢀ0  
0
2.0  
4.0  
8.0  
10  
                                          
MC14007UB  
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25°C)  
L
A
V
Typ  
DD  
Vdc  
(Note 6)  
Symbol  
Characteristic  
Output Rise Time  
Min  
Max  
Unit  
t
ns  
TLH  
t
t
t
= (1.2 ns/pF) C + 30 ns  
5.0  
10  
15  
90  
45  
35  
180  
90  
70  
TLH  
TLH  
TLH  
L
= (0.5 ns/pF) C + 20 ns  
L
= (0.4 ns/pF) C + 15 ns  
L
t
ns  
ns  
ns  
Output Fall Time  
THL  
t
t
t
= (1.2 ns/pF) C + 15 ns  
= (0.5 ns/pF) C + 15 ns  
= (0.4 ns/pF) C + 10 ns  
5.0  
10  
15  
75  
40  
30  
150  
80  
60  
THL  
THL  
THL  
L
L
L
t
TurnOff Delay Time  
PLH  
t
t
t
= (1.5 ns/pF) C + 35 ns  
= (0.2 ns/pF) C + 20 ns  
= (0.15 ns/pF) C + 17.5 ns  
5.0  
10  
15  
60  
30  
25  
125  
75  
55  
PLH  
PLH  
PLH  
L
L
L
t
TurnOn Delay Time  
PHL  
t
t
t
= (1.0 ns/pF) C + 10 ns  
= (0.3 ns/pF) C + 15 ns  
= (0.2 ns/pF) C + 15 ns  
5.0  
10  
15  
60  
30  
25  
125  
75  
55  
PHL  
PHL  
PHL  
L
L
L
5. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.  
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.  
V
= −ꢀV  
14  
V
= V  
DD GS  
DD  
GS  
14  
I
V
= V − V  
DS OH DD  
OH  
I
OL  
V
= V  
DS OL  
7
V
SS  
7
V
SS  
All unused inputs connected to ground.  
All unused inputs connected to ground.  
0
4.0  
8.0  
20  
16  
12  
8.0  
4.0  
0
a
V
= 15 Vdc  
GS  
b
c
c
a
V
= −ꢀ5.0 Vdc  
b
a
GS  
10 Vdc  
a
b
c
T
=
ꢀ55°C  
= +ꢀ25°C  
= +ꢀ125°C  
A
T
A
b
c
T
A
a
b
c
T = −ꢀ55°C  
A
c
b
T
A
= +ꢀ25°C  
b
T
A
= +ꢀ125°C  
c
−ꢀ15 Vdc  
−ꢀ10 Vdc  
a
a
c
b
5.0 Vdc  
6.0  
a
V
, DRAIN VOLTAGE (Vdc)  
V , DRAIN VOLTAGE (Vdc)  
DS  
DS  
Figure 3. Typical Output Source Characteristics  
Figure 4. Typical Output Sink Characteristics  
These typical curves are not guarantees, but are design aids.  
Caution: The maximum current rating is 10 mA per pin.  
http://onsemi.com  
4
 
MC14007UB  
V
I
DD  
20 ns  
20 ns  
V
V
V
V
DD  
SS  
OH  
OL  
0.01 mF  
90%  
50%  
10%  
500ꢁmF  
V
D
CERAMIC  
in  
14  
V
t
t
PLH  
PHL  
V
in  
PULSE  
GENERATOR  
90%  
50%  
10%  
V
out  
V
out  
C
L
7
SS  
t
t
TLH  
THL  
Figure 5. Switching Time and Power Dissipation Test Circuit and Waveforms  
APPLICATIONS  
The MC14007UB dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications.  
Figures 1, 6, and 7 are a few examples of the device flexibility.  
+ꢀV  
V
DD  
DD  
2
OUT = A+BC  
14  
DISABLEꢂ3  
1
13  
11  
11  
2
1
10  
12  
INPUTꢂ10  
12ꢂOUTPUT  
B
OUTPUT  
8
7
9
8
9
5
DISABLEꢂ6  
3
6
7
C
A
4
INPUT  
DISABLE  
OUTPUT  
1
0
X
0
0
1
0
1
OPEN  
Substrates of PChannel devices internally connected to V  
Substrates of NChannel devices internally connected to V  
;
.
DD  
SS  
X = Don’t Care  
Figure 7. AOI Functions Using Tree Logic  
Figure 6. 3State Buffer  
http://onsemi.com  
5
MC14007UB  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC14007UBCP  
PDIP14  
25 Units / Rail  
55 Units / Rail  
MC14007UBCPG  
PDIP14  
(PbFree)  
MC14007UBD  
SOIC14  
MC14007UBDG  
SOIC14  
(PbFree)  
MC14007UBDR2  
SOIC14  
2500 / Tape & Reel  
2000 / Tape & Reel  
MC14007UBDR2G  
SOIC14  
(PbFree)  
MC14007UBFEL  
SOEIAJ14  
MC14007UBFELG  
SOEIAJ14  
(PbFree)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
http://onsemi.com  
6
MC14007UB  
PACKAGE DIMENSIONS  
PDIP14  
CASE 64606  
ISSUE P  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEADS WHEN  
FORMED PARALLEL.  
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.  
5. ROUNDED CORNERS OPTIONAL.  
14  
1
8
7
B
INCHES  
MILLIMETERS  
A
F
DIM  
A
B
C
D
F
MIN  
MAX  
0.770  
0.260  
0.185  
0.021  
0.070  
MIN  
18.16  
6.10  
3.69  
0.38  
1.02  
MAX  
19.56  
6.60  
4.69  
0.53  
1.78  
0.715  
0.240  
0.145  
0.015  
0.040  
L
N
C
G
H
J
K
L
M
N
0.100 BSC  
2.54 BSC  
0.052  
0.008  
0.115  
0.290  
−−−  
0.095  
0.015  
0.135  
0.310  
10  
1.32  
0.20  
2.92  
7.37  
−−−  
0.38  
2.41  
0.38  
3.43  
7.87  
10  
T−  
SEATING  
PLANE  
J
_
_
K
0.015  
0.039  
1.01  
D 14 PL  
H
G
M
M
0.13 (0.005)  
http://onsemi.com  
7
MC14007UB  
PACKAGE DIMENSIONS  
SOIC14  
CASE 751A03  
ISSUE H  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
A−  
14  
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
5. DIMENSION D DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.127  
(0.005) TOTAL IN EXCESS OF THE D  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
B−  
P 7 PL  
M
M
B
0.25 (0.010)  
7
1
G
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN MAX  
F
R X 45  
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55  
3.80  
1.35  
0.35  
0.40  
8.75 0.337 0.344  
4.00 0.150 0.157  
1.75 0.054 0.068  
0.49 0.014 0.019  
1.25 0.016 0.049  
0.050 BSC  
0.25 0.008 0.009  
0.25 0.004 0.009  
T−  
SEATING  
PLANE  
J
M
K
1.27 BSC  
D 14 PL  
0.19  
0.10  
0
M
S
S
0.25 (0.010)  
T
B
A
7
0
7
_
_
_
_
5.80  
0.25  
6.20 0.228 0.244  
0.50 0.010 0.019  
SOLDERING FOOTPRINT*  
7X  
7.04  
14X  
1.52  
1
14X  
0.58  
1.27  
PITCH  
DIMENSIONS: MILLIMETERS  
*For additional information on our PbFree strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
http://onsemi.com  
8
MC14007UB  
PACKAGE DIMENSIONS  
SOEIAJ14  
CASE 96501  
ISSUE A  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD  
FLASH OR PROTRUSIONS AND ARE MEASURED  
AT THE PARTING LINE. MOLD FLASH OR  
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)  
PER SIDE.  
L
14  
8
E
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
H
E
E
_
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT  
INCLUDE DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)  
TOTAL IN EXCESS OF THE LEAD WIDTH  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
DAMBAR CANNOT BE LOCATED ON THE LOWER  
RADIUS OR THE FOOT. MINIMUM SPACE  
BETWEEN PROTRUSIONS AND ADJACENT LEAD  
TO BE 0.46 ( 0.018).  
L
7
1
DETAIL P  
Z
D
MILLIMETERS  
INCHES  
MIN MAX  
−−− 0.081  
VIEW P  
DIM MIN  
MAX  
2.05  
0.20  
0.50  
0.20  
10.50  
5.45  
A
e
A
−−−  
0.05  
0.35  
0.10  
9.90  
5.10  
c
A
1
b
c
0.002  
0.008  
0.020  
0.008  
0.413  
0.215  
0.014  
0.004  
0.390  
0.201  
D
E
e
b
A
1
1.27 BSC  
0.050 BSC  
H
M
7.40  
0.50  
1.10  
8.20  
0.85  
1.50  
0.291  
0.020  
0.043  
0.323  
0.033  
0.059  
0.13 (0.005)  
E
0.10 (0.004)  
0.50  
L
E
M
0
10  
10  
0.035  
0
0.028  
_
_
_
_
Q
1
0.70  
−−−  
0.90  
1.42  
Z
−−− 0.056  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 8002829855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81357733850  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 3036752175 or 8003443860 Toll Free USA/Canada  
Fax: 3036752176 or 8003443867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
MC14007UB/D  

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Dual Complementary Pair Plus Inverter
ONSEMI

MC14007UBFL2

IC,COMPLEMENTARY PAIR AND INVERTER,CMOS,SOP,14PIN,PLASTIC
ONSEMI

MC14007UB_06

Dual Complementary Pair Plus Inverter
ONSEMI

MC14008B

4-Bit Full Adder
MOTOROLA

MC14008B

4-Bit Full Adder
ONSEMI

MC14008BAL

Adder/Subtractor, 4000/14000/40000 Series, 4-Bit, CMOS, CDIP16, 620-09
MOTOROLA

MC14008BALD

暂无描述
MOTOROLA

MC14008BCL

4-Bit Full Adder
MOTOROLA