MC14012B [ONSEMI]
B-Suffix Series CMOS Gates; B-后缀系列CMOS门
| 型号： | MC14012B |
| 厂家： | 
ONSEMI |
| 描述： | B-Suffix Series CMOS Gates |
| 文件： | 总8页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs
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MARKING
DIAGRAMS
14
PDIP–14
P SUFFIX
CASE 646
• Pin–for–Pin Replacements for Corresponding CD4000 Series B
MC14012BCP
AWLYYWW
Suffix Devices
1
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
14
Symbol
Parameter
Value
Unit
V
SOIC–14
D SUFFIX
CASE 751A
14012B
AWLYWW
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
1
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
14
SOEIAJ–14
F SUFFIX
CASE 965
P
Power Dissipation,
per Package (Note 3.)
500
mW
D
MC14012B
AWLYWW
T
A
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
1
T
stg
T
Lead Temperature
(8–Second Soldering)
L
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
2. Maximum Ratings are those values beyond which damage to the device
may occur.
WW or W = Work Week
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
ORDERING INFORMATION
Device
Package
PDIP–14
SOIC–14
Shipping
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
MC14012BCP
MC14012BD
2000/Box
55/Rail
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
MC14012BDR2
MC14012BF
SOIC–14 2500/Tape & Reel
SOEIAJ–14
SOEIAJ–14
See Note 1.
See Note 1.
MC14012BFEL
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
April, 2000 – Rev. 3
MC14012B/D
MC14012B
MC14012B
Dual 4–Input NAND Gate
OUT
1
2
3
4
5
6
7
14
V
DD
A
2
3
4
5
IN 1
13 OUT
1
A
B
IN 2
12 IN 4
B
A
9
IN 3
11 IN 3
B
A
10
11
12
13
IN 4
10 IN 2
B
A
NC
9
8
IN 1
B
NC = 6, 8
= PIN 14
V
SS
NC
V
DD
V
SS
= PIN 7
NC = NO CONNECTION
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
– 0.88
– 2.25
– 8.8
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (0.3 µA/kHz) f + I /N
T DD
I = (0.6 µA/kHz) f + I /N
T DD
I = (0.9 µA/kHz) f + I /N
T
(Dynamic plus Quiescent,
Per Gate, C = 50 pF)
L
DD
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
T
L
DD
SS
package.
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2
MC14012B
B–SERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
(8.)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time
t
ns
TLH
t
t
t
= (1.35 ns/pF) C + 33 ns
L
TLH
TLH
TLH
5.0
10
15
—
—
—
100
50
40
200
100
80
= (0.60 ns/pF) C + 20 ns
L
= (0.40 ns/PF) C + 20 ns
L
Output Fall Time
t
ns
ns
THL
t
t
t
= (1.35 ns/pF) C + 33 ns
L
= (0.60 ns/pF) C + 20 ns
= (0.40 ns/pF) C + 20 ns
THL
THL
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
L
L
Propagation Delay Time
t
, t
PLH PHL
t
t
t
, t
= (0.90 ns/pF) C + 115 ns
= (0.36 ns/pF) C + 47 ns
L
5.0
10
15
—
—
—
160
65
50
300
130
100
PLH PHL
L
, t
PLH PHL
, t
= (0.26 ns/pF) C + 37 ns
PLH PHL
L
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
INPUT
20 ns
14
V
DD
V
DD
90%
50%
10%
INPUT
*
0 V
PULSE
GENERATOR
OUTPUT
t
t
PLH
PHL
90%
50%
10%
V
OH
C
L
OUTPUT
V
OL
INVERTING
t
t
TLH
THL
t
t
PHL
PLH
V
OH
7
V
SS
OUTPUT
90%
50%
10%
NON–INVERTING
V
OL
* All unused inputs of AND, NAND gates must be connected to V
.
DD
t
t
THL
TLH
All unused inputs of OR, NOR gates must be connected to V
.
SS
Figure 1. Switching Time Test Circuit and Waveforms
CIRCUIT SCHEMATIC
MC14012B
One of Two Gates Shown
V
DD
14
V
DD
2, 9
*
3, 10
V
SS
1, 13
4, 11
5, 12
SAME AS
ABOVE
7
V
SS
* Inverter omitted
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3
MC14012B
TYPICAL B–SERIES GATE CHARACTERISTICS
N–CHANNEL DRAIN CURRENT (SINK)
P–CHANNEL DRAIN CURRENT (SOURCE)
– 10
5.0
4.0
3.0
– 9.0
– 8.0
– 7.0
– 6.0
– 5.0
– 4.0
T = – 55°C
A
T = – 55°C
A
– 40°C
– 40°C
+ 25°C
+ 25°C
+ 85°C
+ 85°C
2.0
1.0
+ 125°C
– 3.0
– 2.0
– 1.0
0
+ 125°C
0
0
1.0
2.0
3.0
4.0
5.0
0
– 1.0
– 2.0
V , DRAIN–TO–SOURCE VOLTAGE (Vdc)
DS
– 3.0
– 4.0
– 5.0
V , DRAIN–TO–SOURCE VOLTAGE (Vdc)
DS
Figure 2. VGS = 5.0 Vdc
Figure 3. VGS = – 5.0 Vdc
20
18
16
14
12
10
8.0
– 50
– 45
– 40
– 35
– 30
– 25
– 20
T = – 55°C
A
– 40°C
+ 25°C
+ 85°C
T = – 55°C
A
– 40°C
+ 125°C
+ 25°C
+ 85°C
6.0
4.0
2.0
0
– 15
– 10
– 5.0
0
+ 125°C
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
0 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0 – 6.0 – 7.0 – 8.0 – 9.0 – 10
V , DRAIN–TO–SOURCE VOLTAGE (Vdc)
DS
V , DRAIN–TO–SOURCE VOLTAGE (Vdc)
DS
Figure 4. VGS = 10 Vdc
Figure 5. VGS = – 10 Vdc
50
45
40
35
30
25
20
– 100
– 90
– 80
– 70
– 60
– 50
– 40
T = – 55°C
A
– 40°C
+ 25°C
T = – 55°C
A
– 40°C
+ 85°C
+ 85°C
+ 25°C
+ 125°C
15
10
5.0
0
– 30
– 20
– 10
0
+ 125°C
0
2.0 4.0 6.0 8.0 10
12
14
16
18
20
0
– 2.0 – 4.0 – 6.0 – 8.0 – 10 – 12 – 14 – 16 – 18 – 20
V , DRAIN–TO–SOURCE VOLTAGE (Vdc)
DS
V , DRAIN–TO–SOURCE VOLTAGE (Vdc)
DS
Figure 6. VGS = 15 Vdc
Figure 7. VGS = – 15 Vdc
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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4
MC14012B
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
5.0
10
8.0
6.0
4.0
3.0
2.0
1.0
0
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
4.0
2.0
0
0
1.0
2.0
3.0
4.0
5.0
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
V , INPUT VOLTAGE (Vdc)
in
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
16
14
12
10
DC NOISE MARGIN
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V and V for the output(s) to
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
IL
IH
be at a fixed voltage V are given in the Electrical
O
8.0
6.0
Characteristics table. V and V are presented graphically
IL
IH
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
4.0
2.0
0
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
Figure 10. VDD = 15 Vdc
V
out
V
DD
V
out
V
DD
V
O
V
O
V
O
V
O
V
DD
V
DD
0
V
in
0
V
in
V
IL
V
IH
V
IL
V
IH
V
SS
= 0 VOLTS DC
(a) Inverting Function
(b) Non–Inverting Function
Figure 11. DC Noise Immunity
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5
MC14012B
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
8
7
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
INCHES
DIM MIN MAX
0.770 18.16
MILLIMETERS
A
F
MIN
MAX
18.80
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
0.260
0.185
0.021
0.070
6.10
3.69
0.38
1.02
L
N
C
G
H
J
K
L
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
–––
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
–––
2.41
0.38
3.43
7.87
10
–T–
SEATING
PLANE
J
K
M
N
0.015
0.039
0.38
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
14
1
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
–T–
SEATING
PLANE
J
M
G
J
K
M
P
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
M
S
S
0.25 (0.010)
T B
A
7
0
5.80
0.25
6.20 0.228
0.50 0.010
0.244
0.019
R
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6
MC14012B
PACKAGE DIMENSIONS
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 965–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
14
8
Q
1
H
E
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
A
e
DIM MIN
MAX
2.05
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
e
H
E
0.50
A
b
1
M
1.27 BSC
0.050 BSC
0.13 (0.005)
0.10 (0.004)
7.40
0.50
1.10
0
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
1.42 –––
0.323
0.033
0.059
10
0.035
0.056
L
E
M
0
Q
Z
0.70
–––
1
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7
MC14012B
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