MC14014BDR2G_技术文档

MC14014B, MC14021B

8−Bit Static Shift Register

The MC14014B and MC14021B 8−bit static shift registers are

constructed with MOS P−channel and N−channel enhancement mode

devices in a single monolithic structure. These shift registers find primary

use in parallel−to−serial data conversion, synchronous and asynchronous

parallel input, serial output data queueing; and other general purpose

register applications requiring low power and/or high noise immunity.

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MARKING

Features

DIAGRAMS

• Synchronous Parallel Input/Serial Output (MC14014B)

• Asynchronous Parallel Input/Serial Output (MC14021B)

• Synchronous Serial Input/Serial Output

• Full Static Operation

16

1

PDIP−16

P SUFFIX

CASE 648

MC140xxBCP

AWLYYWW

• “Q” Outputs from Sixth, Seventh, and Eighth Stages

• Double Diode Input Protection

16

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

SOIC−16

D SUFFIX

CASE 751B

140xxB

AWLYWW

• Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range

• MC14014B Pin−for−Pin Replacement for CD4014B

1

• MC14021B Pin−for−Pin Replacement for CD4021B

• Pb−Free Packages are Available*

16

SOEIAJ−16

F SUFFIX

CASE 966

MC140xxB

AWLYWW

MAXIMUM RATINGS (Voltages Referenced to V

)

SS

1

Symbol

Parameter

Value

−0.5 to +18.0

Unit

V

DD

DC Supply Voltage Range

V , V

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

V

in out

DD

xx

A

WL, L

YY, Y

= Specific Device Code

= Assembly Location

= Wafer Lot

I , I

in out

Input or Output Current

(DC or Transient) per Pin

±10

mA

= Year

WW, W = Work Week

P

D

Power Dissipation, per Package

(Note 1)

500

mW

T

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

A

ORDERING INFORMATION

See detailed ordering and shipping information in the package

T

stg

T

Lead Temperature

L

dimensions section on page 6 of this data sheet.

(8−Second Soldering)

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V and V should be constrained

in

out

to the range V v (V or V ) v V

.

SS

in

out

DD

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

SS

DD

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2005

1

Publication Order Number:

February, 2005 − Rev. 5

MC14014B/D

MC14014B, MC14021B

TRUTH TABLE

SERIAL OPERATION:

Q6

P/S t=n+6

Q7

Q8

t

Clock D

S

t=n+7 t=n+8

n

0

1

0

1

?

0

1

0

?

0

1

n+1

n+2

n+3

1

0

1

X

0

Q6

Q7

Q8

PARALLEL OPERATION:

Clock

MC14014B MC14021B

D

P/S

P

*Q

0

S

n

X

1

0

X

1

*Q6, Q7, & Q8 are available externally

X = Don’t Care

PIN ASSIGNMENT

P8

Q6

Q8

P4

P3

P2

P1

1

2

3

4

5

6

7

8

16

V

DD

15 P7

14 P6

13 P5

12 Q7

11

10

9

D

C

S

V

SS

P/S

LOGIC DIAGRAM

P1

P2

P3

P6

P7

P8

7

6

5

14

15

1

9

P/S

11

D

S

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

10

CLOCK

V

= PIN 16

= PIN 8

P4 = PIN 4

P5 = PIN 13

DD

2

12

3

V

SS

Q6

Q7

Q8

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2

MC14014B, MC14021B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

SS

− 55_C

25_C

Typ

125_C

Characteristic

Symbol

Unit

Min

Max

Min

Max

Min

Max

V

DD

(Note 2)

Vdc

Output Voltage

“0” Level

“1” Level

“0” Level

V

5.0

10

15

−

0.05

−

0

0.05

−

0.05

Vdc

OL

V

in

= V or 0

DD

V

OH

5.0

10

15

4.95

9.95

14.95

−

4.95

9.95

14.95

5.0

10

15

−

4.95

9.95

14.95

−

Vdc

V

in

= 0 or V

DD

Input Voltage

(V = 4.5 or 0.5 Vdc)

V

IL

5.0

10

15

−

1.5

3.0

4.0

−

2.25

4.50

6.75

1.5

3.0

4.0

−

1.5

3.0

4.0

O

(V = 9.0 or 1.0 Vdc)

O

(V = 13.5 or 1.5 Vdc)

O

V

IH

5.0

10

15

3.5

7.0

11

−

3.5

7.0

11

2.75

5.50

8.25

−

3.5

7.0

11

−

Vdc

(V = 0.5 or 4.5 Vdc) “1” Level

O

(V = 1.0 or 9.0 Vdc)

O

(V = 1.5 or 13.5 Vdc)

O

Output Drive Current

I

mAdc

OH

(V = 2.5 Vdc)

Source

Sink

5.0

10

– 3.0

– 0.64

– 1.6

– 4.2

−

– 2.4

– 0.51

− 1.3

− 3.4

– 4.2

– 0.88

– 2.25

− 8.8

−

– 1.7

− 0.36

– 0.9

− 2.4

−

OH

(V = 4.6 Vdc)

OH

(V = 9.5 Vdc)

OH

(V = 13.5 Vdc)

OH

15

(V = 0.4 Vdc)

I

OL

5.0

10

15

0.64

1.6

4.2

−

0.51

1.3

3.4

0.88

2.25

8.8

−

0.36

0.9

2.4

−

mAdc

OL

(V = 0.5 Vdc)

OL

(V = 1.5 Vdc)

OL

Input Current

Input Capacitance

I

15

−

± 0.1

−

±0.00001

± 0.1

−

± 1.0

mAdc

in

C

−

5.0

7.5

−

pF

in

(V = 0)

in

Quiescent Current

(Per Package)

I

5.0

10

15

−

5.0

10

15

−

0.005

0.010

0.015

5.0

10

15

−

150

300

600

mAdc

DD

Total Supply Current (Notes 3 & 4)

(Dynamic plus Quiescent,

Per Package)

I

T

5.0

10

15

I = (0.75 mA/kHz) f + I

T

DD

I = (1.50 mA/kHz) f + I

T

I = (2.25 mA/kHz) f + I

T

(C = 50 pF on all outputs, all

L

buffers switching)

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

I (C ) = I (50 pF) + (C − 50) Vfk

T

L

T

L

where: I is in mA (per package), C in pF, V = (V − V ) in volts, f in kHz is input frequency, and k = 0.0015.

T

L

DD

SS

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3

MC14014B, MC14021B

SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)

L

A

Characteristic

Symbol

V

DD

Min

Typ

Max

Unit

Vdc

(Note 6)

ns

Output Rise and Fall Time

t

,

TLH

−

t

, t

= (1.5 ns/pF) C + 25 ns

= (0.75 ns/pF) C + 12.5 ns

L

t

THL

5.0

10

15

100

50

40

200

100

80

TLH THL

L

, t

TLH THL

, t

= (0.55 ns/pF) C + 9.5 ns

TLH THL

L

ns

Propagation Delay Time (Clock to Q, P/S to Q)

t

,

PLH

t

, t

= (1.7 ns/pF) C + 315 ns

t

PHL

5.0

10

15

−

400

170

115

800

340

230

PHL PLH

L

, t

= (0.66 ns/pF) C + 137 ns

L

PHL PLH

, t

= (0.5 ns/pF) C + 90 ns

L

PHL PLH

Clock Pulse Width

t

−

ns

MHz

ns

5.0

10

15

400

175

135

150

75

WH

40

Clock Frequency

f

cl

−

5.0

10

15

3.0

6.0

8.0

1.5

3.0

4.0

Parallel/Serial Control Pulse Width

t

−

5.0

10

15

400

175

135

150

75

WH

40

t

su

−

ns

Setup Time

P/S to Clock

5.0

10

15

200

100

80

100

50

40

t

h

−

ns

Hold Time

5.0

10

15

20

25

– 2.5

– 10

0

Clock to P/S

t

su

−

ns

Setup Time

5.0

10

15

350

80

150

50

Data (Parallel or Serial) to

Clock or P/S

60

30

t

h

−

ns

Hold Time

5.0

10

15

45

35

0

5

Clock to D

s

t

h

−

ns

Hold Time

Clock to P

5.0

10

15

50

45

25

20

n

Input Clock Rise Time

t

−

ms

5.0

10

15

5

r(cl)

4

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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4

MC14014B, MC14021B

V

DD

V

out

V

DD

V

out

P/S Q6

C

P/S Q6

C

PULSE

GENERATOR

P6

Q7

P7

P8

P7

P8

I

OL

OH

D

S

Q8

D

S

Q8

EXTERNAL

POWER

SUPPLY

EXTERNAL

POWER

SUPPLY

Preset output under test to a logic “1” level.

Figure 1. Output Source Current Test Circuit

Figure 2. Output Sink Current Test Circuit

V

DD

500 mF

I

D

0.01 mF

CERAMIC

P/S

C

PULSE

Q6

Q7

Q8

GENERATOR 1

P1

P2

C

L

P3

P4

P5

P6

P7

P8

C

L

PULSE

D

S

GENERATOR 2

C

L

V

SS

1

f

CLOCK

DATA

50%

Figure 3. Power Dissipation Test Circuit and Waveform

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5

MC14014B, MC14021B

SW 1

V

DD

1

V

DD

PULSE

20 ns

90%

20 ns

V

GENERATOR 1

PARALLEL OR

SERIAL DATA

INPUT

DD

2

P/S

C

50%

10%

t

Q6

Q7

Q8

V

SS

P1

P2

P3

P4

P5

P6

P7

P8

su

2

1

2

1

PULSE

t

THL

WH

GENERATOR 2

V

DD

CLOCK OR P/S

INPUT

90%

50%

10%

SS

C

L

t

WL

WH

t

PHL

V

PLH

OH

Q

90%

50%

10%

D

S

OUTPUT

V

SWITCH POSITION 1 = PARALLEL IN

SWITCH POSITION 2 = SERIAL IN

OL

V

SS

SW 2

t

THL

TLH

t = t = 50% DUTY CYCLE

WL WH

Figure 4. Switching Time Test Circuit and Waveforms

ORDERING INFORMATION

Device

†

Package

Shipping

MC14014BCP

PDIP−16

500 Units / Rail

MC14014BCPG

PDIP−16

(Pb−Free)

MC14014BD

SOIC−16

48 Units / Rail

MC14014BDG

SOIC−16

(Pb−Free)

MC14014BDR2

SOIC−16

2500 Units / Tape & Reel

MC14014BDR2G

SOIC−16

(Pb−Free)

MC14014BF

SOEIAJ−16

50 Units / Rail

MC14014BFEL

2000 Units / Tape & Reel

MC14021BCP

PDIP−16

500 Units / Rail

MC14021BCPG

PDIP−16

(Pb−Free)

MC14021BD

SOIC−16

48 Units / Rail

MC14021BDG

SOIC−16

(Pb−Free)

MC14021BDR2

SOIC−16

2500 Units / Tape & Reel

MC14021BDR2G

SOIC−16

(Pb−Free)

MC14021BF

SOEIAJ−16

50 Units / Rail

MC14021BFEL

2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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6

MC14014B, MC14021B

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648−08

ISSUE T

NOTES:

−A−

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

16

1

9

8

B

S

5. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

0.740 0.770 18.80 19.55

MILLIMETERS

F

C

L

MIN MAX

A

B

C

D

F

0.250 0.270

0.145 0.175

0.015 0.021

6.35

3.69

0.39

1.02

6.85

4.44

0.53

1.77

SEATING

PLANE

−T−

0.040

0.70

G

H

J

K

L

0.100 BSC

2.54 BSC

1.27 BSC

K

M

H

J

0.050 BSC

0.008 0.015

0.110 0.130

0.295 0.305

G

0.21

0.38

3.30

7.74

10

D 16 PL

2.80

7.50

0

M

0.25 (0.010)

T

A

M

S

0

10

_

0.020 0.040

0.51

1.01

SOIC−16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−A−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

16

9

8

−B−

P 8 PL

M

S

B

0.25 (0.010)

1

MILLIMETERS

INCHES

MIN

G

DIM MIN

MAX

10.00

4.00

1.75

0.49

1.25

MAX

0.393

0.157

0.068

0.019

0.049

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

0.386

0.150

0.054

0.014

0.016

F

R X 45

K

_

G

J

1.27 BSC

0.050 BSC

C

0.19

0.10

0

0.25

7

0.008

0.004

0

0.009

7

−T−

SEATING

PLANE

K

M

P

R

J

_

M

5.80

0.25

6.20

0.50

0.229

0.010

0.244

0.019

D

16 PL

M

S

0.25 (0.010)

T

B

A

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7

MC14014B, MC14021B

PACKAGE DIMENSIONS

SOEIAJ−16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966−01

ISSUE O

NOTES:

ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

16

9

L

E

ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.

ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

Q

1

H

E

M

_

E

ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

1

8

L

ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

DETAIL P

Z

D

VIEW P

e

A

c

MILLIMETERS

INCHES

MIN

−−−

DIM MIN

MAX

0.081

0.008

0.020

0.011

0.413

0.215

A

−−−

0.05

0.35

0.18

9.90

5.10

2.05

A

1

0.20 0.002

0.50 0.014

0.27 0.007

1

b

0.13 (0.005)

b

c

0.10 (0.004)

M

D

E

10.50

5.45 0.201

0.390

e

1.27 BSC

0.050 BSC

H

7.40

0.50

1.10

8.20 0.291

0.85 0.020

1.50 0.043

0.323

0.033

0.059

E

L

E

0

10

0.90 0.028

10

_

0.035

0.031

M

Q

0

_

0.70

−−−

1

Z

0.78

−−−

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

Literature Distribution Center for ON Semiconductor

P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada

Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

For additional information, please contact your

local Sales Representative.

MC14014B/D

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8


型号：	MC14014BDR2G
厂家：	ONSEMI
描述：	8-Bit Static Shift Register 8位的静态移位寄存器移位寄存器触发器逻辑集成电路光电二极管
文件：	总8页 (文件大小：104K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC14014BDR2G [ONSEMI]

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