概述
数据手册MC14040B_05 概述
12−Bit Binary Counter 12位二进制计数器
MC14040B_05 数据手册
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PDF下载MC14040B
12−Bit Binary Counter
The MC14040B 12−stage binary counter is constructed with MOS
P−Channel and N−Channel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripple−carry binary counter. The device
advances the count on the negative−going edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency−driving circuits.
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MARKING
DIAGRAMS
Features
16
1
• Fully Static Operation
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
PDIP−16
P SUFFIX
CASE 648
MC14040BCP
AWLYYWWG
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• Common Reset Line
16
SOIC−16
D SUFFIX
CASE 751B
14040BG
AWLYWW
• Pin−for−Pin Replacement for CD4040B
• Pb−Free Packages are Available*
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
16
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
14
040B
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
V
DC Supply Voltage Range
DD
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
1
I , I
Input or Output Current
(DC or Transient) per Pin
10
mA
in out
16
1
SOEIAJ−16
F SUFFIX
CASE 966
P
T
Power Dissipation, per Package
(Note 1)
500
mW
MC14040B
ALYWG
D
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
T
stg
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
T
Lead Temperature
(8−Second Soldering)
L
= Year
WW, W = Work Week
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
G
= Pb−Free Indicator
1. Temperature Derating:
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
DD
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 7
MC14040B/D
MC14040B
PIN ASSIGNMENT
Q12
Q6
Q5
Q7
Q4
Q3
Q2
1
2
3
4
5
6
7
8
16
V
DD
15 Q11
14 Q10
13 Q8
12 Q9
TRUTH TABLE
Clock
Reset
Output State
0
0
1
No Change
Advance to next state
All Outputs are low
X
11
10
9
R
X = Don’t Care
C
V
Q1
SS
LOGIC DIAGRAM
Q1
Q2
Q3
Q10
Q11
15
Q12
9
7
6
14
1
CLOCK
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
C
C
Q
10
R
R
R
R
R
R
RESET
11
Q4 = PIN 5
Q5 = PIN 3
Q6 = PIN 2
Q7 = PIN 4
Q8 = PIN 13
Q9 = PIN 12
V
= PIN 16
= PIN 8
DD
SS
V
ORDERING INFORMATION
Device
†
Package
Shipping
MC14040BCP
PDIP−16
500 Units / Rail
500 Units / Rail
MC14040BCPG
PDIP−16
(Pb−Free)
MC14040BD
SOIC−16
48 Units / Rail
48 Units / Rail
MC14040BDG
SOIC−16
(Pb−Free)
MC14040BDR2
SOIC−16
2500 Units / Tape & Reel
2500 Units / Tape & Reel
MC14040BDR2G
SOIC−16
(Pb−Free)
MC14040BDT
MC14040BDTR2
MC14040BFEL
TSSOP−16*
TSSOP−16*
SOEIAJ−16
96 Units / Rail
2500 Units / Tape & Reel
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC14040B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
125_C
V
Vdc
DD
Characteristic
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
(Note 2)
Output Voltage
“0” Level
“1” Level
“0” Level
V
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
OL
V
in
= V or 0
DD
V
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
OH
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
V
Vdc
“1” Level
IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
(V = 0.5 or 4.5 Vdc)
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
OH
OH
OH
OH
15
(V = 0.4 Vdc)
(V = 0.5 Vdc)
(V = 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
OL
OL
OL
Input Current
Input Capacitance
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
in
C
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
mAdc
DD
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
I
5.0
10
15
I
I
I
= (0.42 mA/kHz) f + I
= (0.85 mA/kHz) f + I
= (1.43 mA/kHz) f + I
T
T
T
T
DD
DD
DD
(C = 50 pF on all outputs, all
L
buffers switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in mA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.001.
T
L
DD
SS
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3
MC14040B
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)
L
A
Characteristic
Symbol
V
Min
Typ
Max
Unit
DD
Vdc
(Note 6)
Output Rise and Fall Time
t
,
ns
TLH
T
T
T
, T
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
L
t
THL
5.0
10
15
−
−
−
100
50
40
200
100
80
TLH THL
L
, T
TLH THL
, T
TLH THL
= (0.55 ns/pF) C + 9.5 ns
L
Propagation Delay Time
Clock to Q1
t
t
,
PLH
ns
ns
ns
PHL
t
t
t
, t
= (1.7 ns/pF) C + 315 ns
= (0.66 ns/pF) C + 137 ns
= (0.5 ns/pF) C + 95 ns
5.0
10
15
−
−
−
260
115
80
520
230
160
PHL PLH
L
, t
PHL PLH
L
, t
PHL PLH
L
Clock to Q12
5.0
10
15
−
−
−
1625
720
500
3250
1440
1000
t
t
t
, t
= (1.7 ns/pF) C + 2415 ns
= (0.66 ns/pF) C + 867 ns
L
= (0.5 ns/pF) C + 475 ns
L
PHL PLH L
, t
PHL PLH
, t
PHL PLH
Propagation Delay Time
Reset to Q
t
PHL
n
t
t
t
= (1.7 ns/pF) C + 485 ns
5.0
10
15
−
−
−
370
155
115
740
310
230
PHL
PHL
PHL
L
= (0.86 ns/pF) C + 182 ns
L
= (0.5 ns/pF) C + 145 ns
L
Clock Pulse Width
t
5.0
10
15
385
150
115
140
55
38
−
−
−
ns
MHz
ns
WH
Clock Pulse Frequency
Clock Rise and Fall Time
Reset Pulse Width
f
5.0
10
15
−
−
−
2.1
7.0
10.0
1.5
3.5
4.5
cl
t
, t
5.0
10
15
TLH THL
No Limit
t
t
5.0
10
15
960
360
270
320
120
80
−
−
−
ns
WH
rem
Reset Removal Time
5.0
10
15
130
50
30
65
25
15
−
−
−
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
V
DD
0.01 mF
CERAMIC
PULSE
GENERATOR
500 mF
I
D
C
Q1
Q2
C
L
Q
n
R
C
L
PULSE
GENERATOR
C
Q1
Q2
C
L
V
SS
C
L
Q
n
R
C
L
C
L
V
20 ns
20 ns
SS
CLOCK
90%
50%
10%
t
WH
20 ns
20 ns
t
t
PHL
PLH
V
V
DD
SS
90%
50%
10%
CLOCK
90%
50%
10%
Q
50% DUTY CYCLE
t
t
THL
TLH
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
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4
MC14040B
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
CLOCK
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Figure 3. Timing Diagram
APPLICATIONS INFORMATION
TIME−BASE GENERATOR
outputs Q5, Q10, Q11, and Q12 division by 3600 is
accomplished. The MC14012B decodes the counter
outputs, produces a single output pulse, and resets the binary
counter. The resulting output frequency is 1.0 pulse/minute.
A 60 Hz sinewave obtained through a 1.0 Megohm
resistor connected directly to a standard 120 Vac power line
is applied to the clock input of the MC14040B. By selecting
V
V
CC
CC
1/6 of HC14A
MC14040B
Clock
1.0M
13
12
10
9
Q5
Q10
Q11
Q12
1.0 Pulse/Minute
Output
1
2
4
5
≥20pF
8
6
120Vac
60Hz
1/2
14012B
1/2
14012B
NOTE: Ground MUST be isolated
by a transformer or
opto−isolator for safety
reasons.
Figure 4. Time−Base Generator
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5
MC14040B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T
B
A
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6
MC14040B
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16X KREF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
U
0.15 (0.006) T
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T
U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
D
F
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
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7
MC14040B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE O
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
16
9
E
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
Q
1
H
E
E
M
_
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.27
10.50
5.45
A
−−−
0.05
0.35
0.18
9.90
5.10
A
A
1
0.002
0.008
0.020
0.011
0.413
0.215
1
b
0.13 (0.005)
b
c
0.014
0.007
0.390
0.201
0.10 (0.004)
M
D
E
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
0
10
10
0.035
M
Q
0
0.028
_
_
_
_
0.70
−−−
0.90
0.78
1
Z
−−− 0.031
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
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Order Literature: http://www.onsemi.com/litorder
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
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Email: orderlit@onsemi.com
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For additional information, please contact your
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MC14040B/D
MC14040B_05 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MC14042 | ONSEMI | Quad Transparent Latch | 获取价格 |
|
| MC14042B | ONSEMI | Quad Transparent Latch | 获取价格 |
|
| MC14042B | MOTOROLA | QUAD TRANSPARENT LATCH | 获取价格 |
|
| MC14042BAL | MOTOROLA | D Latch, 4000/14000/40000 Series, 1-Func, High Level Triggered, 4-Bit, Complementary Output, CMOS, CDIP16, 620-09 | 获取价格 |
|
| MC14042BALD | MOTOROLA | 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16, 620-09 | 获取价格 |
|
| MC14042BALDS | MOTOROLA | 暂无描述 | 获取价格 |
|
| MC14042BALS | MOTOROLA | IC,LATCH,QUAD,1-BIT,CMOS,DIP,16PIN,CERAMIC | 获取价格 |
|
| MC14042BCL | MOTOROLA | QUAD TRANSPARENT LATCH | 获取价格 |
|
| MC14042BCLD | MOTOROLA | D Latch, 4000/14000/40000 Series, 1-Func, High Level Triggered, 4-Bit, Complementary Output, CMOS, CDIP16, 620-09 | 获取价格 |
|
| MC14042BCLDS | MOTOROLA | 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16, 620-09 | 获取价格 |
|
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