MC14067BDWR2 [ONSEMI]

Analog Multiplexers/Demultiplexers; 模拟多路复用器/多路解复用器
MC14067BDWR2
型号: MC14067BDWR2
厂家: ONSEMI    ONSEMI
描述:

Analog Multiplexers/Demultiplexers
模拟多路复用器/多路解复用器

解复用器 开关 复用器或开关 信号电路 光电二极管
文件: 总12页 (文件大小:242K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
The MC14067 multiplexer/demultiplexer is a digitally controlled  
analog switch featuring low ON resistance and very low leakage  
current. This device can be used in either digital or analog  
applications.  
http://onsemi.com  
The MC14067 is a 16–channel multiplexer/demultiplexer with an  
inhibit and four binary control inputs A, B, C, and D. These control  
inputs select 1–of–16 channels by turning ON the appropriate analog  
switch (see MC14067 truth table.)  
MARKING  
DIAGRAMS  
24  
PDIP–24  
P SUFFIX  
CASE 709  
Low OFF Leakage Current  
MC14067BCP  
AWLYYWW  
Matched Channel Resistance  
Low Quiescent Power Consumption  
Low Crosstalk Between Channels  
Wide Operating Voltage Range: 3 to 18 V  
Low Noise  
1
24  
SOIC–24  
DW SUFFIX  
CASE 751E  
14067B  
AWLYYWW  
Pin for Pin Replacement for CD4067B  
1
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 1.)  
SS  
Symbol  
Parameter  
Value  
Unit  
V
V
DD  
DC Supply Voltage Range  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage Range  
(DC or Transient)  
– 0.5 to V + 0.5  
V
ORDERING INFORMATION  
in out  
DD  
Device  
Package  
PDIP–24  
SOIC–24  
Shipping  
I
in  
Input Current (DC or Transient),  
per Control Pin  
± 10  
mA  
MC14067BCP  
MC14067BDW  
MC14067BDWR2  
15/Rail  
30/Rail  
I
sw  
Switch Through Current  
± 25  
mA  
SOIC–24 1000/Tape & Reel  
P
D
Power Dissipation,  
500  
mW  
per Package (Note 2.)  
T
Ambient Temperature Range  
Storage Temperature Range  
– 55 to + 125  
– 65 to + 150  
260  
C
C
C
A
T
stg  
T
Lead Temperature  
L
(8–Second Soldering)  
1. Maximum Ratings are those values beyond which damage to the device  
may occur.  
2. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high–impedancecircuit. For proper operation, V and V should be constrained  
in  
out  
to the range V  
(V or V  
)
V
DD  
.
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 3  
MC14067B/D  
MC14067B  
MC14067 TRUTH TABLE  
Control Inputs  
Selected  
Channel  
A
B
C
D
Inh  
X
0
1
0
X
0
0
1
X
0
0
0
X
0
0
0
1
0
0
0
None  
X0  
X1  
X2  
1
0
1
0
1
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
X3  
X4  
X5  
X6  
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
X7  
X8  
X9  
X10  
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
X11  
X12  
X13  
X14  
X15  
MC14067B  
PIN ASSIGNMENT  
X
X7  
X6  
X5  
X4  
X3  
1
2
3
4
5
6
24  
V
DD  
23 X8  
22 X9  
21 X10  
20 X11  
19 X12  
X2  
X1  
X0  
A
7
18 X13  
17 X14  
16 X15  
15 INHIBIT  
8
9
10  
11  
12  
B
14  
13  
C
D
V
SS  
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2
MC14067B  
MC14067B  
16–Channel Analog  
Multiplexer/Demultiplexer  
15  
10  
11  
14  
13  
9
INHIBIT  
A
B
C
CONTROLS  
D
X0  
8
X1  
7
X2  
6
X3  
5
4
X4  
X5  
COMMON  
OUT/IN  
X
1
3
X6  
2
X7  
X8  
SWITCHES  
IN/OUT  
23  
22  
21  
20  
19  
18  
17  
16  
X9  
V
DD  
= PIN 24  
X10  
X11  
X12  
X13  
X14  
X15  
V
SS  
= PIN 12  
MC14067 FUNCTIONAL DIAGRAM  
INHIBIT  
A
CONTROL  
INPUTS  
B
C
D
1–OF–16 DECODER  
X0  
X1  
X2  
X3  
X4  
X5  
X6  
X
X7  
X
X8  
X9  
IN/OUT  
OUT/IN  
X10  
X11  
X12  
X13  
X14  
X15  
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3
MC14067B  
ELECTRICAL CHARACTERISTICS  
– 55°C  
Min Max Min  
25 C  
125 C  
(3.)  
Characteristic  
Symbol  
V
DD  
Test Conditions  
Unit  
Typ  
Max Min Max  
SUPPLY REQUIREMENTS (Voltages Referenced to V  
)
SS  
Power Supply Voltage  
Range  
V
DD  
3.0  
18  
3.0  
18  
3.0  
18  
V
Quiescent Current Per  
Package  
I
5.0 Control Inputs: V  
5.0  
10  
20  
0.005  
0.010  
0.015  
5.0  
10  
20  
150  
300  
600  
µA  
DD  
in =  
10  
V
SS  
or V  
,
DD  
15 Switch I/O: V  
V
SS  
I/O  
V
V  
, and  
DD  
(4.)  
500 mV  
switch  
Total Supply Current  
(Dynamic Plus  
Quiescent,  
I
5.0 T = 25 C only (The  
µA  
D(AV)  
A
(0.07 µA/kHz) f + I  
(0.20 µA/kHz) f + I  
(0.36 µA/kHz) f + I  
DD  
DD  
DD  
10  
15  
channel component,  
(V – V )/R , is  
Typical  
in  
out  
on  
Per Package  
not included.)  
CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to V  
)
SS  
Low–Level Input Voltage  
V
5.0  
10  
15  
R
= per spec,  
on  
= per spec  
1.5  
3.0  
4.0  
2.25  
4.50  
6.75  
1.5  
3.0  
4.0  
1.5  
3.0  
4.0  
V
V
IL  
IH  
in  
I
off  
High–Level Input Voltage  
V
5.0  
10  
15  
R
= per spec,  
3.5  
7.0  
11  
3.5  
7.0  
11  
2.75  
5.50  
8.25  
3.5  
7.0  
11  
on  
I
off  
= per spec  
Input Leakage Current  
Input Capacitance  
I
15  
V
in  
= 0 or V  
± 0.1  
±0.00001 ± 0.1  
1.0  
µA  
DD  
C
5.0  
7.5  
pF  
in  
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to V  
)
SS  
Recommended Peak–to–  
Peak Voltage Into or  
Out of the Switch  
V
Channel On or Off  
0
V
0
0
V
0
0
V
V
p–p  
I/O  
DD  
DD  
DD  
Recommended Static or  
Dynamic Voltage  
V  
Channel On  
0
600  
600  
300  
mV  
switch  
(4.)  
Across the Switch  
(Figure 1)  
Output Offset Voltage  
ON Resistance  
V
V
= 0 V, No Load  
10  
µV  
OO  
in  
(4.)  
R
5.0 V  
10  
15  
500 mV  
V = V or V  
in  
,
800  
400  
220  
250  
120  
80  
1050  
500  
280  
1300  
550  
320  
on  
switch  
IL  
IH  
(Control), and V  
in  
0 to V (Switch)  
DD  
ON Resistance Between  
Any Two Channels  
R  
5.0  
10  
15  
70  
50  
45  
25  
10  
10  
70  
50  
45  
135  
95  
65  
on  
in the Same Package  
Off–Channel Leakage  
Current (Figure 2)  
I
off  
15  
V
in  
= V or V  
IH  
± 100  
± 0.05  
±100  
±1000 nA  
IL  
(Control) Channel to  
Channel or Any One  
Channel  
Capacitance, Switch I/O  
C
C
Inhibit = V  
10  
pF  
pF  
I/O  
O/I  
DD  
Capacitance, Common O/I  
Inhibit = V  
DD  
(MC14067B)  
(MC14097B)  
100  
60  
Capacitance, Feedthrough  
(Channel Off)  
C
Pins Not Adjacent  
Pins Adjacent  
0.47  
pF  
I/O  
3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.  
4. For voltage drops across the switch (V ) > 600 mV ( > 300 mV at high temperature), excessive V current may be drawn; i.e.  
switch  
DD  
the current out of the switch may contain both V and switch input components. The reliability of the device will be unaffected unless the  
DD  
Maximum Ratings are exceeded. (See first page of this data sheet.)  
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4
MC14067B  
ELECTRICAL CHARACTERISTICS (C = 50 pF, T = 25 C)  
L
A
V
– V  
SS  
DD  
Vdc  
(5.)  
Characteristic  
Symbol  
,t  
Typ  
Max  
Unit  
Propagation Delay Times  
t
ns  
PLH PHL  
Channel Input–to–Channel Output (R = 200 k)  
L
MC14067B  
(Figure 3)  
5.0  
10  
15  
35  
15  
12  
90  
40  
30  
Control Input–to–Channel Output  
t
, t  
ns  
ns  
ns  
PZH PZL  
Channel Turn–On Time (R = 10 k)  
L
MC14067B  
(Figure 4)  
5.0  
10  
15  
240  
115  
75  
600  
290  
190  
Channel Turn–Off Time (R = 300 k)  
t
,t  
L
PHZ PLZ  
MC14067B  
(Figure 4)  
5.0  
10  
15  
250  
120  
75  
625  
300  
190  
Any Pair of Address Inputs to Output  
MC14067B  
t
, t  
PLH PHL  
5.0  
10  
15  
280  
115  
85  
700  
290  
215  
Second Harmonic Distortion  
10  
0.3  
%
(R = 10 k, f = 1 kHz, V = 5 V  
)
L
in  
p–p  
ON Channel Bandwidth  
BW  
MHz  
[R = 1 k, V = 1/2 (V – V )  
(sine–wave)]  
Off Channel Feedthrough Attenuation  
[R = 1 k, V = 1/2 (V –V ) (sine–wave)]  
SS p–p  
L
in  
DD  
SS p–p  
20 Log10 (V /V ) = – 3 dB  
MC14067B  
(Figure 5)  
10  
10  
15  
out in  
– 40  
dB  
dB  
L
in  
DD  
f
in  
= 20 MHz – MC14067B  
(Figure 5)  
Channel Separation  
[R = 1 k, V = 1/2 (V –V ) (sine–wave)]  
SS p–p  
10  
10  
– 40  
30  
L
in  
DD  
f
= 20 MHz  
(Figure 6)  
in  
Crosstalk, Control Inputs–to–Common O/I  
(R1 = 1 k, R = 10 k,  
mV  
L
Control t = t = 20 ns, Inhibit = V )  
SS  
(Figure 7)  
r
f
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.  
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5
MC14067B  
OFF CHANNEL UNDER TEST  
V
DD  
ON SWITCH  
A
V
CONTROL  
SECTION  
OF IC  
SS  
CONTROL  
SECTION  
OF IC  
OTHER  
CHANNEL(S)  
V
SS  
LOAD  
V
DD  
V
SOURCE  
V
SS  
V
DD  
Figure 1. V Across Switch  
Figure 2. Off Channel Leakage  
V
C
A
B
C
D
PULSE  
GENERATOR  
V
DD  
V
out  
A
B
C
D
C = 50 pF  
L
INH  
R
L
V
out  
V
in  
V
X
INH  
C = 50 pF  
L
R
L
V
DD  
V
SS  
V
V
SS DD  
20 ns  
50%  
20 ns  
V
in  
90%  
50%  
10%  
V
C
20 ns  
20 ns  
90%  
V
DD  
V
in  
50%  
90%  
V = V  
in  
DD  
10%  
V
out  
V
SS  
V = V  
X
SS  
t
t
PHL  
PLH  
t
, t  
t
, t  
PZH PZL  
PHZ PLZ  
50%  
V
out  
V = V  
V
out  
50%  
in  
SS  
10%  
V = V  
X
DD  
Figure 3. Propagation Delay Test Circuit  
and Waveforms Vin to Vout  
Figure 4. Turn–On and Delay Turn–Off  
Test Circuit and Waveforms  
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6
MC14067B  
V
DD  
A, B, and C inputs used to turn ON or OFF  
the switch under test.  
R
L
A
B
C
D
ON  
A
B
C
OFF  
INH  
V
out  
V
out  
D
C = 50 pF  
L
R
L
INH  
R
L
C = 50 pF  
L
V
in  
V
in  
Figure 5. Bandwidth and Off–Channel  
Feedthrough Attenuation  
Figure 6. Channel Separation  
(Adjacent Channels Used for Setup)  
A
B
C
D
V
C
V
out  
R
L
INH  
C = 50 pF  
L
R1  
Figure 7. Crosstalk, Control to Common O/I  
V
B
A
B
C
D
A
V
INH  
V
DD  
C
L
V
DD  
V
out  
KEITHLEY 160  
DIGITAL  
MULTIMETER  
50%  
50%  
V
A
10 k  
V
DD  
1 kΩ  
RANGE  
XY  
PLOTTER  
V
B
t
t
PLH  
PHL  
V
SS  
V
out  
50%  
Figure 8. Channel Resistance (RON) Test Circuit  
Figure 9. Propagation Delay, Any Pair of  
Address Inputs to Output  
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7
MC14067B  
TYPICAL RESISTANCE CHARACTERISTICS  
350  
300  
350  
300  
250  
200  
150  
100  
250  
200  
150  
T = 125°C  
A
T = 125°C  
A
100  
25°C  
25°C  
55°C  
55°C  
50  
0
50  
0
10 8.0 6.0 4.0 2.0  
0
0.2 4.0 6.0 8.0  
10  
10 8.0 6.0 4.0 2.0  
0
0.2 4.0 6.0 8.0 10  
V , INPUT VOLTAGE (VOLTS)  
in  
V , INPUT VOLTAGE (VOLTS)  
in  
Figure 10. VDD = 7.5 V, VSS = – 7.5 V  
Figure 11. VDD = 5.0 V, VSS = – 5.0 V  
350  
300  
700  
600  
T = 25°C  
A
250  
200  
150  
100  
500  
400  
300  
200  
V
DD  
= 2.5 V  
T = 125°C  
5.0 V  
A
7.5 V  
25°C  
50  
0
100  
0
55°C  
10 8.0 6.0 4.0 2.0  
0
0.2 4.0 6.0 8.0 10  
10 8.0 6.0 4.0 2.0  
0
0.2 4.0 6.0 8.0  
10  
V , INPUT VOLTAGE (VOLTS)  
in  
V , INPUT VOLTAGE (VOLTS)  
in  
Figure 13. Comparison at 25°C, VDD = VSS  
Figure 12. VDD = 2.5 V, VSS = – 2.5 V  
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8
MC14067B  
APPLICATIONS INFORMATION  
Figure  
A
illustrates use of the Analog  
signal which allows no margin at either peak. If voltage  
transients above V and/or below V are anticipated on  
Multiplexer/Demultiplexer. The 0–to–5 volt Digital Control  
DD  
SS  
signal is used to directly control a 5 V analog signal.  
the analog channels, external diodes (D ) are recommended  
p–p  
x
The digital control logic levels are determined by V  
as shown in Figure B. These diodes should be small signal  
typesable toabsorbthe maximum anticipatedcurrent surges  
during clipping.  
DD  
and V . The V voltage is the logic high voltage; the V  
SS  
DD  
SS  
voltage is logic low. For the example. V = + 5 V = logic  
DD  
high at the control inputs; V = GND = 0 V = logic low.  
TheabsolutemaximumpotentialdifferencebetweenV  
SS  
DD  
The maximum analog signal level is determined by V  
and V is 18.0 volts. Most parameters are specified up to  
DD  
SS  
and V . The analog voltage must swing neither higher than  
15 V which is the recommended maximum difference  
SS  
V
nor lower than V . The example shows a 5 V  
between V and V .  
DD  
SS  
p–p  
DD SS  
+5 V  
V
DD  
V
SS  
+5.0 V  
5 V  
SWITCH  
I/O  
p–p  
5 V  
ANALOG SIGNAL  
COMMON  
O/I  
p–p  
+2.5 V  
ANALOG SIGNAL  
+5 V  
GND  
MC14067B  
EXTERNAL  
CMOS  
DIGITAL  
0–TO–5 V DIGITAL  
CONTROL SIGNALS  
CIRCUITRY  
Figure A. Application Example  
V
DD  
V
DD  
D
X
D
X
SWITCH  
I/O  
COMMON  
O/I  
D
X
D
X
V
SS  
V
SS  
Figure B. External Germanium or Schottky Clipping Diodes  
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9
MC14067B  
PACKAGE DIMENSIONS  
PDIP–24  
P SUFFIX  
CASE 709–02  
ISSUE C  
NOTES:  
1. POSITIONAL TOLERANCE OF LEADS (D),  
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM  
MATERIAL CONDITION, IN RELATION TO  
SEATING PLANE AND EACH OTHER.  
2. DIMENSION L TO CENTER OF LEADS WHEN  
FORMED PARALLEL.  
24  
1
13  
12  
B
3. DIMENSION B DOES NOT INCLUDE MOLD  
FLASH.  
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN  
MAX  
1.265  
0.560  
0.200  
0.022  
0.060  
A
B
C
D
F
31.37  
13.72  
3.94  
0.36  
1.02  
32.13 1.235  
14.22 0.540  
5.08 0.155  
0.56 0.014  
1.52 0.040  
L
A
C
N
G
H
J
K
L
2.54 BSC  
0.100 BSC  
K
1.65  
0.20  
2.92  
2.03 0.065  
0.38 0.008  
3.43  
0.080  
0.015  
0.135  
J
H
F
M
SEATING  
PLANE  
0.115  
D
G
15.24 BSC  
0.600 BSC  
M
N
0
0.51  
15  
0
15  
0.040  
1.02 0.020  
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10  
MC14067B  
PACKAGE DIMENSIONS  
SOIC–24  
DW SUFFIX  
CASE 751E–04  
ISSUE E  
–A–  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
24  
13  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
–B– 12X P  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
M
M
0.010 (0.25)  
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN  
EXCESS OF D DIMENSION AT MAXIMUM  
MATERIAL CONDITION.  
1
12  
24X D  
J
MILLIMETERS  
DIM MIN MAX  
INCHES  
M
S
S
0.010 (0.25)  
T A  
B
MIN  
MAX  
0.612  
0.299  
0.104  
0.019  
0.035  
A
B
C
D
F
15.25  
7.40  
2.35  
0.35  
0.41  
15.54 0.601  
7.60 0.292  
2.65 0.093  
0.49 0.014  
0.90 0.016  
F
R X 45  
G
J
K
M
P
1.27 BSC  
0.050 BSC  
0.23  
0.13  
0
0.32 0.009  
0.29 0.005  
0.013  
0.011  
8
C
K
–T–  
SEATING  
8
0
M
10.05  
0.25  
10.55 0.395  
0.75 0.010  
0.415  
0.029  
PLANE  
R
22X G  
http://onsemi.com  
11  
MC14067B  
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MC14067B/D  

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