MC14094BFL1
更新时间：2024-09-18 14:17:35
品牌：ONSEMI
描述：4000/14000/40000 SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, EIAJ, PLASTIC, SOIC-16
概述
规格参数
数据手册MC14094BFL1 概述
4000/14000/40000 SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, EIAJ, PLASTIC, SOIC-16 移位寄存器
MC14094BFL1 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | SOIC | 包装说明： | EIAJ, PLASTIC, SOIC-16 |
| 针数： | 16 | Reach Compliance Code： | not_compliant |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.58 |
| Is Samacsys： | N | 计数方向： | RIGHT |
| 系列： | 4000/14000/40000 | JESD-30 代码： | R-PDSO-G16 |
| JESD-609代码： | e0 | 长度： | 10.2 mm |
| 逻辑集成电路类型： | SERIAL IN PARALLEL OUT | 最大频率@ Nom-Sup： | 1250000 Hz |
| 位数： | 8 | 功能数量： | 1 |
| 端子数量： | 16 | 最高工作温度： | 125 °C |
| 最低工作温度： | -55 °C | 输出特性： | 3-STATE |
| 输出极性： | TRUE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP16,.3 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 5/15 V |
| 传播延迟（tpd）： | 840 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 2.05 mm | 子类别： | Shift Registers |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | MILITARY |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 触发器类型： | POSITIVE EDGE |
| 宽度： | 5.275 mm | 最小 fmax： | 3 MHz |
| Base Number Matches： | 1 |
MC14094BFL1 数据手册
通过下载MC14094BFL1数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载The MC14094B combines an 8–stage shift register with a data latch
for each stage and a three–state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
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seventh stage to two serial outputs. The Q output data is for use in
S
high–speed cascaded systems. The Q′ output data is shifted on the
following negative clock transition for use in low–speed cascaded
systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while
strobe is high.
S
MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14094BCP
AWLYYWW
Outputs of the eight data latches are controlled by three–state
buffers which are placed in the high–impedance state by a logic Low
on Output Enable.
1
16
1
SOIC–16
D SUFFIX
CASE 751B
• Three–State Outputs
14094B
AWLYWW
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
• Input Diode Protection
16
• Data Latch
• Dual Outputs for Data Out on Both Positive and
Negative Clock Transitions
TSSOP–16
DT SUFFIX
CASE 948F
14
094B
ALYW
• Useful for Serial–to–Parallel Data Conversion
1
• Pin–for–Pin Compatible with CD4094B
16
1
SOEIAJ–16
F SUFFIX
CASE 966
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
MC14094B
AWLYWW
SS
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
in out
DD
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
ORDERING INFORMATION
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
Device
Package
PDIP–16
SOIC–16
SOIC–16
TSSOP–16
Shipping
A
T
stg
MC14094BCP
MC14094BD
2000/Box
48/Rail
T
Lead Temperature
(8–Second Soldering)
L
MC14094BDR2
MC14094BDT
2500/Tape & Reel
96/Rail
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
MC14094BDTR2 TSSOP–16 2500/Tape & Reel
MC14094BF SOEIAJ–16 See Note 1.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
1. For ordering information on the EIAJ version of the
SOIC packages, please contact your local ON
Semiconductor representative.
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14094B/D
MC14094B
PIN ASSIGNMENT
STROBE
DATA
CLOCK
Q1
1
2
3
4
5
6
7
8
16
15
V
DD
OUTPUT
ENABLE
14 Q5
13 Q6
12 Q7
11 Q8
Q2
Q3
Q4
10 Q′
S
V
SS
9
Q
S
Parallel Outputs
Serial Outputs
Output
Enable
Clock
Strobe
Data
Q1
Z
Q
Q *
S
Q′
S
N
0
0
1
1
1
1
X
X
0
1
1
1
X
X
X
0
1
1
Z
Q7
No Chg.
Q7
No Chg.
Q7
Z
Z
No Chg. No Chg.
No Chg.
No Chg.
No Chg.
Q7
0
1
Q –1
Q7
N
Q –1
N
Q7
No Chg. No Chg. No Chg.
Z = High Impedance
X = Don’t Care
* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q .
S
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2
MC14094B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (4.1 µA/kHz) f + I
T
I = (14 µA/kHz) f + I
T
I = (140 µA/kHz) f + I
T
DD
DD
(Dynamic plus Quiescent,
Per Package)
DD
(C = 50 pF on all outputs, all
L
buffers switching)
3–State Output Leakage Current
I
TL
15
—
± 0.1
—
± 0.0001
± 0.1
—
± 3.0
µA
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.001.
T
L
DD
SS
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3
MC14094B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
(8.)
Characteristic
Output Rise and Fall Time
Symbol
Min
Typ
Max
Unit
t
,
ns
TLH
t
t
t
, t
= (1.35 ns/pF) C + 33 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.6 ns/pF) C + 20 ns
TLH THL
L
, t
= (0.4 ns/pF) C + 20 ns
L
TLH THL
Propagation Delay Time
Clock to Serial out QS
t
t
,
ns
PLH
PHL
t
t
t
, t
= (0.90 ns/pF) C + 305 ns
5.0
10
15
—
—
—
350
125
95
600
250
190
PLH PHL
L
, t
= (0.36 ns/pF) C + 107 ns
PLH PHL
L
, t
= (0.26 ns/pF) C L + 82 ns
PLH PHL
Clock to Serial out Q’S
t
t
t
, t
= (0.90 ns/pF) C + 350 ns
= (0.36 ns/pF) C + 149 ns
L
= (0.26 ns/pF) C + 62 ns
L
5.0
10
15
—
—
—
230
110
75
460
220
150
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Clock to Parallel out
5.0
10
15
—
—
—
420
195
135
840
390
270
t
t
t
, t
= (0.90 ns/pF) C + 375 ns
= (0.35 ns/pF) C + 177 ns
L
= (0.26 ns/pF) C + 122 ns
L
PLH PHL L
, t
PLH PHL
, t
PLH PHL
Strobe to Parallel out
5.0
10
15
—
—
—
290
145
100
580
290
200
t
t
t
, t
= (0.90 ns/pF) C + 245 ns
= (0.36 ns/pF) C L + 127 ns
= (0.26 ns/pF) C + 87 ns
L
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Output Enable to Output
t
t
,
5.0
10
15
—
—
—
140
75
55
280
150
110
PHZ
t
t
t
t
, t
= (0.90 ns/pF) C + 95 ns
= (0.36 ns/PF) C + 57 ns
L
= (0.26 ns/pF) C + 42 ns
PHZ PZL L
PZL
, t
PHZ PZL
, t
PHZ PZL
L
,
5.0
10
15
—
—
—
225
95
70
450
190
140
t
t
t
, t
= (0.90 ns/pF) C + 180 ns
= (0.36 ns/pF) C + 77 ns
= (0.26 ns/pF) C + 57 ns
L
PLZ
PLZ PZH
L
t
, t
PZH
PLZ PZH
L
, t
PLZ PZH
Setup Time
Data in to Clock
t
5.0
10
15
125
55
35
60
30
20
—
—
—
ns
ns
su
Hold Time
Clock to Data
t
5.0
10
15
0
20
20
– 40
– 10
0
—
—
—
h
Clock Pulse Width, High
Clock Rise and Fall Time
Clock Pulse Frequency
Strobe Pulse Width
t
5.0
10
15
200
100
83
100
50
40
—
—
—
ns
WH
t
5
10
15
—
—
—
—
—
—
15
5.0
4.0
µs
r(cl)
t
f(cl)
f
cl
5.0
10
15
—
—
—
2.5
5.0
6.0
1.25
2.5
3.0
MHz
ns
t
5.0
10
15
200
80
70
100
40
35
—
—
—
WL
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14094B
3–STATE TEST CIRCUIT
FOR t
AND t
FOR t AND t
PLZ PZL
PHZ
PZH
V
SS
V
DD
O.E.
DATA
ST
1 k
OUTPUT
50 pF
CLOCK
BLOCK DIAGRAM
REGISTER STAGE 1
CLOCK
LATCH 1
STROBE
3–STATE BUFFER 1
CLOCK
V
DD
2
*
4
Q1
SERIAL
DATA IN
STROBE STROBE
STROBE
CLOCK
CLOCK
CLOCK
CLOCK
15
*
2
5
6
7
Q2
Q3
Q4
REGISTER STAGE 2
LATCH 2
LATCH 3
LATCH 4
LATCH 5
LATCH 6
LATCH 7
3–STATE BUFFER
3–STATE BUFFER
3–STATE BUFFER
3–STATE BUFFER
3–STATE BUFFER
3–STATE BUFFER
2
OUTPUT
ENABLE
3
4
5
6
7
REGISTER STAGE 3
REGISTER STAGE 4
REGISTER STAGE 5
REGISTER STAGE 6
REGISTER STAGE 7
3
4
5
6
7
14 Q5
13 Q6
12 Q7
11 Q8
8
REGISTER STAGE 8
LATCH 8
3–STATE BUFFER
8
CLOCK
CLOCK
CLOCK
CLOCK
STROBE STROBE
10 Q′
S
3
1
*
CLOCK
CLOCK
CLOCK
CLOCK
*Input Protection Diodes
STROBE
*
CLOCK
9
Q
S
STROBE
STROBE
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5
MC14094B
DYNAMIC TIMING DIAGRAM
t
WH
t
f
t
r
90%
10%
3
CLOCK
50%
50%
t
su
t
h
2
1
DATA IN
t
WL
STROBE
OUTPUT
ENABLE
50%
50%
15
N
t
t
t
t
t
PZL
t
PLH
PLH
PZH
PLZ
t
PHZ
PHL
90%
10%
90%
90%
10%
90%
Q1 Q7
t
10%
10%
t
t
t
PLH
PHL
TLH
THL
50%
9
Q
S
50%
t
t
PLH
PHL
10
Q′
S
50%
50%
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
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6
MC14094B
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
TSSOP–16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T U
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
2X L/2
J1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
B
–U–
SECTION N–N
L
J
PIN 1
IDENT.
8
1
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
N
0.25 (0.010)
S
0.15 (0.006) T U
A
M
–V–
N
F
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.200
0.177
0.047
0.006
0.030
A
B
C
4.90
4.30
–––
5.10 0.193
4.50 0.169
1.20
DETAIL E
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
–W–
C
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.011
0.008
0.006
0.012
0.010
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
–T–
D
G
6.40 BSC
0.252 BSC
M
0
8
0
8
http://onsemi.com
7
MC14094B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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MC14094B/D
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