MC14106BDTR [ONSEMI]
MC14106BDTR;
| 型号： | MC14106BDTR |
| 厂家： | 
ONSEMI |
| 描述： | MC14106BDTR 触发器 |
| 文件： | 总10页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14106B
Hex Schmitt Trigger
The MC14106B hex Schmitt Trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14106B
may be used in place of the MC14069UB hex inverter for enhanced
noise immunity or to “square up” slowly changing waveforms.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than
maximum rated voltages to this high−impedance circuit. For proper
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MARKING
DIAGRAMS
14
MC14106BCP
AWLYYWWG
operation, V and V should be constrained to the range V v (V
in
out
SS
in
or V ) v V
.
out
DD
PDIP−14
P SUFFIX
CASE 646
1
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS
DD
Features
14
• Increased Hysteresis Voltage Over the MC14584B
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
14106BG
AWLYWW
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD40106B and MM74C14
• Can Be Used to Replace the MC14584B or MC14069UB
SOIC−14
D SUFFIX
CASE 751A
1
14
14
106B
ALYWG
G
• Pb−Free Packages are Available
14
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
1
TSSOP−14
DT SUFFIX
CASE 948G
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
V
DC Supply Voltage Range
DD
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
A
= Assembly Location
= Year
WL, L = Wafer Lot
YY, Y
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
WW, W = Work Week
G or G = Pb−Free Package
P
Power Dissipation, per Package
(Note 1)
500
mW
D
(Note: Microdot may be in either location)
T
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
T
stg
ORDERING INFORMATION
T
Lead Temperature
L
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
(8−Second Soldering)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/°C From
65°C To 125°C
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 7
MC14106B/D
MC14106B
1
3
2
4
5
6
9
8
11
13
10
12
V
= PIN 14
= PIN 7
DD
V
SS
Figure 2. Equivalent Circuit Schematic
(1/6 of Circuit Shown)
Figure 1. Logic Diagram
ORDERING INFORMATION
†
Device
Package
Shipping
MC14106BCP
PDIP−14
25 Units / Rail
55 Units / Rail
MC14106BCPG
PDIP−14
(Pb−Free)
MC14106BD
SOIC−14
MC14106BDG
SOIC−14
(Pb−Free)
MC14106BDR2
SOIC−14
MC14106BDR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC14106BDTR2
TSSOP−14*
TSSOP−14*
MC14106BDTR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC14106B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55°C
25°C
125°C
V
Vdc
DD
(2)
Min
Max
Min
Typ
Max
Min
Max
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
V
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
OL
V
in
= V
DD
V
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
OH
V
in
= 0
(5)
Hysteresis Voltage
V
5.0
10
15
0.3
1.2
1.6
2.0
3.4
5.0
0.3
1.2
1.6
1.1
1.7
2.1
2.0
3.4
5.0
0.3
1.2
1.6
2.0
3.4
5.0
H
Threshold Voltage
Positive−Going
V
5.0
10
15
2.2
4.6
6.8
3.6
7.1
10.8
2.2
4.6
6.8
2.9
5.9
8.8
3.6
7.1
10.8
2.2
4.6
6.8
3.6
7.1
10.8
Vdc
Vdc
T+
T–
V
5.0
10
15
0.9
2.5
4.0
2.8
5.2
7.4
0.9
2.5
4.0
1.9
3.9
5.8
2.8
5.2
7.4
0.9
2.5
4.0
2.8
5.2
7.4
Negative−Going
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
OH
OH
OH
OH
15
(V = 0.4 Vdc)
(V = 0.5 Vdc)
(V = 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
OL
OL
OL
Input Current
Input Capacitance
I
15
−
−
±0.1
−
−
±0.00001
±0.1
−
−
±1.0
mAdc
in
C
−
−
5.0
7.5
−
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
mAdc
DD
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
I
5.0
10
15
I
I
I
= (1.8 mA/kHz) f + I
= (3.6 mA/kHz) f + I
= (5.4 mA/kHz) f + I
T
T
T
T
DD
DD
DD
(C = 50 pF on all outputs, all
L
buffers switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25°C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk where I is in mA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and
T
L
T
L
T
L
DD
SS
k = 0.001.
=
5. V
V
– V (But maximum variation of V is specified as less that V
– V
).
H
T+
T–
H
T+ max
T– min
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3
MC14106B
SWITCHING CHARACTERISTICS (C = 50 pF, T = 25°C)
L
A
V
Vdc
DD
(6)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time
Output Fall Time
t
5.0
10
15
−
−
−
100
50
40
200
100
80
ns
TLH
t
5.0
10
15
−
−
−
100
50
40
200
100
80
ns
ns
THL
Propagation Delay Time
t
, t
5.0
10
15
−
−
−
125
50
40
250
100
80
PLH PHL
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
V
DD
14
V
DD
INPUT
90%
50%
10%
OUTPUT
PULSE
GENERATOR
INPUT
V
V
SS
t
t
PLH
C
PHL
L
7
V
SS
OH
90%
50%
OUTPUT
10%
V
OL
t
f
t
r
Figure 1. Switching Time Test Circuit and Waveforms
V
DD
0
0
V
V
V
DD
T−
T+
V
H
V , INPUT VOLTAGE (Vdc)
in
Figure 2. Typical Transfer Characteristics
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4
MC14106B
APPLICATIONS
V
out
V
in
V
V
DD
DD
V
V
H
H
V
in
V
in
V
V
V
V
SS
DD
SS
DD
V
out
V
out
V
V
SS
SS
(a) Schmitt Triggers will square up
inputs with slow rise and fall times.
(b) A Schmitt trigger offers maximum
noise immunity in gate applications.
Figure 3.
V
V
DD
DD
R
C
tw
tw
Rs
Rs
V
out
V
out
C
R
V
DD
tw = RC IN
V
T+
Useful as Pushbutton/Keyboard Debounce Circuit.
Figure 4. Monostable Multivibrator
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5
MC14106B
t1+t2
t1
R
A
V
in
V
out
R
C
t2
V
V
DD
V
in
V
T+
SS
C
V
T
)
V
V
DD
* t ꢀ [ꢀ R ꢀl ꢀ
1
V
–
T
V
T+
A
–ꢁꢀV
V
–
T
DDꢁ
SS
* t ꢀ [ꢀ R ꢀl ꢀ
2
V
ꢀꢁ–ꢁꢀV
DD
T)
V
)
T
V
V
DD
V
–ꢁV
–
DDꢁꢀ
T
1
f
ꢀǒ
Ǔꢀǒ Ǔ
ꢀ [ꢀ R ꢀln
ƪ
*t + t & t
PHL PLH
ƫ
V
out
V
T+
V
T–
V
ꢀꢁ–ꢁV
DD
T)
SS
+ t
1
2
Useful in discriminating against short pulse durations.
Figure 5. Astable Multivibrator
Figure 6. Integrator
C
V
in
V
in
R
+ꢀEDGE
−ꢀEDGE
C
C
C
−
EDGE
+ꢀEDGE
V
in
V
DD
R
R
R
tw
V
DD
tw = RC ln
Useful as an edge detector circuit.
V
T+
Figure 7. Differentiator
Figure 8. Positive Edge Time Delay Circuit
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6
MC14106B
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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7
MC14106B
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MC14106B
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
INCHES
K1
DIM MIN
MAX
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
0.15 0.002 0.006
0.75 0.020 0.030
J J1
−−− 0.047
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MC14106B
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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MC14106B/D
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