MC14513B_06_技术文档

MC14513B

BCD−To−Seven Segment

Latch/Decoder/Driver

CMOS MSI

(Low−Power Complementary MOS)

The MC14513B BCD−to−seven segment latch/decoder/driver is

constructed with complementary MOS (CMOS) enhancement mode

devices and NPN bipolar output drivers in a single monolithic structure.

The circuit provides the functions of a 4−bit storage latch, an 8421

BCD−to−seven segment decoder, and has output drive capability. Lamp

test (LT), blanking (BI), and latch enable (LE) inputs are used to test the

display, to turn−off or pulse modulate the brightness of the display, and

to store a BCD code, respectively. The Ripple Blanking Input (RBI) and

Ripple Blanking Output (RBO) can be used to suppress either leading

or trailing zeroes. It can be used with seven−segment light emitting

diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal

readouts either directly or indirectly.

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PDIP−18

P SUFFIX

CASE 707

1

MARKING DIAGRAM

Applications include instrument (e.g., counter, DVM, etc.) display

driver, computer/calculator display driver, cockpit display driver, and

various clock, watch, and timer uses.

18

Features

MC14513BCP

AWLYYWWG

• Low Logic Circuit Power Dissipation

• High−Current Sourcing Outputs (Up to 25 mA)

• Latch Storage of Binary Input

1

• Blanking Input

A

= Assembly Location

• Lamp Test Provision

WL = Wafer Lot

YY = Year

WW = Work Week

• Readout Blanking on all Illegal Input Combinations

• Lamp Intensity Modulation Capability

• Time Share (Multiplexing) Capability

• Adds Ripple Blanking In, Ripple Blanking Out to MC14511B

• Supply Voltage Range = 3.0 V to 18 V

• Capable of Driving Two Low−Power TTL Loads, One Low−Power

Schottky TTL Load to Two HTL Loads Over the Rated Temperature

Range

G

= Pb−Free Package

ORDERING INFORMATION

Device

Package

Shipping

20 Units/Rail

MC14513BCP

MC14513BCPG

PDIP−18

• Pb−Free Package is Available*

MAXIMUM RATINGS (Voltages Referenced to V

PDIP−18

(Pb−Free)

)

SS

Parameter

Symbol

Value

−0.5 to +18.0

Unit

V

DC Supply Voltage Range

V

DD

This device contains protection circuitry to protect

the inputs against damage due to high static voltages

or electric fields. However, it is advised that normal

precautions be taken to avoid application of any

voltage higher than maximum rated voltages to this

high−impedance circuit. A destructive high current

Input Voltage Range, All Inputs

DC Current Drain per Input Pin

Power Dissipation per Package (Note 1)

Operating Temperature Range

Storage Temperature Range

V

−0.5 to V +0.5

V

in

DD

I

10

500

mA

mW

°C

P

D

T

A

−55 to +125

−65 to +150

25

mode may occur if V and V are not constrained to

in

out

the range V v (V or V ) v V

.

T

stg

°C

SS

in

out

DD

Due to the sourcing capability of this circuit,

Maximum Continuous Output Drive

Current (Source) per Output

I

mA

OHmax

damage can occur to the device if V is applied, and

DD

the outputs are shorted to V and are at a logical 1

SS

(See Maximum Ratings).

Unused inputs must always be tied to an appropriate

logic voltage level (e.g., either V or V ).

Maximum Continuous Output Power

(Source) per Output (Note 2)

P

50

mW

OHmax

SS

DD

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating: Plastic “P and D/DW”

*For additional information on our Pb−Free strategy

and soldering details, please download the

ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

Packages: – 7.0 mW/_C From 65_C To 125_C

2. P

= I

(V − V

)

OH

OHmax

OH

DD

©

Semiconductor Components Industries, LLC, 2006

1

Publication Order Number:

June, 2006 − Rev. 6

MC14513B/D

MC14513B

PIN ASSIGNMENT

B

C

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

V

f

DD

LT

BI

LE

D

g

a

b

c

d

e

A

RBI

V

10 RBO

SS

a

f

g

b

e

c

d

DISPLAY

0

1

2

3

4

5

6

7

8

9

TRUTH TABLE

Inputs

Outputs

RBI LE BI LT

D

C

X

B

X

A RBO

a

1

0

b

c

1

0

d

1

0

e

1

0

f

g

1

0

Display

8

X

0

1

X

+

1

0

1

0

Blank

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Blank

0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

6

7

8

9

Blank

X

0

1

0

1

0

1

0

1

0

1

0

Blank

X

1

X

†

*

X = Don’t Care

†RBO = RBI (D C B A), indicated by other rows of table

*Depends upon the BCD code previously applied when LE = 0

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2

MC14513B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

SS

− 55_C

25_C

Typ

125_C

V

DD

(Note 3)

Min

Max

Min

Max

Min

Max

Vdc

Characteristic

Symbol

Unit

Output Voltage — Segment Outputs

“0” Level

V

Vdc

OL

5.0

10

15

−

0.05

−

0

0.05

−

0.05

V

in

= V or 0

DD

“1” Level

V

5.0

10

15

4.1

9.1

14.1

−

4.1

9.1

14.1

5.0

10

15

−

4.1

9.1

14.1

−

Vdc

OH

V

in

= 0 or V

DD

Output Voltage — RBO Output

V

OL

“0” Level

5.0

10

15

−

0.05

−

0

0.05

−

0.05

V

in

= V or 0

DD

“1” Level

V

5.0

10

15

4.95

9.95

14.95

−

4.95

9.95

14.95

5.0

10

15

−

4.95

9.95

14.95

−

Vdc

OH

V

= 0 or V

in

DD

Input Voltage (Note 3) “0” Level

(V = 3.8 or 0.5 Vdc)

V

IL

5.0

10

15

−

1.5

3.0

4.0

−

2.25

4.50

6.75

1.5

3.0

4.0

−

1.5

3.0

4.0

O

(V = 8.8 or 1.0 Vdc)

(V = 13.8 or 1.5 Vdc)

(V = 0.5 or 3.8 Vdc) “1” Level

O

V

5.0

10

15

3.5

7.0

11

−

3.5

7.0

11

2.75

5.50

8.25

−

3.5

7.0

11

−

Vdc

IH

(V = 1.0 or 8.8 Vdc)

O

(V = 1.5 or 13.8 Vdc)

O

Output Drive Voltage — Segments

V

OH

(I

= 0 mA)

Source

5.0

10

15

4.1

−

3.9

−

3.4

−

4.1

−

3.9

−

3.4

−

4.57

4.24

4.12

3.94

3.70

3.54

−

4.1

−

3.5

−

3.0

−

OH

= 5.0 mA)

= 10 mA)

= 15 mA)

= 20 mA)

= 25 mA)

(I

= 0 mA)

OH

9.1

−

9.0

−

8.6

−

9.1

−

9.0

−

8.6

−

9.58

9.26

9.17

9.04

8.90

8.75

−

9.1

−

8.6

−

8.2

−

Vdc

= 5.0 mA)

= 10 mA)

= 15 mA)

= 20 mA)

= 25 mA)

(I

= 0 mA)

OH

= 5.0 mA)

= 10 mA)

= 15 mA)

= 20 mA)

= 25 mA)

14.1

−

14

−

13.6

−

14.1

−

14

−

13.6

−

14.59

14.27

14.18

14.07

13.95

13.80

−

14.1

−

13.6

−

13.2

−

3. Noise immunity specified for worst−case input combination.

Noise Margin for both “1” and “0” level =1.0 Vdc min @ V = 5.0 Vdc

DD

2.0 Vdc min @ V = 10 Vdc

DD

2.5 Vdc min @ V = 15 Vdc

DD

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3

MC14513B

ELECTRICAL CHARACTERISTICS (continued) (Voltages Referenced to V

– 55_C

)

SS

25_C

Typ

125_C

V

DD

(Note 4)

Vdc

Min

Max

Min

Max

Min

Max

Characteristic

Symbol

Unit

Output Drive Current — RBO Output

I

mAdc

OH

(V

= 2.5 V)

= 9.5 V)

= 13.5 V)

Source

5.0

10

15

– 0.40

– 0.21

– 0.81

−

– 0.32

– 0.17

– 0.66

– 0.64

– 0.34

– 1.30

−

– 0.22

– 0.12

– 0.46

−

OH

(V = 0.4 V)

Sink

OL

I

5.0

10

15

0.18

0.47

1.80

−

0.15

0.38

1.50

0.29

0.75

2.90

−

0.10

0.26

1.0

−

mAdc

OL

(V = 0.5 V)

OL

(V = 1.5 V)

OL

Output Drive Current — Segments

(V = 0.4 V) Sink

5.0

10

15

0.64

1.6

4.2

−

0.51

1.3

3.4

0.88

2.25

8.8

−

0.36

0.9

2.4

−

OL

(V = 0.5 V)

OL

(V = 1.5 V)

OL

Input Current

I

15

−

0.1

−

0.00001

5.0

0.1

7.5

−

1.0

−

mAdc

pF

in

Input Capacitance

Quiescent Current

C

in

I

5.0

10

15

−

5.0

10

20

−

0.005

0.010

0.015

5.0

10

20

−

150

300

600

mAdc

DD

(Per Package) V = 0 or V

,

DD

in

I

= 0 mA

out

Total Supply Current (Note 5, 6)

(Dynamic plus Quiescent,

Per Package)

I

5.0

10

15

I

= (1.9 mA/kHz) f + I

= (3.8 mA/kHz) f + I

= (5.7 mA/kHz) f + I

mAdc

T

DD

(C = 50 pF on all outputs, all

L

buffers switching)

4. Noise immunity specified for worst−case input combination.

Noise Margin for both “1” and “0” level =1.0 Vdc min @ V = 5.0 Vdc

DD

2.0 Vdc min @ V = 10 Vdc

DD

2.5 Vdc min @ V = 15 Vdc

DD

5. The formulas given are for the typical characteristics only at 25_C.

−3

6. To calculate total supply current at loads other than 50 pF: I (C ) = I (50 pF) + 3.5 x 10 (C − 50) V f where: I is in mA (per package),

T

L

T

L

DD

T

C in pF, V in Vdc, and f in kHz is input frequency.

L

DD

Input LE and RBI low, and Inputs D, BI and LT high.

f in respect to a system clock.

All outputs connected to respective C loads.

L

20 ns

V

DD

SS

90%

50%

1

A, B, AND C

10%

2f

50% DUTY CYCLE

V

OH

OL

50%

ANY OUTPUT

Figure 1. Dynamic Power Dissipation Signal Waveforms

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4

MC14513B

SWITCHING CHARACTERISTICS (Note 7) (C = 50 pF, T = 25_C)

L

A

All Types

Typ

V

Vdc

DD

Min

Max

Characteristic

Symbol

Unit

Output Rise Time — Segment Outputs

t

ns

TLH

THL

PLH

5.0

10

15

−

40

30

25

80

60

50

Output Rise Time — RBO Output

ns

5.0

10

15

−

480

240

190

960

480

380

Output Fall Time — Segment Outputs (Note 7)

t

= (1.5 ns/pF) C + 50 ns

5.0

10

15

−

125

75

65

250

150

130

THL

L

= (0.75 ns/pF) C + 37.5 ns

L

= (0.55 ns/pF) C + 37.5 ns

L

Output Fall Time — RBO Outputs

t

= (3.25 ns/pF) C + 107.5 ns

5.0

10

15

−

270

135

110

540

270

220

THL

L

= (1.35 ns/pF) C + 67.5 ns

L

= (0.95 ns/pF) C + 62.5 ns

L

Propagation Delay Time — A, B, C, D Inputs (Note 7)

t

= (0.40 ns/pF) C + 620 ns

5.0

10

15

−

640

250

175

1280

500

350

PLH

L

= (0.25 ns/pF) C + 237.5 ns

L

= (0.20 ns/pF) C + 165 ns

L

t

= (1.3 ns/pF) C + 655 ns

L

PHL

t

5.0

10

15

−

720

290

200

1440

580

400

ns

PHL

PLH

= (0.60 ns/pF) C + 260 ns

L

= (0.35 ns/pF) C + 182.5 ns

L

Propagation Delay Time — RBI and BI Inputs (Note 7)

5.0

10

15

−

600

200

150

750

300

220

t

= (1.05 ns/pF) C + 547.5 ns

PLH

L

= (0.45 ns/pF) C + 177.5 ns

L

= (0.30 ns/pF) C + 135 ns

L

t

= (0.85 ns/pF) C + 442.5 ns

L

PHL

t

5.0

10

15

−

485

200

160

970

400

320

ns

PHL

PLH

= (0.45 ns/pF) C + 177.5 ns

L

= (0.35 ns/pF) C + 142.5 ns

L

Propagation Delay Time — LT Input (Note 7)

5.0

10

15

−

313

125

90

625

250

180

t

= (0.45 ns/pF) C + 290.5 ns

PLH

L

= (0.25 ns/pF) C + 112.5 ns

L

= (0.20 ns/pF) C + 80 ns

L

t

= (1.3 ns/pF) C + 248 ns

L

PHL

t

5.0

10

15

−

313

125

90

625

250

180

ns

PHL

= (0.45 ns/pF) C + 102.5 ns

L

= (0.35 ns/pF) C + 72.5 ns

L

Setup Time

Hold Time

t

5.0

10

15

100

40

30

−

su

t

5.0

10

15

60

40

30

−

h

Latch Enable Pulse Width

t

5.0

10

15

520

220

130

260

110

65

−

WL(LE)

7. The formulas given are for the typical characteristics only.

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5

MC14513B

20 ns

V

DD

90%

50%

10%

INPUT C

V

SS

t

PHL

PLH

OH

OUTPUT g

t

V

OL

t

THL

TLH

a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.

20 ns

V

DD

90%

50%

10%

INPUT C

V

SS

t

PHL

PLH

V

OH

90%

10%

OUTPUT RBO

50%

V

OL

t

THL

TLH

b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.

20 ns

V

DD

90%

50%

LE

10%

V

SS

DD

t

h

t

su

INPUT C

50%

V

SS

OH

OUTPUT g

V

OL

c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.

20 ns

V

DD

90%

50%

10%

LE

V

SS

t

WL(LE)

d. Pulse Width: Data DCBA strobed into latches.

Figure 2. Dynamic Signal Waveforms

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6

MC14513B

CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIGHT EMITTING DIODE (LED) READOUT

V

DD

V

DD

COMMON

ANODE LED

COMMON

CATHODE LED

≈ 1.7 V

V

SS

V

SS

INCANDESCENT READOUT

FLUORESCENT READOUT

V

DD

V

DD

* *

DIRECT

(LOW BRIGHTNESS)

FILAMENT

(SUPPLY)

V

SS

V

VOLTAGE BELOW V

OR APPROPRIATE

.

SS

GAS DISCHARGE READOUT

LIQUID CRYSTAL (LC) READOUT

EXCITATION

(SQUARE WAVE,

TO V

APPROPRIATE

VOLTAGE

V

DD

V

DD

V

)

DD

SS

1/4 OF MC14070B

V

SS

V

SS

**A filament pre−warm resistor is recommended to reduce

filament thermal shock and increase the effective cold

resistance of the filament.

Direct dc drive of LC’s not recommended for life of LC readouts.

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7

MC14513B

LOGIC DIAGRAM

BIꢀ4

15ꢀa

Aꢀ7

Bꢀ1

14ꢀb

13ꢀc

12ꢀd

11ꢀe

17ꢀf

Cꢀ2

16ꢀg

LTꢀ30

10ꢀRBO

RBIꢀ8

Dꢀ6

LEꢀ5

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8

MC14513B

TYPICAL APPLICATIONS FOR RIPPLE BLANKING

LEADING EDGE ZERO SUPPRESSION

DISPLAYS

a − − − − − g

RBI RBO

a − − − − − g

RBO

a − − − − − g

RBO

RBI

a − − − − − g

RBO

a − − − − − g

CONNECT TO

(1)

RBO

A

RBO

RBI

D

RBI

D

RBI

1

0

1

V

D

C

B

A

D

C

B

A

D

C

B

A

D

C

B

A

C

B

C

B

A

DD

MC14513B

0

1

0

1

0

1

0

1

0

INPUT

CODE

(0)

(5)

(0)

(1)

(3)

(0)

TRAILING EDGE ZERO SUPPRESSION

DISPLAYS

− − − − −

a

g

a

g

a

g

a

g

a

g

RBI

A

g

RBI

A

CONNECT TO

V (1)

DD

0

RBI

A

RBI

A

RBO

D

RBO

D

RBO

D

RBI

A

RBI

A

RBO

D

RBO

D

RBO

D

0

1

0

C

B

C

B

C

B

C

B

C

B

C

B

MC14513B

0

1

0

1

0

1

0

1

INPUT CODE

(0)

(1)

(3)

(0)

(5)

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9

MC14513B

PACKAGE DIMENSIONS

PDIP−18

CASE 707−02

ISSUE D

NOTES:

1. POSITIONAL TOLERANCE OF LEADS (D), SHALL

J

BE WITHIN 0.25 mm (0.010) AT MAXIMUM

MATERIAL CONDITION, IN RELATION TO SEATING

PLANE AND EACH OTHER.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

18

10

9

B

L

1

3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

4. CONTROLLING DIMENSION: INCH.

M

A

INCHES

DIM MIN MAX

MILLIMETERS

MIN

22.22

6.10

3.56

0.36

1.27

MAX

23.24

6.60

4.57

0.56

1.78

A

B

C

D

F

0.875

0.240

0.140

0.014

0.050

0.915

0.260

0.180

0.022

0.070

C

K

N

G

H

J

0.100 BSC

2.54 BSC

0.040

0.008

0.115

0.060

0.012

0.135

1.02

0.20

2.92

1.52

0.30

3.43

F

D

SEATING

PLANE

H

K

L

G

0.300 BSC

7.62 BSC

M

N

0

0.020

15

0.040

0

_

0.51

15

_

1.02

_

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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LITERATURE FULFILLMENT:

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

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Phone: 81−3−5773−3850

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MC14513B/D

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10


型号：	MC14513B_06
厂家：	ONSEMI
描述：	BCD−To−Seven Segment Latch/Decoder/Driver CMOS MSI (Low−Power Complementary MOS) BCD至七段锁存器/解码器/驱动器CMOS MSI （低功耗互补MOS ）解码器驱动器锁存器 CD
文件：	总10页 (文件大小：108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC14513B_06 [ONSEMI]

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