MC14518BDW [ONSEMI]
Dual Up Counters; 双专柜
| 型号： | MC14518BDW |
| 厂家： | 
ONSEMI |
| 描述： | Dual Up Counters |
| 文件： | 总8页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS P–channel and N–channel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4–stage
counters. The counter stages are type D flip–flops, with
interchangeable Clock and Enable lines for incrementing on either the
positive–going or negative–going transition as required when
cascading multiple stages. Each counter can be cleared by applying a
high level on the Reset line. In addition, the MC14518B will count out
of all undefined states within two clock periods. These complementary
MOS up counters find primary use in multi–stage synchronous or
ripple counting applications requiring low power dissipation and/or
high noise immunity.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14518BCP
AWLYYWW
1
• Diode Protection on All Inputs
16
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Internal and External Speeds
• Logic Edge–Clocked Design — Incremented on Positive Transition
of Clock or Negative Transition on Enable
14518B
SOIC–16
DW SUFFIX
CASE 751G
AWLYYWW
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
1
16
SOEIAJ–16
F SUFFIX
CASE 966
MC14518B
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
1
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
V , V
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
in out
DD
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
ORDERING INFORMATION
Device
Package
PDIP–16
SOIC–16
Shipping
T
Operating Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
MC14518BCP
MC14518BDW
2000/Box
47/Rail
T
stg
T
Lead Temperature
L
(8–Second Soldering)
MC14518BDWR2
MC14518BF
SOIC–16 1000/Tape & Reel
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
MC14518BFEL
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14518B/D
MC14518B
PIN ASSIGNMENT
C
1
2
3
4
5
6
7
8
16
15
V
DD
A
E
A
R
B
Q0
A
14 Q3
B
Q1
A
13 Q2
B
Q2
A
12 Q1
B
Q3
A
11 Q0
B
R
A
10
9
E
B
V
SS
C
B
BLOCK DIAGRAM
CLOCK
1
Q0
Q1
Q2
Q3
3
4
5
6
C
2
ENABLE
R
R
7
CLOCK
9
11
12
13
14
Q0
Q1
Q2
Q3
C
10
ENABLE
15
V
V
= PIN 16
= PIN 8
DD
SS
TRUTH TABLE
Clock Enable Reset
Action
1
X
0
0
0
0
0
0
0
1
Increment Counter
Increment Counter
No Change
0
X
No Change
No Change
1
No Change
X
X
Q0 thru Q3 = 0
X = Don’t Care
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2
MC14518B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (0.6 µA/kHz) f + I
T
I = (1.2 µA/kHz) f + I
T
I = (1.7 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.002.
T
L
DD
SS
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3
MC14518B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
All Types
(8.)
Characteristic
Output Rise and Fall Time
Symbol
V
DD
Unit
Min
Typ
Max
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
L
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
TLH THL
, t
= (0.55 ns/pF) C + 9.5 ns
TLH THL
L
Propagation Delay Time
Clock to Q/Enable to Q
t
t
,
ns
ns
PLH
PHL
PHL
w(H)
t
t
t
, t
= (1.7 ns/pF) C + 215 ns
= (0.66 ns/pF) C + 97 ns
L
= (0.5 ns/pF) C + 75 ns
L
5.0
10
15
—
—
—
280
115
80
560
230
160
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Reset to Q
t
t
t
t
= (1.7 ns/pF) C + 265 ns
5.0
10
15
—
—
—
330
130
90
650
230
170
PHL
PHL
PHL
L
= (0.66 ns/pF) C + 117 ns
L
= (0.66 ns/pF) C + 95 ns
L
Clock Pulse Width
t
t
5.0
10
15
200
100
70
100
50
35
—
—
—
ns
MHz
µs
w(L)
Clock Pulse Frequency
Clock or Enable Rise and Fall Time
Enable Pulse Width
f
cl
5.0
10
15
—
—
—
2.5
6.0
8.0
1.5
3.0
4.0
t
, t
5.0
10
15
—
—
—
—
—
—
15
5
4
THL TLH
t
5.0
10
15
440
200
140
220
100
70
—
—
—
ns
WH(E)
Reset Pulse Width
t
5.0
10
15
280
120
90
125
55
40
—
—
—
ns
WH(R)
Reset Removal Time
t
5.0
10
15
– 5
15
20
– 45
– 15
– 5
—
—
—
ns
rem
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
0.01 µF
CERAMIC
500 µF
I
D
PULSE
GENERATOR
Q0
C
Q1
Q2
Q3
C
L
E
R
C
L
C
L
C
L
V
SS
20 ns
20 ns
90%
50%
10%
V
SS
VARIABLE
WIDTH
Figure 1. Power Dissipation Test Circuit and Waveform
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4
MC14518B
20 ns
20 ns
V
DD
V
DD
90%
50%
10%
CLOCK
INPUT
Q0
PULSE
GENERATOR
V
SS
C
E
t
t
WL
WH
Q1
Q2
Q3
t
t
PHL
PLH
C
L
90%
C
L
R
50%
10%
C
L
C
L
V
Q
SS
t
r
t
f
Figure 2. Switching Time Test Circuit and Waveforms
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17 18
CLOCK
ENABLE
RESET
0
1
2
3
4
5
6
7
8
9 0
Q0
Q1
Q2
Q3
MC14518B
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3 4
Q0
Q1
Q2
Q3
MC14520B
Figure 3. Timing Diagram
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5
MC14518B
Q0
Q1
Q2
Q3
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
R
R
R
R
RESET
ENABLE
CLOCK
Figure 4. Decade Counter (MC14518B) Logic Diagram
(1/2 of Device Shown)
Q0
Q1
Q2
Q3
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
Q
Q
C
R
R
R
R
RESET
ENABLE
CLOCK
Figure 5. Binary Counter (MC14520B) Logic Diagram
(1/2 of Device Shown)
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6
MC14518B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
SOIC–16
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–03
ISSUE B
A
D
16
9
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
8
MILLIMETERS
B
16X B
DIM MIN
MAX
2.65
0.25
0.49
0.32
10.45
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
10.15
7.40
M
S
S
0.25
T A
B
e
1.27 BSC
H
h
L
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
14X
e
C
T
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7
MC14518B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
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MC14518B/D
相关型号：
MC14518BDWR2
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, SOIC-16
MOTOROLA
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