MC14536 [ONSEMI]
Programmable Timer; 可编程定时器
ONSEMI 
The MC14536B programmable timer is a 24–stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
on–chip RC oscillator or an external clock are provided. An on–chip
monostable circuit incorporating a pulse–type output has been
included. By selecting the appropriate counter stage in conjunction
with the appropriate input clock frequency, a variety of timing can be
achieved.
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MARKING
DIAGRAMS
0
24
• 24 Flip–Flop Stages — Will Count From 2 to 2
• Last 16 Stages Selectable By Four–Bit Select Code
• 8–Bypass Input Allows Bypassing of First Eight Stages
• Set and Reset Inputs
16
PDIP–16
P SUFFIX
CASE 648
MC14536BCP
AWLYYWW
• Clock Inhibit and Oscillator Inhibit Inputs
• On–Chip RC Oscillator Provisions
1
16
• On–Chip Monostable Output Provisions
• Clock Conditioning Circuit Permits Operation With Very Long Rise
and Fall Times
14536B
SOIC–16
DW SUFFIX
CASE 751G
• Test Mode Allows Fast Test Sequence
AWLYYWW
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
1
• Capable of Driving Two Low–power TTL Loads or One Low–power
16
Schottky TTL Load Over the Rated Temperature Range
SOEIAJ–16
F SUFFIX
CASE 966
MC14536B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
Symbol
Parameter
Value
Unit
V
A
= Assembly Location
V
DD
DC Supply Voltage Range
–0.5 to +18.0
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
ORDERING INFORMATION
P
Power Dissipation,
per Package (Note 3.)
500
mW
D
Device
Package
PDIP–16
SOIC–16
Shipping
T
A
Operating Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
MC14536BCP
MC14536BDW
2000/Box
47/Rail
T
stg
T
Lead Temperature
(8–Second Soldering)
L
MC14536BDWR2
MC14536BF
SOIC–16 1000/Tape & Reel
SOEIAJ–16 See Note 1.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 5
MC14536B/D
MC14536B
PIN ASSIGNMENT
SET
RESET
1
2
3
4
5
6
7
8
16
V
DD
15 MONO IN
14 OSC INH
13 DECODE
IN 1
OUT 1
OUT 2
12
11
10
9
D
C
B
A
8–BYPASS
CLOCK INH
V
SS
BLOCK DIAGRAM
CLOCK INH.
7
RESET SET 8 BYPASS
2
1
6
OSC. INHIBIT 14
STAGES 9 THRU 24
STAGES
1 THRU 8
IN
1
Q
9
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
3
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
4
OUT
5
A
B
C
D
9
OUT
2
1
10
11
12
DECODER
V
DD
= PIN 16
V
SS
= PIN 8
DECODE
OUT
MONOSTABLE
MULTIVIBRATOR
MONO–IN 15
13
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2
MC14536B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Pins 4 & 5
5.0
5.0
10
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.25
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 2.5 Vdc)
Source
Pin 13
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
mAdc
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
– 3.4
(V = 0.4 Vdc)
Sink
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
±0.1
—
—
±0.00001
±0.1
—
—
±1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (1.50 µA/kHz) f + I
T
I = (2.30 µA/kHz) f + I
T
I = (3.55 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.003.
T
L
DD
SS
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3
MC14536B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
(8.)
Characteristic
Symbol
V
DD
Min
Typ
Max
Unit
Output Rise and Fall Time (Pin 13)
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
L
TLH THL
Propagation Delay Time
t
,
ns
PLH
Clock to Q1, 8–Bypass (Pin 6) High
t
PHL
t
t
t
, t
= (1.7 ns/pF) C + 1715 ns
= (0.66 ns/pF) C + 617 ns
L
5.0
10
15
—
—
—
1800
650
450
3600
1300
1000
PLH PHL
L
, t
PLH PHL
, t
= (0.5 ns/pF) C + 425 ns
PLH PHL
L
Clock to Q1, 8–Bypass (Pin 6) Low
t
t
,
µs
µs
ns
PLH
t
t
t
t
, t
= (1.7 ns/pF) C + 3715 ns
= (0.66 ns/pF) C + 1467 ns
L
= (0.5 ns/pF) C + 1075 ns
L
5.0
10
15
—
—
—
3.8
1.5
1.1
7.6
3.0
2.3
PLH PHL
L
PHL
, t
PLH PHL
, t
PLH PHL
Clock to Q16
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 6915 ns
= (0.66 ns/pF) C + 2967 ns
L
= (0.5 ns/pF) C + 2175 ns
L
t
5.0
10
15
—
—
—
7.0
3.0
2.2
14
6.0
4.5
PHL PLH
L
PHL
, t
PHL PLH
, t
PHL PLH
Reset to Q
t
n
PHL
t
t
t
= (1.7 ns/pF) C + 1415 ns
5.0
10
15
—
—
—
1500
600
450
3000
1200
900
PHL
PHL
PHL
L
= (0.66 ns/pF) C + 567 ns
L
= (0.5 ns/pF) C + 425 ns
L
Clock Pulse Width
t
5.0
10
15
600
200
170
300
100
85
—
—
—
ns
MHz
—
WH
Clock Pulse Frequency
(50% Duty Cycle)
f
cl
5.0
10
15
—
—
—
1.2
3.0
5.0
0.4
1.5
2.0
Clock Rise and Fall Time
Reset Pulse Width
t
,
5.0
10
15
TLH
t
No Limit
THL
t
5.0
10
15
1000
400
300
500
200
150
—
—
—
ns
WH
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14536B
PIN DESCRIPTIONS
INPUTS
OSC INHIBIT (Pin 14) — A high level on this pin stops
the RC oscillator which allows for very low–power standby
operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONO–IN (Pin 15) — Used as the timing pin for the
on–chip monostable multivibrator. If the Mono–In input is
SET (Pin 1) — A high on Set asynchronously forces
Decode Out to a high level. This is accomplished by setting
an output conditioning latch to a high level while at the same
time resetting the 24 flip–flop stages. After Set goes low
(inactive), the occurrence of the first negative clock
transition on IN causes Decode Out to go low. The
1
connected to V , the monostable circuit is disabled, and
SS
counter’s flip–flop stages begin counting on the second
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
negative clock transition of IN . When Set is high, the
on–chip RC oscillator is disabled. This allows for very
low–power standby operation.
1
between Mono–In and V . This resistor and the device’s
DD
internal capacitance will determine the minimum output
pulse widths. With the addition of an external capacitor to
RESET (Pin 2) — A high on Reset asynchronously
forces Decode Out to a low level; all 24 flip–flop stages are
also reset to a low level. Like the Set input, Reset disables
the on–chip RC oscillator for standby operation.
V
, the pulse width range may be extended. For reliable
SS
operation the resistor value should be limited to the range of
5 kΩ to 100 kΩ and the capacitor value should be limited to
a maximum of 1000 pf. (See figures 3, 4, 5, and 10).
A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the
flip–flop stage to be connected to Decode Out. (See the truth
tables.)
IN (Pin 3) — The device’s internal counters advance on
1
the negative–going edge of this input. IN may be used as an
1
external clock input or used in conjunction with OUT and
1
OUT to form an RC oscillator. When an external clock is
2
used, both OUT and OUT may be left unconnected or
1
2
used to drive 1 LSTTL or several CMOS loads.
OUTPUTS
8–BYPASS (Pin 6) — A high on this input causes the first
8 flip–flop stages to be bypassed. This device essentially
becomes a 16–stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) — A high on this input
disconnects the first counter stage from the clocking source.
This holds the present count and inhibits further counting.
However, the clocking source may continue to run.
Therefore, when Clock Inhibit is brought low, no oscillator
start–up time is required. When Clock Inhibit is low, the
counter will start counting on the occurrence of the first
OUT , OUT (Pin 4, 5) — Outputs used in conjunction
1
2
with IN to form an RC oscillator. These outputs are
1
0
buffered and may be used for 2 frequency division of an
external clock.
DECODE OUT (Pin 13) — Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flip–flop
stages into three 8–stage sections to facilitate a fast test
sequence. The test mode is enabled when 8–Bypass, Set and
Reset are at a high level. (See Figure 8.)
negative edge of the clocking source at IN .
1
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5
MC14536B
TRUTH TABLES
Input
Input
Stage Selected
for Decode Out
Stage Selected
for Decode Out
8–Bypass
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8–Bypass
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FUNCTION TABLE
Clock
Inh
OSC
Inh
Decode
Out
In
1
Set
Reset
Out 1
Out 2
0
0
0
0
No
Change
0
0
0
0
Advance to
next state
X
X
X
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
1
0
—
—
No
Change
X
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
No
Change
X
No
Change
Advance to
next state
X = Don’t Care
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6
MC14536B
LOGIC DIAGRAM
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7
MC14536B
TYPICAL RC OSCILLATOR CHARACTERISTICS
(For Circuit Diagram See Figure 11 In Application)
8.0
4.0
100
V
DD
= 10 V
V
DD
= 15 V
50
f AS A FUNCTION
OF R
20
10
TC
(C = 1000 pF)
0
(R ≈ 2R
)
TC
S
10 V
5.0
–4.0
f AS A FUNCTION
OF C
2.0
1.0
0.5
–8.0
–12
–16
(R = 56 kΩ)
TC
5.0 V
(R = 120 k)
S
0.2
0.1
R
= 56 kΩ,
R = 0, f = 10.15 kHz @ V = 10 V, T = 25°C
S DD A
R = 120 kΩ, f = 7.8 kHz @ V = 10 V, T = 25°C
TC
C = 1000 pF
S
DD
A
–55
–25
0
25
50
75
100
125
1.0 k
10 k
TC
0.001
100 k
1.0 M
0.1
R
, RESISTANCE (OHMS)
* Device Only.
T , AMBIENT TEMPERATURE (°C)*
A
0.0001
0.01
C, CAPACITANCE (µF)
Figure 1. RC Oscillator Stability
Figure 2. RC Oscillator Frequency as a
Function of RTC and C
MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 10 In Application)
100
100
FORMULA FOR CALCULATING t IN
FORMULA FOR CALCULATING t IN
W
W
MICROSECONDS IS AS FOLLOWS:
MICROSECONDS IS AS FOLLOWS:
t
W
= 0.00247 R • C 0.85
t = 0.00247 R • C 0.85
W X X
X
X
WHERE R IS IN kΩ, C IN pF.
WHERE R IS IN kΩ, C IN pF.
X
X
10
10
R = 100 kΩ
X
R = 100 kΩ
X
50 kΩ
50 kΩ
1.0
0.1
1.0
0.1
10 kΩ
5 kΩ
10 kΩ
5 kΩ
T = 25°C
T = 25°C
A
A
V
= 5 V
V
= 10 V
DD
DD
1.0
10
100
1000
1.0
10
100
1000
C , EXTERNAL CAPACITANCE (pF)
X
C , EXTERNAL CAPACITANCE (pF)
X
Figure 3. Typical CX versus Pulse Width
@ VDD = 5.0 V
Figure 4. Typical CX versus Pulse Width
@ VDD = 10 V
100
FORMULA FOR CALCULATING t IN
W
MICROSECONDS IS AS FOLLOWS:
t
W
= 0.00247 R • C 0.85
X X
WHERE R IS IN kΩ, C IN pF.
X
10
R = 100 kΩ
X
50 kΩ
1.0
0.1
10 kΩ
5 kΩ
T = 25°C
A
V
DD
= 15 V
1.0
10
100
1000
C , EXTERNAL CAPACITANCE (pF)
X
Figure 5. Typical CX versus Pulse Width
@ VDD = 15 V
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8
MC14536B
V
DD
0.01 µF
CERAMIC
I
D
500 µF
SET
20 ns
20 ns
IN
RESET OUT 1
8–BYPASS
C
L
V
DD
50%
1
PULSE
IN
1
GENERATOR
t
t
WH
WL
C INH
MONO IN
OSC INH
A
SET
OUT 1
OUT
2
RESET
90%
10%
50%
t
OUT
t
C
L
8–BYPASS
IN
PULSE
GENERATOR
1
PHL
PLH
B
t
t
THL
C INH
MONO IN
OSC INH
A
TLH
C
D
DECODE
OUT
OUT
2
C
L
V
SS
B
C
D
DECODE
OUT
20 ns
20 ns
C
L
V
SS
90%
10%
50%
50%
DUTY CYCLE
Figure 6. Power Dissipation Test
Circuit and Waveform
Figure 7. Switching Time Test Circuit and Waveforms
V
DD
FUNCTIONAL TEST SEQUENCE
SET
Test function (Figure 8) has been included for the
reduction of test time required to exercise all 24 counter
stages. This test function divides the counter into three
8–stage sections and 255 counts are loaded in each of the
8–stage sections in parallel. All flip–flops are now at a “1”.
The counter is now returned to the normal 24–stages in
RESET OUT 1
8–BYPASS
PULSE
GENERATOR
IN
1
C INH
MONO IN
OSC INH
A
OUT
2
series configuration. One more pulse is entered into In
1
B
which will cause the counter to ripple from an all “1” state
to an all “0” state.
C
D
DECODE
OUT
V
SS
Figure 8. Functional Test Circuit
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9
MC14536B
FUNCTIONAL TEST SEQUENCE
Outputs
Inputs
Comments
Decade Out
Q1 thru Q24
In
Set
0
Reset
8–Bypass
1
All 24 stages are in Reset mode.
1
1
0
1
1
1
1
1
1
0
0
0
1
Counter is in three 8 stage sections in parallel mode.
First “1” to “0” transition of clock.
1
1
0
—
—
—
1
1
1
255 “1” to “0” transitions are clocked in the counter.
0
0
1
0
1
0
1
0
1
1
The 255 “1” to “0” transition.
Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1
0
0
0
0
0
0
0
1
0
In Switches to a “1”.
1
Counter Ripples from an all “1” state to an all “0” state.
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10
MC14536B
+V
16
V
DD
6
8–BYPASS
4
5
9
A
OUT 1
OUT 2
10
B
11
C
12
D
2
RESET
14
OSC INH
15
MONO–IN
1
PULSE
GEN.
SET
7
CLOCK INH
3
13
DECODE OUT
IN
1
PULSE
GEN.
V
SS
8
CLOCK
IN
1
SET
CLOCK INH
DECODE OUT
POWER UP
NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8–Bypass,
n
A, B, C, and D inputs, and the clock input period. A 2 frequency division (where n = the
0
number of stages selected from the truth table) is obtainable at Decode Out. A 2 –divided
output of IN can be obtained at OUT and OUT .
1
1
2
Figure 9. Time Interval Configuration Using an External Clock, Set,
and Clock Inhibit Functions
(Divide–by–2 Configured)
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11
MC14536B
+V
16
V
DD
6
9
8–BYPASS
R
X
4
5
A
OUT 1
OUT 2
10
11
12
2
B
C
D
PULSE
GEN.
RESET
SET
1
7
CLOCK INH
MONO–IN
CLOCK INH
15
14
3
13
DECODE OUT
IN
1
CLOCK
V
SS
C
X
8
IN
1
RESET
*t ≈ .00247 • R • C 0.85
w
X
X
t
R
C
in µsec
w
DECODE OUT
in kΩ
X
X
in pF
*t
w
POWER UP
NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
n
input low enables the chip’s internal counters. After Reset goes low, the 2 /2 negative transition of the clock input causes
Decode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The pulse width of the
n
output is dependent on the external timing components. The second and all subsequent pulses occur at 2 x (the clock
period) intervals where n = the number of stages selected from the truth table.
Figure 10. Time Interval Configuration Using an External Clock, Reset,
and Output Monostable to Achieve a Pulse Output
(Divide–by–4 Configured)
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12
MC14536B
+V
R
S
16
V
DD
6
9
8–BYPASS
4
5
A
OUT 1
OUT 2
10
11
12
2
C
B
C
R
TC
D
PULSE
GEN.
RESET
SET
14
15
CLOCK INH
MONO–IN
CLOCK INH
1
7
3
13
DECODE OUT
IN
1
V
SS
8
RESET
OUT 1
OUT 2
1
f
osc
2.3R
C
tc
DECODE OUT
tc
≥ R
R
s
= Hz
= Ohms
= FARADS
F
R
C
t
w
POWER UP
NOTE: This circuit is designed to use the on–chip oscillation function. The oscillator frequency is deter-
mined by the external R and C components. When power is first applied to the device, Decode Out
initializes to a high state. Because this output is tied directly to the Osc–Inh input, the oscillator is
disabled.Thisputsthedeviceinalow–currentstandbycondition. TherisingedgeoftheResetpulse
will cause the output to go low. This in turn causes Osc–Inh to go low. However, while Reset is high,
the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low
n
for 2 /2 of the oscillator’s period. After the part times out, the output again goes high.
Figure 11. Time Interval Configuration Using On–Chip RC Oscillator and
Reset Input to Initiate Time Interval
(Divide–by–2 Configured)
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13
MC14536B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
SOIC–16
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–03
ISSUE B
A
D
16
9
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
8
MILLIMETERS
B
16X B
DIM MIN
MAX
2.65
0.25
0.49
0.32
10.45
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
10.15
7.40
M
S
S
0.25
T A
B
e
1.27 BSC
H
h
L
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
14X
e
C
T
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14
MC14536B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
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15
MC14536B
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