MC14543B_06 [ONSEMI]
BCD−to−Seven Segment Latch/Decoder/Driver for Liquid Crystals; BCD至七段锁存器/解码器/驱动器，用于液晶
| 型号： | MC14543B_06 |
| 厂家： | 
ONSEMI |
| 描述： | BCD−to−Seven Segment Latch/Decoder/Driver for Liquid Crystals |
| 文件： | 总8页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14543B
BCD−to−Seven Segment
Latch/Decoder/Driver for
Liquid Crystals
The MC14543B BCD−to−seven segment latch/decoder/driver is
designed for use with liquid crystal readouts, and is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit provides the functions of a 4−bit storage latch and an 8421
BCD−to−seven segment decoder and driver. The device has the
capability to invert the logic levels of the output combination. The
phase (Ph), blanking (BI), and latch disable (LD) inputs are used to
reverse the truth table phase, blank the display, and store a BCD code,
respectively. For liquid crystal (LC) readouts, a square wave is applied
to the Ph input of the circuit and the electrically common backplane of
the display. The outputs of the circuit are connected directly to the
segments of the LC readout. For other types of readouts, such as
light−emitting diode (LED), incandescent, gas discharge, and
fluorescent readouts, connection diagrams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
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MARKING
DIAGRAMS
16
PDIP−16
MC14543BCP
AWLYYWWG
P SUFFIX
CASE 648
1
1
16
SOIC−16
D SUFFIX
CASE 751B
14543BG
AWLYWW
1
1
Features
• Latch Storage of Code
• Blanking Input
16
SOEIAJ−16
F SUFFIX
CASE 966
MC14543B
ALYWG
• Readout Blanking on All Illegal Input Combinations
1
1
• Direct LED (Common Anode or Cathode) Driving Capability
• Supply Voltage Range = 3.0 V to 18 V
• Capable of Driving 2 Low−power TTL Loads, 1 Low−power Schottky
TTL Load or 2 HTL Loads Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4056A (with Pin 7 Tied to V ).
• Chip Complexity: 207 FETs or 52 Equivalent Gates
• Pb−Free Packages are Available*
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
SS
G
= Pb−Free Package
ORDERING INFORMATION
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Parameter
Symbol
Value
−0.5 to +18.0
Unit
V
DC Supply Voltage Range
V
DD
Input Voltage Range, All Inputs
DC Input Current per Pin
V
−0.5 to V +0.5
V
in
DD
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper
I
10
mA
mW
°C
in
Power Dissipation per Package (Note 1)
Operating Temperature Range
Storage Temperature Range
P
500
D
T
A
−55 to +125
−65 to +150
operation, V and V should be constrained to the
in
out
T
stg
°C
range V v (V or V ) v V
.
DD
SS
in
out
Maximum Continuous Output Drive
Current (Source or Sink)
I
I
10
mA
OHmax
OLmax
Unused inputs must always be tied to an appropriate
(per Output)
logic voltage level (e.g., either V or V ). Unused
SS
DD
outputs must be left open.
Maximum Continuous Output Power
(Source or Sink) (Note 2)
P
P
70
mW
OHmax
OLmax
(per Output)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Packages: – 7.0 mW/_C From 65_C To 125_C
2. P
= I
(V − V ) and P
= I (V − V
)
SS
OHmax
OH
OH
DD
OLmax
OL
OL
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MC14543B/D
MC14543B
TRUTH TABLE
Inputs
Outputs
LD BI Ph*
D
C
B
A
a
b
c
d
e
f
g
Display
X
1
0
X
X
X
X
0
0
0
0
0
0
0
Blank
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
1
0
1
0
0
0
0
0
1
1
0
1
2
3
PIN ASSIGNMENT
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
0
4
5
6
7
LD
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
f
B
g
e
d
c
b
a
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
8
9
D
Blank
Blank
A
PH
BI
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
V
SS
0
†
0
†
0
†
X
X
X
X
**
**
†
Inverse of Output
Combinations
Above
Display
as above
X = Don’t care
† = Above Combinations
* = For liquid crystal readouts, apply a square wave to Ph
For common cathode LED readouts, select Ph = 0
For common anode LED readouts, select Ph = 1
** = Depends upon the BCD code previously applied when LD = 1
ORDERING INFORMATION
†
Device
MC14543BCP
Package
Shipping
PDIP−16
25 Units / Rail
MC14543BCPG
PDIP−16
(Pb−Free)
MC14543BD
SOIC−16
48 Units / Rail
2500 / Tape & Reel
50 Units / Rail
MC14543BDG
SOIC−16
(Pb−Free)
MC14543BDR2
SOIC−16
MC14543BDR2G
SOIC−16
(Pb−Free)
MC14543BF
SOEIAJ−16
MC14543BFG
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MC14543B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
125_C
V
Typ
DD
(Note 3)
Min
Max
Min
Max
Min
Max
Vdc
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
OL
V
in
= V or 0
DD
V
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
OH
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
Vdc
IH
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 0.5 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
10
15
– 3.0
– 0.64
−
– 1.6
– 4.2
−
−
−
−
−
– 2.4
– 0.51
−
– 1.3
– 3.4
– 4.2
– 0.88
– 10.1
– 2.25
– 8.8
−
−
−
−
−
– 1.7
– 0.36
−
– 0.9
– 2.4
−
−
−
−
OH
OH
OH
OH
OH
(V = 0.4 Vdc)
I
5.0
10
10
15
0.64
1.6
−
−
−
−
−
0.51
1.3
−
0.88
2.25
10.1
8.8
−
−
−
−
0.36
0.9
−
−
−
−
mAdc
OL
OL
(V = 0.5 Vdc)
OL
(V = 9.5 Vdc)
OL
(V = 1.5 Vdc)
OL
4.2
3.4
2.4
Input Current
Input Capacitance
Quiescent Current (Per Package)
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
pF
in
C
in
I
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
DD
V
in
= 0 or V
,
DD
I
= 0 mA
out
Total Supply Current (Note 4, 5)
(Dynamic plus Quiescent,
Per Package)
I
5.0
10
15
I
I
I
= (1.6 mA/kHz) f + I
= (3.1 mA/kHz) f + I
= (4.7 mA/kHz) f + I
mAdc
T
T
T
T
DD
DD
DD
(C = 50 pF on all outputs, all
L
buffers switching)
3. Noise immunity specified for worst−case input combination.
Noise Margin for both “1” and “0” level
=
=
=
1.0 V min @ V = 5.0 V
DD
2.0 V min @ V = 10 V
DD
2.5 V min @ V = 15 V
DD
−3
4. To calculate total supply current at loads other than 50 pF: I (C ) = I (50 pF) + 3.5 x 10 (C − 50) V f where: I is in mA (per package),
T
L
T
L
DD
T
C in pF, V in V, and f in kHz is input frequency.
L
DD
5. The formulas given are for the typical characteristics only at 25_C.
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3
MC14543B
SWITCHING CHARACTERISTICS (Note 6) (C = 50 pF, T = 25_C)
L
A
Characteristic
Symbol
V
Min
Typ
Max
Unit
DD
Output Rise Time
t
t
t
t
ns
TLH
THL
PLH
PHL
t
t
t
= (3.0 ns/pF) C + 30 ns
= (1.5 ns/pF) C + 15 ns
= (1.1 ns/pF) C + 10 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
TLH
TLH
TLH
L
L
L
Output Fall Time
ns
ns
ns
t
t
t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
= (0.55 ns/pF) C + 12.5 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
THL
THL
THL
L
L
L
Turn−Off Delay Time
t
t
t
= (1.7 ns/pF) C + 520 ns
= (0.66 ns/pF) C + 217 ns
= (0.5 ns/pF) C + 160 ns
5.0
10
15
−
−
−
605
250
185
1210
500
370
PLH
PLH
PLH
L
L
L
Turn−On Delay Time
t
t
t
= (1.7 ns/pF) C + 420 ns
5.0
10
15
−
−
−
505
205
155
1650
660
495
PHL
PHL
PHL
L
= (0.66 ns/pF) C + 172 ns
L
= (0.5 ns/pF) C + 130 ns
L
Setup Time
t
5.0
10
15
350
450
500
−
−
−
ns
ns
ns
su
Hold Time
t
5.0
10
15
40
30
20
−
−
−
h
Latch Disable Pulse Width (Strobing Data)
t
5.0
10
15
250
100
80
125
50
40
−
−
−
WH
6. The formulas given are for the typical characteristics only.
LOGIC DIAGRAM
BIꢀ7
V
= PIN 16
= PIN 8
DD
V
SS
ꢀ9ꢀa
Aꢀ5
Bꢀ3
10ꢀb
11ꢀc
12ꢀd
13ꢀe
15ꢀf
Cꢀ2
Dꢀ4
14ꢀg
LDꢀ1
PHASEꢀ6
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4
−
12
−
18
24
6.0
−
0
−
16
−ꢁ12
−ꢁ8.0
−ꢁ4.0
0
0
4.0
8.0
16
−
6.0
18
12
MC14543B
0
24
V
= 15 Vdc
DD
V
= 5.0 Vdc
DD
P
= 70 mWdc
OHmax
V
= 10 Vdc
DD
V
= 10 Vdc
DD
P
= 70 mWdc
OLmax
V
= 15 Vdc
V
= 5.0 Vdc
DD
DD
V
= 0 Vdc
V
= 0 Vdc
12
SS
SS
(V − V ), SOURCE DEVICE VOLTAGE (Vdc)
OH DD
(V − V ), SINK DEVICE VOLTAGE (Vdc)
OL SS
Figure 1. Typical Output Source Characteristics
Figure 2. Typical Output Sink Characteristics
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.
20 ns
20 ns
V
V
V
V
DD
SS
OH
OL
90%
10%
C
g
50%
t
t
PLH
PHL
90%
50%
10%
t
t
TLH
THL
(b) Inputs D, Ph, and BI low, and Inputs A and B high.
20 ns
50%
V
V
V
V
V
V
DD
SS
DD
SS
OH
OL
90%
LD
C
10%
t
su
t
h
Inputs BI and Ph low, and Inputs D and LD high.
f in respect to a system clock.
50%
50%
All outputs connected to respective C loads.
L
20 ns
50%
20 ns
A, B, AND C
g
V
V
DD
SS
90%
1
10%
2f
50% DUTY CYCLE
(c) Data DCBA strobed into latches
V
V
DD
SS
V
V
50%
LD
OH
OL
ANY OUTPUT
t
WH
Figure 3. Dynamic Power Dissipation
Signal Waveforms
Figure 4. Dynamic Signal Waveforms
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5
MC14543B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIQUID CRYSTAL (LC) READOUT
INCANDESCENT READOUT
APPROPRIATE
VOLTAGE
MC14543B
ONE OF SEVEN SEGMENTS
OUTPUT
Ph
COMMON
BACKPLANE
MC14543B
OUTPUT
Ph
SQUARE WAVE
(V TO V
)
DD
SS
V
SS
LIGHT EMITTING DIODE (LED) READOUT
GAS DISCHARGE READOUT
APPROPRIATE
VOLTAGE
V
DD
COMMON
CATHODE LED
COMMON
ANODE LED
MC14543B
OUTPUT
Ph
MC14543B
OUTPUT
Ph
MC14543B
OUTPUT
Ph
V
SS
V
DD
NOTE: Bipolar transistors may be added for gain (for V v 10 V or I ≥ 10 mA).
DD
out
V
SS
CONNECTIONS TO SEGMENTS
a
f
g
b
e
c
d
V
= PIN 16
= PIN 8
DD
V
SS
DISPLAY
0
1
2
3
4
5
6
7
8
9
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6
MC14543B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
J
0.21
0.38
3.30
7.74
10
G
2.80
7.50
0
D 16 PL
M
M
0.25 (0.010)
T A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
5.80
0.25
0.25
0.25
7
6.20
0.50
0.008
0.004
0
0.229
0.010
0.009
0.009
7
0.244
0.019
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
D
16 PL
M
S
S
0.25 (0.010)
T B
A
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7
MC14543B
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
NOTES:
ꢂꢀ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
16
9
E
ꢂꢀ2. CONTROLLING DIMENSION: MILLIMETER.
ꢂꢀ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
Q
1
H
E
E
M
_
ꢂꢀ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢂꢀ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
A
−−−
0.05
0.35
0.10
9.90
5.10
A
A
1
0.002
0.008
0.020
0.011
0.413
0.215
1
b
0.13 (0.005)
b
c
0.014
0.007
0.390
0.201
0.10 (0.004)
M
D
E
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
0
0.70
−−−
10
10
0.035
−−− 0.031
M
Q
0
0.028
_
_
_
_
0.90
0.78
1
Z
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