MC14551BCPG [ONSEMI]
Quad 2−Channel Analog Multiplexer/Demultiplexer; 四2通道模拟多路复用器/多路解复用器
| 型号： | MC14551BCPG |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2−Channel Analog Multiplexer/Demultiplexer |
| 文件： | 总10页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14551B
Quad 2−Channel Analog
Multiplexer/Demultiplexer
The MC14551B is a digitally−controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved.
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MARKING
Features
• Triple Diode Protection on All Control Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (V − V ) = 3.0 to 18 V
DIAGRAMS
16
DD
EE
PDIP−16
P SUFFIX
CASE 648
MC14551BCP
AWLYYWWG
Note: V must be v V
EE
SS
• Linearized Transfer Characteristics
1
1
• Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical
• For Low R , Use The HC4051, HC4052, or HC4053 High−Speed
ON
16
CMOS Devices
SOIC−16
D SUFFIX
CASE 751B
14551BG
AWLYWW
• Switch Function is Break Before Make
• Pb−Free Packages are Available*
1
1
MAXIMUM RATINGS
16
Parameter
Symbol
Value
Unit
SOEIAJ−16
F SUFFIX
CASE 966
DC Supply Voltage Range
V
– 0.5 to + 18.0
V
MC14551B
ALYWG
DD
(Referenced to V , V ≥ V )
EE
SS
EE
1
Input or Output Voltage (DC or Transient) V , V
– 0.5 to V
+ 0.5
V
in out
DD
1
(Referenced to V for Control Input and
SS
V
EE
for Switch I/O)
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
Input Current (DC or Transient),
per Control Pin
I
10
mA
in
Switch Through Current
I
25
mA
mW
_C
sw
G
= Pb−Free Package
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
P
T
500
D
– 55 to + 125
– 65 to + 150
260
A
ORDERING INFORMATION
Storage Temperature Range
T
_C
stg
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Lead Temperature (8–Second Soldering)
T
_C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: − 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V for control inputs and V ≤ (V or V
)
out
SS
in
out
DD
EE
in
≤ V for Switch I/O.
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V , V or V ). Unused outputs must be left open.
SS
EE
DD
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MC14551B/D
MC14551B
PIN ASSIGNMENT
W1
X0
X1
X
1
2
3
4
5
6
7
8
16
V
DD
CONTROL
9
W
14
ꢀ4
15 W0
W0
W1
X0
X1
Y0
Y1
Z0
Z1
15
1
14
13
W
Z
X
COMMONS
OUT/IN
2
3
SWITCHES
IN/OUT
Y
12 Z1
11 Z0
10 Y1
Y
Z
ꢀ5
13
6
Y0
10
11
12
V
EE
SS
V
9
CONTROL
Control
ON
V
V
V
= Pin 16
= Pin 8
= Pin 7
DD
SS
EE
0
1
W0 X0 Y0 Z0
W1 X1 Y1 Z1
NOTE: Control Input referenced to V , Analog Inputs and
SS
Outputs reference to V . V must be v V
.
SS
EE
EE
ORDERING INFORMATION
†
Device
MC14551BCP
Package
Shipping
PDIP−16
25 Units / Rail
48 Units / Rail
MC14551BCPG
PDIP−16
(Pb−Free)
MC14551BD
SOIC−16
MC14551BDG
SOIC−16
(Pb−Free)
MC14551BDR2
SOIC−16
2500 / Tape & Reel
50 Units / Rail
MC14551BDR2G
SOIC−16
(Pb−Free)
MC14551BF
SOEIAJ−16
SOEIAJ−16
(Pb−Free)
MC14551BFG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MC14551B
ELECTRICAL CHARACTERISTICS
– 55_C
25_C
Typ
125_C
(Note 2)
Min Max Min
Max Min
Max
Characteristic
V
Test Conditions
Symbol
Unit
DD
SUPPLY REQUIREMENTS (Voltages Referenced to V
)
EE
Power Supply Voltage
Range
−
V
– 3.0 ≥ V ≥ V
V
3.0
18
3.0
−
18
3.0
18
V
DD
SS
EE
DD
Quiescent Current Per
Package
5.0
10
15
Control Inputs: V
I
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mA
in =
DD
V
or V
,
SS
DD
Switch I/O: V v V
EE
I/O
v
v V , and DV
DD
switch
500 mV (Note 3 )
Total Supply Current
(Dynamic Plus Quiescent,
Per Package)
5.0
10
15
T = 25_C only (The
I
mA
A
D(AV)
(0.07 mA/kHz) f + I
Typical (0.20 mA/kHz) f + I
(0.36 mA/kHz) f + I
DD
DD
DD
channel component,
(V – V )/R , is
in
out
on
not included.)
CONTROL INPUT (Voltages Referenced to V
)
SS
Low−Level Input Voltage
High−Level Input Voltage
5.0
10
15
R
= per spec,
= per spec
V
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
V
V
on
IL
IH
in
I
off
5.0
10
15
R
on
= per spec,
= per spec
V
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
I
off
Input Leakage Current
Input Capacitance
15
−
V
in
= 0 or V
I
−
−
0.1
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mA
DD
C
−
pF
in
SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to V
)
EE
Recommended Peak−to−
Peak Voltage Into or Out
of the Switch
−
−
Channel On or Off
V
0
0
V
0
−
−
V
0
0
V
V
p–p
I/O
DD
DD
DD
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 3)
Channel On
DV
600
0
600
300
mV
switch
Output Offset Voltage
ON Resistance
−
V
= 0 V, No Load
V
−
−
−
10
−
−
−
mV
in
OO
5.0
10
15
DV
(Note 3),
V
in
v 500 mV
R
−
−
800
400
220
−
−
−
250
120
80
1050
500
280
−
−
−
1200
520
300
W
switch
on
= V or V
IL
IH
(Control), and V = 0 to
in
V
DD
(Switch)
DON Resistance Between
Any Two Channels
in the Same Package
5.0
10
15
DR
−
−
−
70
50
45
−
−
−
25
10
10
70
50
45
−
−
−
135
95
65
W
on
Off−Channel Leakage
Current (Figure 8)
15
V
= V or V
I
off
−
100
−
0.05
100
−
1000
nA
in
IL
IH
(Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O
Capacitance, Common O/I
−
−
Switch Off
C
C
C
−
−
−
−
−
−
10
17
−
−
−
−
−
−
pF
pF
pF
I/O
O/I
I/O
Capacitance, Feedthrough
(Channel Off)
−
−
Pins Not Adjacent
Pins Adjacent
−
−
−
−
−
−
0.15
0.47
−
−
−
−
−
−
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DV ) > 600 mV ( > 300 mV at high temperature), excessive V current may be drawn; i.e. the
switch
DD
current out of the switch may contain both V
and switch input components. The reliability of the device will be unaffected unless the
DD
Maximum Ratings are exceeded. (See first page of this data sheet.)
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3
MC14551B
ELECTRICAL CHARACTERISTICS (C = 50 pF, T = 25_C, V v V
)
SS
L
A
EE
V
– V
Typ
DD
EE
Vdc
(Note 4 )
Characteristic
Symbol
, t
Min
Max
Unit
Propagation Delay Times
Switch Input to Switch Output (R = 10 kW)
t
−
ns
PLH PHL
L
t
t
t
, t
= (0.17 ns/pF) C + 26.5 ns
5.0
10
15
35
15
12
90
40
30
PLH PHL
L
, t
= (0.08 ns/pF) C + 11 ns
PLH PHL
L
, t
= (0.06 ns/pF) C + 9.0 ns
L
PLH PHL
Control Input to Output (R = 10 kW)
t
, t
−
ns
L
PLH PHL
V
= V (Figure 4)
5.0
10
15
350
140
100
875
350
250
EE
SS
Second Harmonic Distortion
−
10
−
−
0.07
−
%
R = 10 kW, f = 1 kHz, V = 5 V
L
in
p−p
Bandwidth (Figure 5)
BW
10
17
−
MHz
R = 1 kW, V = 1/2 (V − V
)
,
L
in
DD
EE p−p
20 Log (V /V ) = − 3 dB, C = 50 pF
out in
L
Off Channel Feedthrough Attenuation, Figure 5
R = 1 kW, V = 1/2 (V − V , f = 55 MHz
−
−
−
10
10
10
−
−
−
– 50
– 50
75
−
−
−
dB
dB
)
EE p−p in
L
in
DD
Channel Separation (Figure 6)
R = 1 kW, V = 1/2 (V − V ) , f = 3 MHz
EE p−p in
L
in
DD
Crosstalk, Control Input to Common O/I, Figure 7
R1 = 1 kW, R = 10 kW, Control t = t = 20 ns
mV
L
r
f
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14551B
V
DD
V
V
DD
DD
IN/OUT
OUT/IN
V
EE
V
DD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
V
EE
Figure 1. Switch Circuit Schematic
16
V
DD
CONTROLꢀ9
LEVEL
CONVERTER
CONTROL
8
V
7
V
EE
SS
W0ꢀ15
W1ꢀꢀ1
14ꢀW
4ꢀꢀX
X0ꢀꢀ2
X1ꢀꢀ3
Y0ꢀꢀ6
Y1ꢀ10
5ꢀꢀY
13ꢀZ
Z0ꢀ11
Z1ꢀ12
Figure 2. MC14551B Functional Diagram
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5
MC14551B
TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
PULSE
GENERATOR
CONTROL
V
out
LOAD
V
R
C
L
L
SOURCE
V
V
DD EE
V
V
EE DD
Figure 3. DV Across Switch
Figure 4. Propagation Delay Times,
Control to Output
Control input used to turn ON or OFF the switch under test.
R
L
ON
CONTROL
V
out
CONTROL
OFF
R
C = 50 pF
L
L
V
out
R
C = 50 pF
L
L
V
in
V
in
V
− V
2
V
− V
2
DD
EE
DD
EE
Figure 5. Bandwidth and Off−Channel
Feedthrough Attenuation
Figure 6. Channel Separation
(Adjacent Channels Used for Setup)
OFF CHANNEL UNDER TEST
V
DD
EE
V
CONTROL
SECTION
OF IC
OTHER
CHANNEL(S)
CONTROL
V
out
V
V
EE
DD
R
C = 50 pF
L
L
R1
V
V
EE
DD
Figure 7. Crosstalk, Control Input
to Common O/I
Figure 8. Off Channel Leakage
V
DD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kW
RANGE
X/Y
PLOTTER
V
DD
V
= V
SS
EE
Figure 9. Channel Resistance (RON) Test Circuit
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6
MC14551B
TYPICAL RESISTANCE CHARACTERISTICS
350
300
350
300
250
200
150
100
250
200
150
T = 125°C
A
T = 125°C
A
100
25°C
−ꢀ55°C
25°C
−ꢀ55°C
50
0
50
0
−ꢀ10 −ꢀ8.0 −ꢀ6.0 −ꢀ4.0 −ꢀ2.0
0
2.0 4.0
6.0 8.0
10
−ꢀ10 −ꢀ8.0 −ꢀ6.0 −ꢀ4.0 −ꢀ2.0
0
2.0 4.0
6.0 8.0 10
V , INPUT VOLTAGE (VOLTS)
in
V , INPUT VOLTAGE (VOLTS)
in
Figure 10. VDD @ 7.5 V, VEE @ – 7.5 V
Figure 11. VDD @ 5.0 V, VEE @ – 5.0 V
700
600
350
300
T = 25°C
A
V
= 2.5 V
500
400
300
200
250
200
150
100
DD
5.0 V
T = 125°C
A
7.5 V
25°C
100
0
−ꢀ55°C
50
0
−ꢀ10 −ꢀ8.0 −ꢀ6.0 −ꢀ4.0 −ꢀ2.0
0
2.0 4.0
6.0 8.0
10
−ꢀ10 −ꢀ8.0 −ꢀ6.0 −ꢀ4.0 −ꢀ2.0
0
2.0 4.0 6.0 8.0 10
V , INPUT VOLTAGE (VOLTS)
in
V , INPUT VOLTAGE (VOLTS)
in
Figure 12. VDD @ 2.5 V, VEE @ – 2.5 V
Figure 13. Comparison at 25_C, VDD @ – VEE
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7
MC14551B
APPLICATIONS INFORMATION
Figure A illustrates use of the on−chip level converter
detailed in Figure 2. The 0−to−5.0 V Digital Control signal is
used to directly control a 9 V analog signal.
signal which allows a 1/2 V margin at each peak. If voltage
transients above V and/or below V are anticipated on the
DD
EE
analog channels, external diodes (D ) are recommended as
p−p
x
The digital control logic levels are determined by V and
shown in Figure B. These diodes should be small signal types
able to absorb the maximum anticipated current surges during
clipping.
DD
V . The V
voltage is the logic high voltage; the V
SS
DD
SS
voltage is logic low. For the example, V = + 5.0 V = logic
DD
high at the control inputs; V = GND = 0 V = logic low.
The absolute maximum potential difference between V
SS
DD
The maximum analog signal level is determined by V
and V is 18 V. Most parameters are specified up to 15 V
DD
EE
and V . The V
voltage determines the maximum
which is the recommended maximum difference between
EE
DD
recommended peak above V . The V voltage determines
V and V .
DD EE
SS
EE
the maximum swing below V . For the example, V – V
Balanced supplies are not required. However, V must be
SS
SS
DD
SS
= 5.0 V maximum swing above V ; V – V = 5.0 V
greater than or equal to V . For example, V = + 10 V, V
SS
SS
EE
EE DD SS
maximum swing below V . The example shows a 4.5 V
= + 5.0 V, and V = – 3.0 V is acceptable. See the table below.
SS
EE
+5 V
−5 V
V
V
V
EE
DD
SS
+4.5 V
9 V
p−p
+5 V
SWITCH
I/O
ANALOG SIGNAL
9 V
p−p
COMMON
O/I
GND
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
MC14551B
CONTROL
0−TO−5 V DIGITAL
CONTROL SIGNAL
−4.5 V
CIRCUITRY
Figure A. Application Example
V
V
DD
DD
D
D
D
D
x
x
x
x
SWITCH
I/O
COMMON
O/I
V
V
EE
EE
Figure B. External Schottky or Germanium Clipping Diodes
POSSIBLE SUPPLY CONNECTIONS
Control Inputs
Logic High/Logic Low
In Volts
V
V
V
EE
In Volts
Maximum Analog Signal Range
In Volts
DD
SS
In Volts
In Volts
+ 8
0
0
0
0
– 8
+ 8/0
+ 5/0
+ 8 to – 8 = 16 V
p–p
+ 5
– 12
0
+ 5 to – 12 = 17 V
p–p
+ 5
+ 5/0
+ 5 to 0 = 5 V
p–p
+ 5
– 5
+ 5/0
+ 5 to – 5 = 10 V
+ 10 to – 5 = 15 V
p–p
+ 10
– 5
+ 10/ + 5
p–p
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8
MC14551B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
H
J
0.21
0.38
3.30
7.74
10
G
2.80
7.50
0
D 16 PL
M
M
0.25 (0.010)
T A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
5.80
0.25
0.25
0.25
7
6.20
0.50
0.008
0.004
0
0.229
0.010
0.009
0.009
7
0.244
0.019
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
D
16 PL
M
S
S
0.25 (0.010)
T B
A
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9
MC14551B
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
NOTES:
ꢂꢀ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
L
E
ꢂꢀ2. CONTROLLING DIMENSION: MILLIMETER.
ꢂꢀ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
Q
1
H
E
E
M
_
ꢂꢀ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢂꢀ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
A
−−−
0.05
0.35
0.10
9.90
5.10
A
A
1
0.002
0.008
0.020
0.011
0.413
0.215
1
b
0.13 (0.005)
b
c
0.014
0.007
0.390
0.201
0.10 (0.004)
M
D
E
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
0.70
−−−
10
10
0.035
−−− 0.031
0
0.028
_
_
_
_
0.90
0.78
1
Z
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MC14551B/D
相关型号：
MC14551BFEL
Single-Ended Multiplexer, 4 Func, 2 Channel, CMOS, PDSO16, EIAJ, PLASTIC, SOIC-16
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