MC14553BDW_技术文档

The MC14553B 3–digit BCD counter consists of 3 negative edge

triggered BCD counters that are cascaded synchronously. A quad latch

at the output of each counter permits storage of any given count. The

information is then time division multiplexed, providing one BCD

number or digit at a time. Digit select outputs provide display control.

All outputs are TTL compatible.

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An on–chip oscillator provides the low–frequency scanning clock

which drives the multiplexer output selector.

This device is used in instrumentation counters, clock displays,

digital panel meters, and as a building block for general logic

applications.

MARKING

DIAGRAMS

16

PDIP–16

P SUFFIX

CASE 648

MC14553BCP

AWLYYWW

• TTL Compatible Outputs

• On–Chip Oscillator

• Cascadable

1

• Clock Disable Input

• Pulse Shaping Permits Very Slow Rise Times on Input Clock

• Output Latches

16

14553B

SOIC–16

DW SUFFIX

CASE 751G

• Master Reset

AWLYYWW

1

MAXIMUM RATINGS (Voltages Referenced to V ) (Note 1.)

SS

A

= Assembly Location

Symbol

Parameter

Value

Unit

V

WL or L = Wafer Lot

YY or Y = Year

V

DD

DC Supply Voltage Range

–0.5 to +18.0

WW or W = Work Week

V , V

in out

Input or Output Voltage Range

(DC or Transient)

–0.5 to V + 0.5

V

DD

I

Input Current

(DC or Transient) per Pin

±10

+20

500

mA

mW

in

ORDERING INFORMATION

I

Output Current

(DC or Transient) per Pin

out

Device

Package

PDIP–16

SOIC–16

Shipping

P

Power Dissipation,

MC14553BCP

MC14553BDW

25/Rail

47/Rail

D

per Package (Note 2.)

T

Ambient Temperature Range

Storage Temperature Range

–55 to +125

–65 to +150

260

°C

A

T

stg

T

Lead Temperature

L

(8–Second Soldering)

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high–impedancecircuit. For proper operation, V and V should be constrained

in

out

to the range V

(V or V

)

V

DD

.

SS

in

out

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V or V ). Unused outputs must be left open.

SS

DD

Semiconductor Components Industries, LLC, 2000

1

Publication Order Number:

March, 2000 – Rev. 3

MC14553B/D

MC14553B

BLOCK DIAGRAM

4

3

CIA CIB

9

7

6

Q0

Q1

Q2

CLOCK

12

10

LE

5

Q3

O.F.

DS1

DS2

DS3

14

2

11

13

DIS

MR

1

15

V

DD

= PIN 16

V

SS

= PIN 8

TRUTH TABLE

Inputs

Master

Reset

Clock

Disable

LE

Outputs

0

1

0

1

0

X

0

X

No Change

Advance

No Change

Advance

No Change

Latched

X

1

0

X

1

0

Latched

Q0 = Q1 = Q2 = Q3 = 0

X = Don’t Care

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2

MC14553B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

SS

– 55 C

25 C

125 C

V

Vdc

DD

(3.)

Characteristic

Output Voltage

Symbol

Unit

Min

Max

Min

Typ

Max

Min

Max

“0” Level

“1” Level

“0” Level

V

OL

5.0

10

15

—

0.05

—

0

0.05

—

0.05

Vdc

V

in

= V or 0

DD

V

OH

5.0

10

15

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

10

15

—

4.95

9.95

14.95

—

Vdc

V

in

= 0 or V

DD

Input Voltage

(V = 4.5 or 0.5 Vdc)

V

IL

5.0

10

15

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

O

(V = 9.0 or 1.0 Vdc)

O

(V = 13.5 or 1.5 Vdc)

O

“1” Level

V

IH

Vdc

(V = 0.5 or 4.5 Vdc)

5.0

10

15

3.5

7.0

11

—

3.5

7.0

11

2.75

5.50

8.25

—

3.5

7.0

11

—

O

(V = 1.0 or 9.0 Vdc)

O

(V = 1.5 or 13.5 Vdc)

O

Output Drive Current

I

mAdc

OH

(V = 4.6 Vdc)

Source —

Pin 3

5.0

10

15

– 0.25

– 0.62

– 1.8

—

– 0.2

– 0.5

– 1.5

– 0.36

– 0.9

– 3.5

—

0.14

0.35

1.1

—

OH

(V = 9.5 Vdc)

OH

(V = 13.5 Vdc)

OH

(V = 4.6 Vdc)

Source —

Other

Outputs

5.0

10

15

– 0.64

– 1.6

– 4.2

—

– 0.51

– 1.3

– 3.4

– 0.88

– 2.25

– 8.8

—

– 0.36

– 0.9

– 2.4

—

mAdc

OH

(V = 9.5 Vdc)

OH

(V = 13.5 Vdc)

OH

(V = 0.4 Vdc)

Sink —

Pin 3

I

OL

5.0

10

15

0.5

1.1

1.8

—

0.4

0.9

1.5

0.88

2.25

8.8

—

0.28

0.65

1.20

—

OL

(V = 0.5 Vdc)

OL

(V = 1.5 Vdc)

OL

(V = 0.4 Vdc) Sink — Other

5.0

10

15

3.0

6.0

18

—

2.5

5.0

15

4.0

8.0

20

—

1.6

3.5

10

—

OL

(V = 0.5 Vdc)

Outputs

OL

(V = 1.5 Vdc)

OL

Input Current

Input Capacitance

I

15

—

±0.1

—

±0.00001

±0.1

—

±1.0

µAdc

in

C

—

5.0

7.5

—

pF

in

(V = 0)

in

Quiescent Current

(Per Package)

I

5.0

10

15

—

5.0

10

20

—

0.010

0.020

0.030

5.0

10

20

—

150

300

600

µAdc

DD

MR = V

DD

(4.) (5.)

Total Supply Current

I

T

5.0

10

15

I = (0.35 µA/kHz) f + I

T

I = (0.85 µA/kHz) f + I

T

I = (1.50 µA/kHz) f + I

T

DD

(Dynamic plus Quiescent,

Per Package)

(C = 50 pF on all outputs, all

L

buffers switching)

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25 C.

5. To calculate total supply current at loads other than 50 pF:

I (C ) = I (50 pF) + (C – 50) Vfk

T

L

T

L

where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.004.

T

L

DD

SS

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3

MC14553B

SWITCHING CHARACTERISTICS ^(6.)(C = 50 pF, T = 25 C)

L

A

(7.)

Characteristic

Figure

Symbol

V

DD

Min

Typ

Max

Unit

Output Rise and Fall Time

2a

t

,

ns

TLH

t

, t

= (1.5 ns/pF) C + 25 ns

t

THL

5.0

10

15

—

100

50

40

200

100

80

TLH THL

L

, t

= (0.75 ns/pF) C + 12.5 ns

TLH THL

L

, t

= (0.55 ns/pF) C + 9.5 ns

L

TLH THL

Clock to BCD Out

Clock to Overflow

Reset to BCD Out

2a

2b

2a

2b

—

2a

2b

—

1

t

,

5.0

10

15

—

900

500

200

1800

1000

400

ns

PLH

PHL

t

5.0

10

15

—

600

400

200

1200

800

400

PHL

t

5.0

10

15

—

900

500

300

1800

1000

600

ns

PHL

Clock to Latch Enable Setup Time

Master Reset to Latch Enable Setup Time

t

su

5.0

10

15

600

400

200

300

200

100

—

ns

Removal Time

t

5.0

10

15

– 80

– 10

0

– 200

– 70

– 50

—

ns

rem

Latch Enable to Clock

Clock Pulse Width

t

5.0

10

15

550

200

150

275

100

75

—

ns

WH(cl)

WH(R)

Reset Pulse Width

5.0

10

15

1200

600

450

600

300

225

—

ns

Reset Removal Time

Input Clock Frequency

Input Clock Rise Time

t

5.0

10

15

– 80

0

20

– 180

– 50

– 30

—

ns

rem

f

cl

5.0

10

15

—

1.5

5.0

7.0

0.9

2.5

3.5

MHz

ns

t

5.0

10

15

No

Limit

TLH

Disable, MR, Latch Enable

Rise and Fall Times

t

,

5.0

10

15

—

15

5.0

4.0

µs

TLH

THL

Scan Oscillator Frequency

f

5.0

10

15

—

1.5/C1

4.2/C1

7.0/C1

—

Hz

osc

(C1 measured in µF)

6. The formulas given are for the typical characteristics only at 25 C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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4

MC14553B

UNITS CLOCK

UNITS Q0

UNITS Q1

UNITS Q2

UNITS Q3

TENS CLOCK

TENS Q0

TENS Q3

UP AT 980

UP AT 80

HUNDREDS

CLOCK

HUNDREDS Q0

HUNDREDS Q3

DISABLE

UP AT 800

(DISABLES CLOCK WHEN HIGH)

OVERFLOW

MASTER

RESET

SCAN

OSCILLATOR

DIGIT SELECT 1

DIGIT SELECT 2

UNITS

TENS

DIGIT SELECT 3

HUNDREDS

Figure 1. 3–Digit Counter Timing Diagram (Reference Figure 3)

16

V

DD

(a)

PULSE

GENERATOR

Q3

Q2

20 ns

t

WL(cl)

C

20 ns

90%

C

L

90%

10%

CLOCK

C

L

50%

Q1

LE

C

L

Q0

t

PLH

1/f

t

cl

C

L

O.F.

DS1

DS2

DS3

PHL

DIS

BCD OUT

C

L

t

50%

t

PHL

10%

t

TLH

THL

50%

OVERFLOW

MR

8

V

SS

t

TLH

90%

10%

CLOCK

50%

V

DD

(b)

GENERATOR

1

t

su

t

Q3

Q2

rem

C

L

LATCH

ENABLE

C

L

50%

, t

Q1

GENERATOR

2

LE

C

L

Q0

t

PHL PLH

t

su

C

L

O.F.

DS1

DS2

DS3

GENERATOR

3

MR

C

L

BCD OUT

50%

DIS

t

PHL

V

SS

50%

MASTER RESET

t

WH(R)

Figure 2. Switching Time Test Circuits and Waveforms

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5

MC14553B

OPERATING CHARACTERISTICS

The MC14553B three–digit counter, shown in Figure 3,

The Master Reset input, when taken high, initializes the

three BCD counters and the multiplexer scanning circuit.

While Master Reset is high the digit scanner is set to digit

one; but all three digit select outputs are disabled to prolong

display life, and the scan oscillator is inhibited. The Disable

input, when high, prevents the input clock from reaching the

counters, while still retaining the last count. A pulse shaping

circuit at the clock input permits the counters to continue

operating on input pulses with very slow rise times.

Information present in the counters when the latch input

goes high, will be stored in the latches and will be retained

while the latch input is high, independent of other inputs.

Information can be recovered from the latches after the

counters have been reset if Latch Enable remains high

during the entire reset cycle.

consists of three negative edge–triggered BCD counters

which are cascaded in a synchronous fashion. A quad latch

at the output of each of the three BCD counters permits

storage of any given count. The three sets of BCD outputs

(active high), after going through the latches, are time

division multiplexed, providing one BCD number or digit at

a time. Digit select outputs (active low) are provided for

display control. All outputs are TTL compatible.

An on–chip oscillator provides the low frequency

scanning clock which drives the multiplexer output selector.

The frequency of the oscillator can be controlled externally

by a capacitor between pins 3 and 4, or it can be overridden

and driven with an external clock at pin 4. Multiple devices

can be cascaded using the overflow output, which provides

one pulse for every 1000 counts.

C1

A

LATCH ENABLE

10

4

3

SCAN

OSCILLATOR

PULSE

GENERATOR

R

C1

B

CLOCK

12

R SCANNER

Q0

PULSE

SHAPER

C

R

Q1

Q2

Q3

QUAD

LATCH

÷10

UNITS

9

Q0

11

DISABLE

(ACTIVE

HIGH)

MULTIPLEXER

7

Q1

Q0

Q1

Q2

Q3

C

R

QUAD

LATCH

BCD

OUTPUTS

(ACTIVE

HIGH)

÷10

TENS

6

Q2

Q0

Q1

Q2

Q3

C

R

5

QUAD

LATCH

Q3

÷10

HUNDREDS

2

1

15

DS1 DS2 DS3

(LSD) DIGIT SELECT (MSD)

(ACTIVE LOW)

13

MR

(ACTIVE HIGH)

14

OVERFLOW

Figure 3. Expanded Block Diagram

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6

MC14553B

Figure 4. Six–Digit Display

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7

MC14553B

PACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

–A–

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

16

1

9

8

B

S

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

0.740 0.770 18.80 19.55

MILLIMETERS

MIN MAX

F

A

B

C

D

F

G

H

J

K

L

M

S

C

L

0.250 0.270

0.145 0.175

0.015 0.021

6.35

3.69

0.39

1.02

6.85

4.44

0.53

1.77

0.040

0.70

SEATING

PLANE

–T–

0.100 BSC

0.050 BSC

0.008 0.015

2.54 BSC

1.27 BSC

K

M

0.21

0.38

3.30

7.74

10

H

J

0.110

0.295 0.305

10

0.020 0.040

0.130

2.80

7.50

0

G

D 16 PL

0

0.51

1.01

M

0.25 (0.010)

T A

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8

MC14553B

PACKAGE DIMENSIONS

SOIC–16

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–03

ISSUE B

A

D

16

9

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS

OF THE B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

1

8

MILLIMETERS

B

16X B

DIM MIN

MAX

2.65

0.25

0.49

0.32

10.45

7.60

A

A1

B

C

D

E

2.35

0.10

0.35

0.23

10.15

7.40

M

S

0.25

T A

B

e

1.27 BSC

H

h

L

10.05

0.25

0.50

0

10.55

0.75

0.90

7

SEATING

PLANE

14X

e

C

T

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9

MC14553B

Notes

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10

MC14553B

Notes

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11

MC14553B

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

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attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

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Email: ONlit–french@hibbertco.com

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EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, England, Ireland

MC14553B/D

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12


型号：	MC14553BDW
厂家：	ONSEMI
描述：	3-Digit BCD Counter 3位BCD计数器计数器触发器逻辑集成电路光电二极管输出元件 CD
文件：	总12页 (文件大小：181K)
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MC14553BDW [ONSEMI]

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