MC14556BFR1 [ONSEMI]
4000/14000/40000 SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, EIAJ, SOP-16;
| 型号： | MC14556BFR1 |
| 厂家： | 
ONSEMI |
| 描述： | 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, EIAJ, SOP-16 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总6页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14555B, MC14556B
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary−to−hexadecimal (1−of−16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
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MARKING
DIAGRAMS
16
PDIP−16
MC1455xBCP
AWLYYWWG
P SUFFIX
CASE 648
1
1
Features
• Diode Protection on All Inputs
16
SOIC−16
D SUFFIX
CASE 751B
• Active High or Active Low Outputs
• Expandable
1455xBG
AWLYWW
1
1
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• These Devices are Pb−Free and are RoHS Compliant
16
SOEIAJ−16
F SUFFIX
CASE 966
MC1455xB
ALYWG
1
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
x
A
= 5 or 6
= Assembly Location
Parameter
Symbol
Value
Unit
V
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
= Pb−Free Package
DC Supply Voltage Range
V
DD
−0.5 to +18.0
Input or Output Voltage Range
(DC or Transient)
V , V
in out
−0.5 to V
V
DD
+ 0.5
G
Input or Output Current (DC or Transient)
per Pin
I , I
10
mA
in out
PIN ASSIGNMENTS
MC14555B MC14556B
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
P
D
500
mW
°C
T
A
−55 to +125
−65 to +150
260
E
1
2
3
4
5
6
7
8
16
15
14
13
V
E
1
2
3
4
5
6
7
8
16
15
14
13
V
A
A
A
A
A
A
A
DD
A
A
A
A
A
A
A
DD
Storage Temperature Range
T
stg
°C
A
B
E
B
A
E
B
Lead Temperature (8−Second Soldering)
T
L
°C
A
B
B
A
B
B
B
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Q0
Q1
Q2
Q3
V
Q0
Q1
Q2
Q3
V
B
B
12 Q0
11 Q1
10 Q2
12 Q0
11 Q1
10 Q2
B
B
B
B
B
B
B
B
Packages: – 7.0 mW/°C From 65°C To 125°C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
9
Q3
9
Q3
SS
SS
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 9
MC14555B/D
MC14555B, MC14556B
TRUTH TABLE
BLOCK DIAGRAM
MC14555B
Q0
MC14556B
Inputs
Outputs
MC14555B MC14556B
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
Enable Select
4
5
6
7
Q0
4
5
6
7
2
3
1
2
3
1
A
B
E
A
B
E
E
B
A
Q1
Q2
Q3
Q1
Q2
Q3
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
X
X
0
0
0
0
1
1
1
1
Q0
Q1
Q2
Q3
12
11
10
9
12
11
10
9
Q0
Q1
Q2
Q3
14
13
15
14
13
15
A
B
E
A
B
E
X = Don’t Care
V
= PIN 16
= PIN 8
DD
V
SS
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55°C
25°C
125°C
Typ
(Note 2)
V
Vdc
DD
Min
Max
Min
Max
Min
Max
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
V
= V or 0
in
DD
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
O
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
O
(V = 1.0 or 9.0 Vdc)
(V = 1.5 or 13.5 Vdc)
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
15
OH
(V = 0.4 Vdc)
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
I
15
−
−
0.1
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
mAdc
pF
in
Input Capacitance, (V = 0)
C
−
−
−
in
in
Quiescent Current (Per Package)
I
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
DD
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Package)
I
T
5.0
10
15
I = (0.85 mA/kHz) f + I
mAdc
T
DD
DD
DD
I = (1.70 mA/kHz) f + I
T
I = (2.60 mA/kHz) f + I
T
(C = 50 pF on all outputs, all
L
buffers switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25°C.
4. To calculate total supply current at loads other than 50 pF: I (C ) = I (50 pF) + (C – 50) Vfk where: I is in mA (per package), C in pF,
T
L
T
L
T
L
V = (V – V ) in volts, f in kHz is input frequency, and k = 0.002.
DD
SS
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2
MC14555B, MC14556B
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25°C)
L
A
Typ
(Note 6)
Characteristic
Output Rise and Fall Time
Symbol
V
Min
Max
Unit
DD
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
5.0
10
15
−
−
−
100
50
40
200
100
80
TLH THL
L
THL
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
TLH THL
L
Propagation Delay Time − A, B to Output
t
,
ns
ns
PLH
t
t
t
, t
= (1.7 ns/pF) C + 135 ns
t
5.0
10
15
−
−
−
220
95
440
190
140
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 62 ns
PLH PHL
L
, t
= (0.5 ns/pF) C + 45 ns
70
PLH PHL
L
Propagation Delay Time − E to Output
t
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 115 ns
t
5.0
10
15
−
−
−
200
85
65
400
170
130
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 52 ns
PLH PHL
L
, t
= (0.5 ns/pF) C + 40 ns
PLH PHL
L
5. The formulas given are for the typical characteristics only at 25°C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
INPUT E LOW
INPUT A HIGH, INPUT E LOW
20 ns
20 ns
20 ns
20 ns
V
DD
90%
50%
10%
V
DD
90%
50%
10%
INPUT B
V
V
A INPUTS
SS
1
V
V
(50% DUTY CYCLE)
SS
2f
DD
t
t
PLH
PHL
OH
90%
50%
10%
OUTPUT Q3
MC14556B
V
V
B INPUTS
SS
V
OL
V
OH
V
OL
(50% DUTY CYCLE)
t
t
THL
TLH
OH
t
t
PHL
PLH
90%
50%
10%
OUTPUT Q1
V
OL
OUTPUT Q3
MC14555B
All 8 outputs connect to respective C loads.
f in respect to a system clock.
L
t
t
TLH
THL
Figure 1. Dynamic Power Dissipation Signal Waveforms
Figure 2. Dynamic Signal Waveforms
LOGIC DIAGRAM
(1/2 of Dual)
*
Q0
A
B
*
Q1
*
Q2
E
*
Q3
*Eliminated for MC14555B
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3
MC14555B, MC14556B
ORDERING INFORMATION
†
Device
Package
Shipping
MC14555BCPG
PDIP−16
500 Units / Rail
48 Units / Rail
(Pb−Free)
MC14555BDG
SOIC−16
(Pb−Free)
MC14555BDR2G
MC14555BFELG
MC14556BCPG
MC14556BDR2G
MC14556BFELG
SOIC−16
(Pb−Free)
2500 / Tape & Reel
2000 / Tape & Reel
500 Units / Rail
SOEIAJ−16
(Pb−Free)
PDIP−16
(Pb−Free)
SOIC−16
(Pb−Free)
2500 / Tape & Reel
2000 / Tape & Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC14555B, MC14556B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
M
S
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
J
0.21
0.38
3.30
7.74
10
G
2.80
7.50
0
D 16 PL
M
M
0.25 (0.010)
T
A
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOEIAJ−16
CASE 966−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
E
16
9
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
Q
1
H
E
M
_
E
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
---
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
---
0.05
0.35
0.10
9.90
5.10
2.05
A
A
1
0.20 0.002
0.50 0.014
0.20 0.007
1
b
0.13 (0.005)
b
c
0.10 (0.004)
M
D
E
10.50 0.390
5.45 0.201
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
0
10
0.90 0.028
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
---
1
Z
0.78
---
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5
MC14555B, MC14556B
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC14555B/D
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