MC14581BDW [ONSEMI]
4-BIT ARITHMETIC LOGIC UNIT, PDSO24, PLASTIC, SOIC-24;
| 型号： | MC14581BDW |
| 厂家： | 
ONSEMI |
| 描述： | 4-BIT ARITHMETIC LOGIC UNIT, PDSO24, PLASTIC, SOIC-24 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC14581B is a CMOS 4–bit ALU capable of providing 16 functions of
two Boolean variables and 16 binary arithmetic operations on two 14–bit
words. The level of the mode control input determines whether the output
function is logic or arithmetic. The desired logic function is selected by
applying the appropriate binary word to the select inputs (S0 thru S3) with
the mode control input high, while the desired arithmetic operation is
selected by applying a low voltage to the mode control input, the required
level to carry in, and the appropriate word to the select inputs. The word
inputs and function outputs can be operated with either active high or active
low data.
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
Carry propagate (P) and carry generate (G) outputs are provided to allow
a full look–ahead carry scheme for fast simultaneous carry generation for the
four bits in the package. Fast arithmetic operations on long words are
obtainable by using the MC14582B as a second order look ahead block. An
ORDERING INFORMATION
inverted ripple carry input (C ) and a ripple carry output (C
for ripple through operation.
When the device is in the subtract mode (LHHL), comparison of two 4–bit
words present at the A and B inputs is provided using the A = B output. It
assumes a high–level state when indicating equality. Also, when the ALU is
) are included
n
n+4
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
T
A
= – 55° to 125°C for all packages.
in the subtract mode the C
magnitude as shown in this table:
output can be used to indicate relative
n+4
PIN ASSIGNMENT
Data
Level
C
C
Magnitude
n
n+4
H
H
L
L
B0
A0
S3
S2
S1
S0
1
2
3
4
5
6
24
23
22
21
20
19
V
DD
Active
High
H
A
B
A1
B1
A2
B2
A3
L
H
L
A < B
A > B
A
B
Active
Low
L
H
L
L
L
H
H
A
B
A < B
A > B
H
A
B
C
7
18
17
16
15
14
13
B3
G
n
•
•
•
•
•
Functional and Pinout Equivalent to 74181.
Diode Protection on All Inputs
All Outputs Buffered
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
MC
F0
F1
F2
8
9
C
P
n+4
10
11
12
A = B
F3
V
SS
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 18.0
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
DD
Vdc
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ #
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 1.2
– 0.64
– 1.6
– 4.2
—
—
—
—
– 1.0
– 0.51
– 1.3
– 3.4
– 1.7
– 0.88
– 2.25
– 8.8
—
—
—
—
– 0.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Capacitance
C
—
—
—
—
5.0
7.5
—
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
T
I
T
I
T
= (1.8 µA/kHz) f + I
= (3.7 µA/kHz) f + I
= (5.5 µA/kHz) f + I
µAdc
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
DD
– V ) in volts, f in kHz is input frequency, and k = 0.008.
SS
T
L
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautionsmust be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, V and V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
be left open.
should be constrained to the range V
≤ (V or V ) ≤ V
.
in out
SS
in
out
DD
or V ). Unused outputs must
SS
DD
MC14581B
MOTOROLA CMOS LOGIC DATA
2
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
Characteristic
Symbol
V
DD
Min
Typ #
Max
Unit
Output Rise and Fall Time
t
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
L
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
THL
, t
TLH THL
, t
TLH THL
L
Propagation Delay Time
Sum in to Sum Out
t
t
,
ns
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 620 ns
= (0.66 ns/pF) C + 217 ns
L
= (0.5 ns/pF) C + 155 ns
5.0
10
15
—
—
—
705
250
180
1410
500
360
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
L
Sum in to Sum Out (Logic Mode)
t
t
t
,
ns
ns
ns
ns
ns
ns
PLH
t
t
t
, t
= (1.7 ns/pF) C + 520 ns
t
5.0
10
15
—
—
—
605
215
180
1210
430
360
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 182 ns
L
PLH PHL
, t
PLH PHL
= (0.5 ns/pF) C + 155 ns
L
Sum in to A = B
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 870 ns
t
5.0
10
15
—
—
—
955
330
245
1910
660
490
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 297 ns
L
PLH PHL
, t
PLH PHL
= (0.5 ns/pF) C + 220 ns
L
Sum in to P or G
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 400 ns
t
5.0
10
15
—
—
—
485
180
130
970
360
260
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 147 ns
PLH PHL
L
, t
PLH PHL
= (0.5 ns/pF) C + 105 ns
L
Sum in to C
n+4
t
PLH
t
t
t
, t
= (1.7 ns/pF) C + 530 ns
5.0
10
15
—
—
—
615
220
160
1230
440
360
PLH PHL
, t
, t
PLH PHL
L
= (0.66 ns/pF) C + 187 ns
= (0.5 ns/pF) C + 135 ns
PLH PHL
L
L
Carry in to Sum Out
t
t
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 295 ns
5.0
10
15
—
—
—
380
145
105
760
290
210
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 112 ns
PLH PHL
L
, t
PLH PHL
= (0.5 ns/pF) C + 80 ns
L
Carry in to C
n+4
t
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 220 ns
t
PHL
5.0
10
15
—
—
—
305
120
85
610
240
170
PLH PHL
, t
, t
PLH PHL
L
= (0.66 ns/pF) C + 87 ns
= (0.5 ns/pF) C + 60 ns
L
PLH PHL
L
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
AC TEST SETUP REFERENCE TABLE
AC Paths
Outputs
DC Data Inputs
To V To V
Fig. 3
Waveform
Test
Mode
Inputs
SS DD
Sum to Sum
Remaining A’s
in out
A0
Any F
All B’s
All B’s
Add
#1
#1
#1
#2
#1
#1
#2
Delay Time
C
n
Sum to P
in
Delay Time
Remaining A’s
A0
B0
B0
P
Add
Add
Add
Add
Add
Sub
C
n
Sum to G
in
Delay Time
All A’s
C
n
G
Remaining B’s
Remaining B’s
All B’s
Sum to C
in n+4
Delay Time
All A’s
C
n
C
n+y
C
to Sum
out
n
C
C
Any F
All A’s
All A’s
n
n
Delay Time
C
to C
n+4
n
C
All B’s
n+4
Delay Time
Sum to A = B
in
Delay Time
All B’s
Remaining A’s
A0
A = B
Any F
C
n
Sum to Sum
in
out
Exclusive
OR
Delay Time
B
0
All A’s
M
#2
(Logic Mode)
MOTOROLA CMOS LOGIC DATA
MC14581B
3
V
= V
OH
V
= V
OH
out
out
V
V
DD
DD
S0 S1 S2 S3
S0 S1 S2 S3
F0
F1
F2
F3
F0
F1
A0
A1
A2
A3
B0
B1
B2
B3
V
V
A0
A1
A2
A3
B0
B1
B2
B3
DD
DD
I
I
OH
F2
OH
F3
A = B
A = B
C
C
n+4
n+4
G
P
G
P
HIGH FOR
ALL OUTPUTS
HIGH FOR
ALL OUTPUTS
EXCEPT C
C
MC
C
MC
n
n
EXCEPT C
EXTERNAL
POWER
EXTERNAL
POWER
n+4
n+4
V
V
SS
SS
SUPPLY
SUPPLY
Figure 1. Typical Source Current Test Circuit
Figure 2. Typical Sink Current Test Circuit
LOAD A
50 pF
20 ns
TP
out
V
DD
20 ns
V
DD
90%
TP
in
10%
0 V
TP
in
t
PHL
t
S0 S1 S2 S3
TLH
SEE AC TEST
SETUP
REFERENCE
TABLE FOR
CONNECTIONS
F0
LOAD A
LOAD A
LOAD A
LOAD A
A0
V
V
OH
PULSE
GENERATOR
F1
A1
A2
F2
#1
TP
out
10%
OL
A3
B0
F3
t
PLH
t
t
THL
B1
B2
B3
LOAD A
LOAD A
LOAD A
LOAD A
A = B
t
THL
90%
V
V
C
OH
n+4
#2
TP
G
C
10%
n
out
OL
P
MC
t
PHL
TLH
t
PLH
Figure 3. Switching Time Test Circuit and Waveforms
V
DD
LOAD A
50 pF
TP
out
S0 S1 S2 S3
LOAD A
LOAD A
LOAD A
LOAD A
F0
F1
F2
F3
A0
A1
A2
A3
B0
TP
in
20 ns
TP
PULSE
GENERATOR
20 ns
B1
B2
B3
LOAD A
LOAD A
LOAD A
LOAD A
A = B
V
DD
90%
50%
C
n+4
G
DUTY CYCLE = 50%
in
10%
0 V
C
n
P
VARIABLE
WIDTH
MC
Figure 4. Dynamic Power Dissipation Test Circuit and Waveform
MC14581B
MOTOROLA CMOS LOGIC DATA
4
BLOCK DIAGRAM
(ACTIVE LOW)
BLOCK DIAGRAM
(ACTIVE HIGH)
3
4
5
6
3
4
5
6
FUNCTION
SELECT
INPUTS
V
V
= PIN 24
= PIN 12
DD
SS
S0 S1 S2 S3
A0
S0 S1 S2 S3
A0
2
23
21
19
1
2
23
21
19
1
F0
9
F0
9
A1
A2
A3
B0
B1
B2
B3
A1
A2
A3
B0
B1
B2
B3
OUTPUT
FUNCTION
WORD A
WORD B
F1
F2
F3
10
11
13
F1
F2
F3
10
11
13
22
20
18
7
22
20
18
7
A = B
14 COMPARISON OUTPUT
16 RIPPLE CARRY OUTPUT
A = B
14
16
17
15
C
C
n+4
G
n+4
G
17
15
LOOK AHEAD
CARRY OUTPUTS
CARRY IN
MODE CONTROL
C
C
n
n
P
P
8
MC
8
MC
TRUTH TABLE
Function Select
Inputs/Outputs Active Low
Inputs/Outputs Active High
Logic
Function
(MC = H)
Arithmetic*
Function
Logic
Function
(MC = H)
Arithmetic*
Function
(MC = L, C = L)
(MC = L, C = H)
S3
S2
S1
S0
n
n
L
L
L
L
L
L
L
H
A
AB
A minus 1
AB minus 1
A
A + B
A
A + B
L
L
L
L
H
H
L
L
H
L
A + B
Logic “1”
A + B
B
AB minus 1
minus 1
AB
A + B
Logic “0”
AB
minus 1
L
H
H
H
H
L
A plus (A + B)
AB plus (A + B)
A minus B minus 1
A + B
A plus AB
L
L
H
L
B
(A + B) plus AB
A minus B minus 1
AB minus 1
A plus AB
L
H
H
L
A
B
A
B
L
H
L
A + B
AB
AB
H
H
H
H
H
H
H
H
A plus (A + B)
A plus B
A + B
L
L
H
L
A
B
A
B
A plus B
L
H
H
L
B
AB plus (A + B)
A + B
B
(A + B) plus AB
AB minus 1
A plus A
L
H
L
A + B
Logic “0”
AB
AB
H
H
H
H
A plus A
Logic “1”
A + B
A + B
A
L
H
L
AB plus A
AB plus A
A
(A + B) plus A
(A + B) plus A
A minus 1
H
H
AB
H
A
* Expressed as two’s complements. For arithmetic function with C in the opposite state, the resulting
n
function is as shown plus 1.
MOTOROLA CMOS LOGIC DATA
MC14581B
5
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
24
1
13
12
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
B
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
31.24
12.70
4.06
0.41
1.27
2.54 BSC
0.20
3.18
MAX
32.77
15.49
5.59
0.51
1.52
MIN
MAX
1.290
0.610
0.220
0.020
0.060
1.230
0.500
0.160
0.016
0.050
0.100 BSC
0.008
0.125
A
SEATING
PLANE
F
C
0.30
4.06
0.012
0.160
K
L
15.24 BSC
0.600 BSC
M
N
0
0.51
15
1.27
0
15
0.050
L
0.020
N
D
J
M
G
K
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
24
1
13
12
B
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
31.37
13.72
3.94
0.36
1.02
MAX
32.13
14.22
5.08
0.56
1.52
MIN
MAX
1.265
0.560
0.200
0.022
0.060
1.235
0.540
0.155
0.014
0.040
L
A
C
N
G
H
J
K
L
2.54 BSC
0.100 BSC
K
1.65
0.20
2.92
2.03
0.38
3.43
0.065
0.008
0.115
0.080
0.015
0.135
J
H
F
M
SEATING
PLANE
D
G
15.24 BSC
0.600 BSC
M
N
0
0.51
15
1.02
0
15
0.040
0.020
MC14581B
6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
24
13
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B– 12X P
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
A
B
DIM
A
B
C
D
MIN
15.25
7.40
2.35
0.35
0.41
MAX
15.54
7.60
2.65
0.49
0.90
MIN
MAX
0.612
0.299
0.104
0.019
0.035
0.601
0.292
0.093
0.014
0.016
F
R X 45
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32
0.29
8
0.009
0.005
0
0.013
0.011
8
C
K
–T–
SEATING
M
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
PLANE
22X G
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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are registered
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MC14581B/D
◊
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