MC14598BCPG [ONSEMI]
8−Bit Bus−Compatible Latches; 8位总线兼容锁存器
| 型号： | MC14598BCPG |
| 厂家： | 
ONSEMI |
| 描述： | 8−Bit Bus−Compatible Latches |
| 文件： | 总6页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14598B
8−Bit Bus−Compatible
Latches
The MC14598B is an 8−bit latch addressed with an external binary
address. The 8 latch−outputs are high drive, three−state and bus line
compatible. The drive capability allows direct applications with MPU
systems such as the Motorola 6800 family.
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The latches of the MC14598B are accessed via the Address pins,
A0, A1, and A2.
All 8 outputs from the latches are available in parallel when Enable
is in the low state. Data is entered into a selected latch from the Data
pin when the Strobe is high. Master reset is available on both parts.
PDIP−18
P SUFFIX
CASE 707
Features
1
• Serial Data Input
• Three−State Bus Compatible Parallel Outputs
• Three−State Control Pin (Enable) TTL Compatible Input
• Open Drain Full Flag (Multiple Latch Wire−O Ring)
• Master Reset
MARKING DIAGRAM
18
1
MC14598BCP
AWLYYWWG
• Level Shifting Inputs on All Except Enable
• Diode Protection — All Inputs
• Supply Voltage Range — 3.0 Vdc to 18 Vdc
• Capable of Driving TTL Over Rated Temperature Range With
A
= Assembly Location
Fanout as Follows: 1 TTL Load
WL = Wafer Lot
YY = Year
WW = Work Week
4 LSTTL Loads
• Pb−Free Package is Available*
G
= Pb−Free Package
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
OUTPUT TRUTH TABLE
Parameter
Symbol
Value
Unit
V
Enable
Outputs
DC Supply Voltage Range
V
−0.5 to +18.0
DD
1
0
High Impedance
Input Voltage Range, enable
(DC or Transient)
V
−0.5 to V
+0.5
V
in
DD
DD
DD
D
n
Input Voltage Range, all Other Inputs
(DC or Transient)
V
in
−0.5 to V
+12
V
V
D = State of nth latch
n
NC = NO CONNECTION
Output Voltage Range, (DC or Transient)
V
out
−0.5 to V
+0.5
ORDERING INFORMATION
Input or Output Current (DC or Transient)
per Pin
I , I
10
mA
in out
Device
Package
Shipping
20 Units/Rail
20 Units/Rail
Power Dissipation per Package (Note 1)
Ambient Temperature Range
P
500
mW
°C
MC14598BCP
MC14598BCPG
PDIP−18
D
T
A
−55 to +125
−65 to +150
260
PDIP−18
(Pb−Free)
Storage Temperature Range
T
stg
°C
Lead Temperature (8−Second Soldering)
T
°C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From
65_C To 125_C
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum
rated voltages to this high−impedance circuit. For
proper operation, V and V should be constrained
in
out
out
to the range V v (V or V ) v V
.
SS
in
DD
Unused inputs must always be tied to an
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
appropriate logic voltage level (e.g., either V
or
SS
V
). Unused outputs must be left open.
DD
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MC14598B/D
MC14598B
PIN ASSIGNMENT
BLOCK DIAGRAM
D0
RESET
DATA
ENABLE
NC
1
2
3
4
5
6
7
8
9
18
V
DD
ENABLE
4
17 D1
16 D2
15 D3
14 D4
13 D5
12 D6
11 D7
10 A2
RESET
DATA
2
3
6
1
D0
STROBE
17 D1
16 D2
15 D3
14 D4
13 D5
12 D6
11 D7
THREE
STATE
8
LATCHES
A0
A1
7
8
OUTPUT
BUFFERS
STROBE
A0
ADDRESS
DECODER
A2 10
A1
V
= 18
= 9
DD
V
SS
V
SS
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
125_C
V
Typ
DD
(Note 2)
Min
Max
Min
Max
Min
Max
Vdc
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
V
5.0
10
15
−
−
−
0.05
0.05
0.05
–
−
−
0
0
0
0.05
0.05
0.05
–
−
−
0.05
0.05
0.05
Vdc
OL
V
in
= V or 0
DD
V
5.0
10
15
4.95
9.95
14.95
–
−
−
4.95
9.95
14.95
5.0
10
15
–
−
−
4.95
9.95
14.95
–
−
−
Vdc
Vdc
OH
V
in
= 0 or V
DD
Input Voltage (Note 3), Enable “0” Level
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
0.8
1.6
2.4
−
−
−
1.1
2.2
3.4
0.8
1.6
2.4
–
−
−
0.8
1.6
2.4
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
“0” Level
V
Vdc
Vdc
IH
(V = 0.5 or 4.5 Vdc)
5.0
10
15
2.0
6.0
10
−
−
−
2.0
6.0
10
1.9
3.1
4.3
–
−
−
2.0
6.0
10
–
−
−
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Input Voltage
Other Inputs
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
–
−
−
2.25
4.50
6.75
1.5
3.0
4.0
–
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
(V = 0.5 or 4.5 Vdc)
“1” Level
Source
V
5.0
10
15
3.5
7.0
11
–
−
−
3.5
7.0
11
2.75
5.50
8.25
–
−
−
3.5
7.0
11
–
−
−
Vdc
O
IH
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
(Full — Sink Only)
I
mAdc
OH
(V
(V
(V
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
5.0
10
1 5
–1.0
−
−
–
−
−
–1.0
−
−
–2.0
–6.0
–12
–
−
−
–1.0
−
−
–
−
−
OH
OH
OH
(V = 0.4 Vdc)
Sink
I
5.0
10
15
1.6
−
−
−
−
−
1.6
−
−
3.2
6.0
12
–
−
−
1.6
−
−
–
−
−
mAdc
OL
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
3−State Leakage Current
Input Capacitance (V = 0)
I
15
15
−
−
−
−
0.1
0.1
−
−
−
−
0.00001
0.00001
5.0
0.1
0.1
7.5
−
−
−
1.0
3.0
−
mAdc
mAdc
pF
in
I
TL
C
in
in
Quiescent Current (Per Package)
I
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
–
−
−
150
300
600
mAdc
DD
Total Supply Current at an External Load
Capacitance of 130 pF (Note 3)
I
5.0
10
I
I
I
= (2.0 mA/kHz) f + I
= (4.0 mA/kHz) f + I
= (6.0 mA/kHz) f + I
mAdc
T
T
T
T
DD
DD
DD
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
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2
MC14598B
SWITCHING CHARACTERISTICS (Note 4) (T = 25_C, C = 130 pF + 1 TTL Load)
A
L
All Types
Typ
V
DD
(Note 5)
Min
Max
Vdc
Characteristic
Output Rise and Fall Time
Symbol
, t
Unit
t
ns
TLH THL
t
t
t
, t
= (0.5 ns/pF) C + 35 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
TLH THL
L
, t
= (0.2 ns/pF) C + 25 ns
TLH THL
L
, t
= (0.16 ns/pF) C + 20 ns
TLH THL
L
Propagation Delay Time
Enable to Output
t
, t
ns
PLH PHL
5.0
10
15
−
−
−
160
125
100
320
250
200
Strobe to Output
Reset to Output
5.0
10
15
−
−
−
200
100
80
400
200
160
5.0
10
15
−
−
−
175
90
70
350
180
140
Pulse Width
Enable
t
, t
ns
WH WL
5.0
10
15
320
240
160
160
120
80
−
−
−
Strobe
5.0
10
15
200
100
80
100
50
40
−
−
−
Increment
Reset
5.0
10
15
200
100
80
100
50
40
−
−
−
5.0
10
15
300
160
100
150
80
50
−
−
−
Setup Time
Data
t
ns
ns
ns
su
5.0
10
15
100
50
35
50
25
20
−
−
−
Address
5.0
10
15
200
100
70
100
50
35
−
−
−
Hold Time
Data
t
h
5.0
10
15
100
50
35
50
25
20
−
−
−
Address
5.0
10
15
100
50
35
50
25
20
−
−
−
Reset Removal Time
t
5.0
10
15
20
20
20
– 25
– 15
– 10
−
−
−
rem
4. The formulas given are for the typical characteristics only at 25_C.
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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3
MC14598B
MC14598B FUNCTION DIAGRAM
RESETꢀ2
DATAꢀ3
V
DD
1ꢀD0
TO OTHER
LATCHES
STROBEꢀ6
ENABLEꢀ4
V
SS
EACH LATCH
TO OTHER
LATCHES
ZERO
SELECT
17ꢀD1
16ꢀD2
15ꢀD3
14ꢀD4
13ꢀD5
12ꢀD6
11ꢀD7
A0ꢀ7
A1ꢀ8
ADDRESS
DECODER
ADDITIONAL 7 LATCHES
A2ꢀ10
(M.S.B)
MC14598B TIMING DIAGRAM
90%
10%
50%
t
t
PLH
THL
90%
10%
D7
t
50%
1
t
t
TLH
PLH
PHL
RESET
A0, A1, A2
DATA
20 ns
t
W
90%
10%
50%
t
su
t
h
t
su
t
h
90%
10%
90%
10%
50%
STROBE
ENABLE
20 ns
t
W
20 ns
*
t
W
*1.4 V with V = 5.0 V
DD
NOTES:
1. High−impedance output state (another device controls bus).
2. Output Load as for MC14597B.
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4
MC14598B
LATCH TRUTH TABLE
Address
TRUTH TABLE FOR MC14597B
Address
Other
Strobe
Reset
Latch
Latches
Increment
Enable
Reset
Counter
Full
0
1
1
1
0
*
Data
0
*
*
X
X
1
0
1
1
0
1
Count Up
−
No Change
Reset to Zero
No Change
−
X
0
X
X
Set to One
Set to One
*= No change in state of latch
X = Don’t care
If at
ADDRESS 7
To Zero on
Falling Edge
of STROBE
X
1
1
X = Don’t care
TEST LOAD, ALL OUTPUTS
+5.0 V
R = 2.5 k
L
D
n
130 pF
11.7 k
Circuit diagrams external to or containing Motorola
products are included as a means of illustration only.
Complete information sufficient for construction purposes
may not be fully illustrated. Although the information herein
has been carefully checked and is believed to be reliable.
Motorola assumes no responsibility for inaccuracies.
Information herein does not convey to the purchaser any
license under the patent rights of Motorola or others.
The information contained herein is for guidance only,
with no warranty of any type, expressed or implied.
Motorola reserves the right to make any changes to the
information and the product(s) to which the information
applies and to discontinue manufacture of the product(s) at
any time.
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5
MC14598B
PACKAGE DIMENSIONS
PDIP−18
CASE 707−02
ISSUE D
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
J
BE WITHIN 0.25 mm (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO SEATING
PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
18
10
9
B
L
1
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. CONTROLLING DIMENSION: INCH.
M
A
INCHES
DIM MIN MAX
MILLIMETERS
MIN
22.22
6.10
3.56
0.36
1.27
MAX
23.24
6.60
4.57
0.56
1.78
A
B
C
D
F
0.875
0.240
0.140
0.014
0.050
0.915
0.260
0.180
0.022
0.070
C
K
G
H
J
0.100 BSC
2.54 BSC
N
0.040
0.008
0.115
0.060
0.012
0.135
1.02
0.20
2.92
1.52
0.30
3.43
F
D
SEATING
PLANE
K
L
H
G
0.300 BSC
7.62 BSC
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.02
_
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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MC14598B/D
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