MC33074DTBR2 [ONSEMI]
High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers; 高压摆率，宽带宽，单电源运算放大器
| 型号： | MC33074DTBR2 |
| 厂家： | 
ONSEMI |
| 描述： | High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers |
| 文件： | 总20页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
http://onsemi.com
Quality bipolar fabrication with innovative design concepts are
employed for the MC33071/72/74, MC34071/72/74 series of
monolithic operational amplifiers. This series of operational
amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/µs slew rate
and fast setting time without the use of JFET device technology.
Although this series can be operated from split supplies, it is
particularly suited for single supply operation, since the common
8
1
8
SO–8
1
P SUFFIX
CASE 626
D SUFFIX
CASE 751
mode input voltage range includes ground potential (V ). With A
EE
PIN CONNECTIONS
Darlington input stage, this series exhibits high input resistance, low
input offset voltage and high gain. The all NPN output stage,
characterized by no deadband crossover distortion and large output
voltage swing, provides high capacitance drive capability, excellent
phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33071/72/74, MC34071/72/74 series of devices are
available in standard or prime performance (A Suffix) grades and are
specified over the commercial, industrial/vehicular or military
temperature ranges. The complete series of single, dual and quad
operational amplifiers are available in plastic DIP, SOIC and TSSOP
surface mount packages.
1
2
3
4
8
7
6
5
Offset Null
Inputs
NC
V
CC
Output
–
+
V
EE
Offset Null
(Single, Top View)
1
2
3
4
8
7
6
5
Output 1
Inputs 1
V
CC
Output 2
–
+
–
+
Inputs 2
V
EE
(Dual, Top View)
• Wide Bandwidth: 4.5 MHz
• High Slew Rate: 13 V/µs
• Fast Settling Time: 1.1 µs to 0.1%
• Wide Single Supply Operation: 3.0 V to 44 V
• Wide Input Common Mode Voltage Range: Includes Ground (V
• Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)
• Large Output Voltage Swing: –14.7 V to +14 V (with ±15 V
Supplies)
14
14
1
SO–14
1
P SUFFIX
CASE 646
D SUFFIX
CASE 751A
EE)
14
1
TSSOP–14
DTB SUFFIX
CASE 948G
• Large Capacitance Drive Capability: 0 pF to 10,000 pF
• Low Total Harmonic Distortion: 0.02%
• Excellent Phase Margin: 60°
PIN CONNECTIONS
• Excellent Gain Margin: 12 dB
• Output Short Circuit Protection
• ESD Diodes/Clamps Provide Input Protection for Dual and Quad
1
Output 1
Inputs 1
14
13
Output 4
Inputs 4
2
3
4
1
4
3
–
+
–
+
12
11
V
CC
V
EE
Inputs 3
Output 3
5
6
10
9
2
+
–
+
–
Inputs 2
Output 2
7
8
(Quad, Top View)
ORDERING INFORMATION
Seedetailedorderingandshippinginformationinthepackage
dimensions section on page 17 of this data sheet.
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
October, 1999 – Rev. 2
MC34071/D
MC34071,2,4,A MC33071,2,4,A
Representative Schematic Diagram
(Each Amplifier)
V
CC
Q3
Q8
Q4
Q6
Q5
Q7
Q1
Q17
Q2
R2
R1
C1
D2
Q18
Bias
R6
R7
Q11
Q9
Q10
Output
–
R8
Inputs
+
C2
D3
Q19
Q15
Q16
Q13
R4
Q14
Base
Current
Cancellation
Q12
D1
Current
Limit
R5
R3
V /Gnd
EE
Offset Null
(MC33071, MC34071 only)
MAXIMUM RATINGS
Rating
Supply Voltage (from V
Symbol
Value
+44
Unit
V
to V
)
V
S
EE
CC
Input Differential Voltage Range
Input Voltage Range
V
Note 1
Note 1
V
IDR
V
V
IR
Output Short Circuit Duration (Note 2)
Operating Junction Temperature
Storage Temperature Range
t
Indefinite
+150
sec
°C
°C
SC
T
J
T
–60 to +150
stg
NOTES: 1. Either or both input voltages should not exceed the magnitude of V
or V .
EE
CC
2. Power dissipation must be considered to ensure maximum junction temperature (T ) is not
J
exceeded (see Figure 1).
http://onsemi.com
2
MC34071,2,4,A MC33071,2,4,A
ELECTRICAL CHARACTERISTICS (V
CC
= +15 V, V = –15 V, R = connected to ground, unless otherwise noted. See Note 3 for
EE L
T
= T
to T
)
A
low
high
A Suffix
Typ
Non–Suffix
Typ
Characteristics
Symbol
Min
Max
Min
Max
Unit
Input Offset Voltage (R = 100 Ω, V
= 0 V, V = 0 V)
V
IO
mV
S
CM
O
—
—
—
—
—
—
V
CC
V
CC
V
CC
= +15 V, V
= +5.0 V, V
= +15 V, V
= –15 V, T = +25°C
0.5
0.5
—
3.0
3.0
5.0
1.0
1.5
—
5.0
5.0
7.0
EE
A
= 0 V, T = +25°C
A
EE
EE
= –15 V, T = T
to T
low high
A
Average Temperature Coefficient of Input Offset Voltage ∆V /∆T
IO
—
10
—
—
10
—
µV/°C
nA
R
= 10 Ω, V = 0 V, V = 0 V,
S
A
CM O
T
= T
to T
low
high
CM
Input Bias Current (V
= 0 V, V = 0 V)
I
IB
O
T
T
= +25°C
—
—
100
—
500
700
—
—
100
—
500
700
A
A
= T
to T
low
high
Input Offset Current (V
= 0 V, V = 0V)
I
nA
CM
O
IO
T
= +25°C
—
—
6.0
—
50
300
—
—
6.0
—
75
300
A
T
= T
to T
A
low
Input Common Mode Voltage Range
= +25°C
high
V
ICR
V
V
V
to (V
CC
to (V
CC
–1.8)
–2.2)
V
V
to (V
to (V
–1.8)
–2.2)
T
EE
EE
EE
EE
CC
CC
A
T
= T
to T
A
low
high
Large Signal Voltage Gain (V = ±10 V, R = 2.0 kΩ)
A
VOL
V/mV
V
O
L
T
T
A
= +25°C
50
25
100
—
—
—
25
20
100
—
—
—
A
= T
to T
low
high
Output Voltage Swing (V = ±1.0 V)
V
OH
ID
= 0 V, R = 2.0 kΩ, T = +25°C
V
V
V
= +5.0 V, V
= +15 V, V
= +15 V, V
3.7
13.6
13.4
4.0
14
—
—
—
—
3.7
13.6
13.4
4.0
14
—
—
—
—
CC
CC
CC
EE
EE
EE
L
A
= –15 V, R = 10 kΩ, T = +25°C
L
L
A
= –15 V, R = 2.0 kΩ,
T
= T
to T
A
low
high
V
V
V
= +5.0 V, V
= +15 V V
,
= +15 V, V
= 0 V, R = 2.0 kΩ, T = +25°C
V
OL
0.1
–14.7
—
0.3
–14.3
–13.5
—
—
—
0.1
–14.7
—
0.3
–14.3
–13.5
V
CC
CC
CC
EE
EE
EE
L
A
—
—
—
= –15 V, R = 10 kΩ, T = +25°C
L
A
= –15 V, R = 2.0 kΩ,
L
T
= T
to T
high
A
low
Output Short Circuit Current (V = 1.0 V, V = 0 V,
I
mA
ID
O
SC
T
A
= 25°C)
Source
Sink
10
20
30
30
—
—
10
20
30
30
—
—
Common Mode Rejection
≤ 10 kΩ, V = V
CMR
PSR
80
97
—
70
97
—
dB
dB
R
, T = 25°C
A
S
CM
ICR
Power Supply Rejection (R = 100 Ω)
80
97
—
70
97
—
S
V
/V
= +16.5 V/–16.5 V to +13.5 V/–13.5 V,
= 25°C
CC EE
T
A
Power Supply Current (Per Amplifier, No Load)
I
mA
D
V
V
V
= +5.0 V, V
= +15 V, V
= +15 V, V
= 0 V, V = +2.5 V, T = +25°C
—
—
—
1.6
1.9
—
2.0
2.5
2.8
—
—
—
1.6
1.9
—
2.0
2.5
2.8
CC
CC
CC
EE
EE
EE
O
A
= –15 V, V = 0 V, T = +25°C
O A
= –15 V, V = 0 V,
O
T
= T
to T
A
low
=
high
NOTES: 3. T
–40°C for MC33071, 2, 4, /A
0°C for MC34071, 2, 4, /A
T
= +85°C for MC33071, 2, 4, /A
= +70°C for MC34071, 2, 4, /A
low
high
=
http://onsemi.com
3
MC34071,2,4,A MC33071,2,4,A
AC ELECTRICAL CHARACTERISTICS (V
= +15 V, V = –15 V, R = connected to ground. T = +25°C, unless otherwise noted.)
EE L A
CC
A Suffix
Typ
Non–Suffix
Typ
Characteristics
Symbol
Min
Max
Min
Max
Unit
Slew Rate (V = –10 V to +10 V, R = 2.0 kΩ, C = 500 pF)
SR
V/µs
in
L
L
A
= +1.0
= –1.0
8.0
—
10
13
—
—
8.0
—
10
13
—
—
V
A
V
Setting Time (10 V Step, A = –1.0)
V
To 0.1% (+1/2 LSB of 9–Bits)
To 0.01% (+1/2 LSB of 12–Bits)
t
s
µs
—
—
1.1
2.2
—
—
—
—
1.1
2.2
—
—
Gain Bandwidth Product (f = 100 kHz)
Power Bandwidth
GBW
BW
3.5
—
4.5
—
—
3.5
—
4.5
—
—
MHz
kHz
160
160
A
V
= +1.0, R = 2.0 kΩ, V = 20 V , THD = 5.0%
L
O
pp
Phase margin
f
Deg
dB
m
R
R
= 2.0 kΩ
= 2.0 kΩ, C = 300 pF
—
—
60
40
—
—
—
—
60
40
—
—
L
L
L
Gain Margin
A
m
R
R
= 2.0 kΩ
= 2.0 kΩ, C = 300 pF
—
—
12
4.0
—
—
—
—
12
4.0
—
—
L
L
L
Equivalent Input Noise Voltage
= 100 Ω, f = 1.0 kHz
e
i
—
—
—
—
—
32
—
—
—
—
—
—
—
—
—
—
32
—
—
—
—
—
nV/√Hz
n
R
S
Equivalent Input Noise Current
f = 1.0 kHz
0.22
150
2.5
0.22
150
2.5
pA/√Hz
MΩ
n
Differential Input Resistance
R
C
in
in
V
= 0 V
CM
Differential Input Capacitance
= 0 V
pF
%
V
CM
Total Harmonic Distortion
= +10, R = 2.0 kΩ, 2.0 V ≤ V ≤ 20 V , f = 10 kHz
THD
0.02
0.02
A
V
L
pp pp
O
Channel Separation (f = 10 kHz)
Open Loop Output Impedance (f = 1.0 MHz)
—
—
—
120
30
—
—
—
—
120
30
—
—
dB
W
|Z
|
O
Figure 1. Power Supply Configurations
Figure 2. Offset Null Circuit
V
CC
Single Supply
Split Supplies
3.0 V to 44 V
V
+|V |≤44 V
CC EE
7
2
3
–
V
CC
V
CC
6
5
+
1
2
V
CC
1
2
1
4
10 k
3
4
3
4
V
EE
V
EE
Offset nulling range is approximately ±80 mV with a 10 k
potentiometer (MC33071, MC34071 only).
V
EE
V
EE
http://onsemi.com
4
MC34071,2,4,A MC33071,2,4,A
Figure 3. Maximum Power Dissipation versus
Temperature for Package Types
Figure 4. Input Offset Voltage versus
Temperature for Representative Units
2400
2000
1600
1200
800
400
0
V
= +15 V
= –15 V
= 0
4.0
2.0
CC
V
EE
V
CM
8 & 14 Pin Plastic Pkg
SO–14 Pkg
0
–2.0
–4.0
SO–8 Pkg
–55 –40 –20
0
20 40 60 80 100 120 140 160
–55
–25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 5. Input Common Mode Voltage
Range versus Temperature
Figure 6. Normalized Input Bias Current
versus Temperature
1.3
V
CC
V = +15 V
CC
V
CC
V
/V = +1.5 V/ –1.5 V to +22 V/ –22 V
CC EE
1.2
1.1
1.0
0.9
V
= –15 V
EE
V
–0.8
–1.6
–2.4
CC
V
= 0
CM
V
CC
V
CC
V
EE
+0.01
0.8
0.7
V
EE
V
EE
–55
–55
–25
0
25
50
75
100
125
–25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 7. Normalized Input Bias Current versus
Input Common Mode Voltage
Figure 8. Split Supply Output Voltage
Swing versus Supply Voltage
50
40
30
20
10
0
1.4
1.2
R Connected
L
V
= +15 V
= –15 V
CC
to Ground T = 25°C
A
V
EE
T = 25°C
A
R = 10 k
L
R = 2.0 k
L
1.0
0.8
0.6
–12
–8.0
–4.0
0
4.0
8.0
12
0
5.0
10
V , |V |, SUPPLY VOLTAGE (V)
CC EE
15
20
25
V , INPUT COMMON MODE VOLTAGE (V)
IC
http://onsemi.com
5
MC34071,2,4,A MC33071,2,4,A
Figure 9. Single Supply Output Saturation
versus Load Resistance to V
Figure 10. Split Supply Output Saturation
versus Load Current
CC
V
V
CC
CC
V
CC
V
/V = +5.0 V/ –5.0 V to +22 V/ –22 V
CC EE
V
CC
T = 25°C
A
V
–1.0
–2.0
CC
V
–2.0
CC
V
= +15 V
CC
Source
R = Gnd
L
V
T = 25°C
V
–4.0
CC
CC
A
V
+2.0
+1.0
0.2
0.1
0
EE
V
EE
Sink
5.0
V
Gnd
EE
V
EE
0
10
LOAD CURRENT (±mA)
15
20
100
1.0 k
10 k
100 k
I
L,
R , LOAD RESISTANCE TO GROUND (Ω)
L
Figure 11. Single Supply Output Saturation
versus Load Resistance to Ground
Figure 12. Output Short Circuit Current
versus Temperature
0
60
50
40
30
20
V
CC
–0.4
–0.8
Sink
Source
2.0
1.0
V
= +15 V
CC
CC
R to V
L
V
= +15 V
= –15 V
CC
T = 25°C
A
V
EE
10
0
R ≤ 0.1 Ω
L
Gnd
∆V = 1.0 V
in
100
1.0 k
10 k
CC
100 k
–55
–25
0
25
50
75
100
125
R , LOAD RESISTANCE TO V (Ω)
T , AMBIENT TEMPERATURE (°C)
A
L
Figure 13. Output Impedance
versus Frequency
Figure 14. Output Voltage Swing
versus Frequency
50
40
30
20
28
24
V
= +15 V
= –15 V
= 0
CC
V
= +15 V
= –15 V
CC
V
EE
V
EE
V
CM
A = +1.0
V
V = 0
O
20
16
12
R = 2.0 k
L
∆I = ±0.5 mA
O
THD ≤ 1.0%
T = 25°C
A
T = 25°C
A
A = 1000
V
A = 100
V
A = 10
V
A = 1.0
V
8.0
4.0
10
0
0
3.0 k
1.0 k
10 k
100
f, FREQUENCY (Hz)
1.0 M
10 M
10 k
30 k
100 k
300 k
1.0 M 3.0 M
f, FREQUENCY (Hz)
http://onsemi.com
6
MC34071,2,4,A MC33071,2,4,A
Figure 15. Total Harmonic Distortion
versus Frequency
Figure 16. Total Harmonic Distortion
versus Output Voltage Swing
4.0
3.0
0.4
0.3
V
= +15 V
= –15 V
CC
A = 1000
V
V
EE
R = 2.0 k
L
A = 1000
V
T = 25°C
A
V
= +15 V
= –15 V
CC
V
EE
V = 2.0 V
2.0
1.0
0
O
pp
0.2
0.1
0
R = 2.0 k
L
T = 25°C
A
A = 100
V
A = 100
V
A = 10
V
A = 10
V
A = 1.0
V
A = 1.0
V
10
100
1.0 k
10 k
100 k
0
4.0
8.0
12
16
20
f, FREQUENCY (Hz)
V , OUTPUT VOLTAGE SWING (V )
O pp
Figure 17. Open Loop Voltage Gain
versus Temperature
Figure 18. Open Loop Voltage Gain and
Phase versus Frequency
100
116
112
108
104
100
96
0
V
= +15 V
= –15 V
CC
80
60
40
20
0
V
Gain
EE
45
90
135
180
Phase
V = –10 V to +10 V
O
R = 10 k
L
f ≤ 10Hz
Phase
Margin
= 60°
V
= +15 V
= –15 V
CC
V
EE
V = 0 V
O
R = 2.0 k
L
T = 25°C
A
–55
–25
0
25
50
75
100
125
1.0
10
100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
f, FREQUENCY (Hz)
T , AMBIENT TEMPERATURE (°C)
A
Figure 19. Open Loop Voltage Gain and
Phase versus Frequency
Figure 20. Normalized Gain Bandwidth
Product versus Temperature
20
10
1.15
1.1
1
100
120
140
160
180
Phase
Margin = 60°
V
= +15 V
= –15 V
CC
V
EE
Gain
Margin = 12 dB
R = 2.0 k
L
0
1.05
–10
–20
–30
–40
1.0
1. Phase R = 2.0 k
2. Phase R = 2.0 k, C = 300 pF
3. Gain R = 2.0 k
4. Gain R = 2.0 k, C = 300 pF
L
L
L
L
3
0.95
L
L
4
V
= +15 V
CC
0.9
V
= 15 V
2
EE
V = 0 V
T = 25°C
A
O
0.85
1.0
2.0
3.0 5.0
7.0 10
20
30
–55
–25
0
25
50
75
100
125
f, FREQUENCY (MHz)
T , AMBIENT TEMPERATURE (°C)
A
http://onsemi.com
7
MC34071,2,4,A MC33071,2,4,A
Figure 21. Percent Overshoot versus
Load Capacitance
Figure 22. Phase Margin versus
Load Capacitance
70
60
100
80
V
= +15 V
= –15 V
V
= +15 V
= –15 V
CC
CC
V
V
EE
EE
R = 2.0 k
A = +1.0
L
V
50
40
30
20
10
0
V = –10 V to +10 V
R = 2.0 k to
L
O
T = 25°C
V = –10 V to +10 V
O
60
A
T = 25°C
A
40
20
0
10
100
1.0 k
10 k
10
100
1.0 k
10 k
C , LOAD CAPACITANCE (pF)
L
C , LOAD CAPACITANCE (pF)
L
Figure 23. Gain Margin versus Load Capacitance
Figure 24. Phase Margin versus Temperature
14
12
80
60
40
20
0
V
= +15 V
= –15 V
CC
C = 10 pF
L
V
EE
C = 100 pF
L
A = +1.0
V
10
8.0
6.0
4.0
2.0
0
R = 2.0 k to ∞
L
V = –10 V to +10 V
O
V
= +15 V
= –15 V
T = 25°C
CC
A
V
EE
A = +1.0
V
R = 2.0 k to ∞
L
V = –10 V to +10 V
O
C = 1,000 pF
L
C = 10,000 pF
L
10
100
1.0 k
10 k
–55
–25
0
25
50
75
100
125
C , LOAD CAPACITANCE (pF)
L
T , AMBIENT TEMPERATURE (°C)
A
Figure 26. Phase Margin and Gain Margin
versus Differential Source Resistance
Figure 25. Gain Margin versus Temperature
70
16
12
8.0
4.0
0
12
V
= +15 V
= –15 V
CC
10
8.0
6.0
4.0
2.0
0
60
50
40
30
20
10
Gain
C = 10 pF
L
V
EE
R
1
A = +1.0
V
V
–
O
R = 2.0 k to ∞
L
+
V = –10 V to +10 V
O
C = 100 pF
L
R
2
V
V
T
V
O
A
= +15 V
= –15 V
R = R + R
CC
EE
C = 10,000 pF
L
C = 1,000 pF
L
1
2
Phase
A = +100
V = 0 V
T = 25°C
0
–55
–25
0
25
50
75
100
125
1.0
10
100
1.0 k
10 k
100 k
T , AMBIENT TEMPERATURE (°C)
A
R , DIFFERENTIAL SOURCE RESISTANCE (Ω)
T
http://onsemi.com
8
MC34071,2,4,A MC33071,2,4,A
Figure 27. Normalized Slew Rate
versus Temperature
Figure 28. Output Settling Time
10
5.0
0
1.15
1.1
V
= +15 V
= –15 V
V
= +15 V
= –15 V
CC
CC
1.0 mV
V
V
EE
EE
10 mV
1.0 mV
A = +1.0
A = –1.0
V
V
R = 2.0 k
L
T = 25°C
A
1.05
1.0
C = 500 pF
L
Compensated
Uncompensated
0.95
1.0 mV
–5.0
10 mV
0.5
0.9
1.0 mV
0.85
–10
–55
–25
0
25
50
75
100
125
0
1.0
1.5
2.0
2.5
3.0
3.5
T , AMBIENT TEMPERATURE (°C)
A
t , SETTLING TIME (µs)
s
Figure 29. Small Signal Transient Response
Figure 30. Large Signal Transient Reponse
V
= +15 V
= –15 V
CC
V
EE
A = +1.0
V
R = 2.0 k
L
C = 300 pF
L
T = 25°C
A
0
0
V
= +15 V
= –15 V
CC
V
EE
A = +1.0
V
R = 2.0 k
L
C = 300 pF
L
T = 25°C
A
2.0 µs/DIV
1.0 µs/DIV
Figure 31. Common Mode Rejection
versus Frequency
Figure 32. Power Supply Rejection
versus Frequency
100
80
100
80
T = 125°C
V
= +15 V
= –15 V
A
V
= +15 V
= –15 V
= 0 V
CC
CC
V
V
EE
T = 25°C
T = 25°C
EE
A
V
A
CM
∆V = ±1.5 V
∆V
CC
T = –55°C
A
CM
(∆V = +1.5 V)
–
CC
60
40
20
0
60
A
DM
∆V
O
+
∆V
EE
+PSR
–
40
20
0
∆V /A
O
DM
A
∆V
DM
∆V
O
+PSR = 20 Log
CM
+
∆V
CC
∆V
CM
∆V /A
O
DM
–PSR
(∆V = +1.5 V)
CMR = 20 Log
x A
DM
–PSR = 20 Log
1.0
∆V
∆V
O
EE
EE
0.1
1.0
10
100
1.0 k 10 k 100 k 1.0 M 10 M
0.1
10
100
1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
http://onsemi.com
9
MC34071,2,4,A MC33071,2,4,A
Figure 33. Supply Current versus
Supply Voltage
Figure 34. Power Supply Rejection
versus Temperature
105
95
85
75
65
9.0
8.0
7.0
6.0
–PSR (∆V = +1.5 V)
EE
V
V
EE
= +15 V
= –15 V
CC
T = –55°C
A
(∆V = +1.5 V)
+PSR
CC
T = 25°C
A
∆V
CC
∆V /A
O
DM
T = 125°C
A
–
+PSR = 20 Log
–PSR = 20 Log
∆V
A
CC
DM
∆V
O
+
5.0
4.0
∆V /A
O
DM
∆V
EE
∆V
EE
0
5.0
10
15
20
25
–55
–25
0
25
50
75
100
125
V
, |V |, SUPPLY VOLTAGE (V)
T , AMBIENT TEMPERATURE (°C)
A
CC EE
Figure 35. Channel Separation versus Frequency
Figure 36. Input Noise versus Frequency
2.8
120
100
80
60
40
20
0
70
V
= +15 V
= –15 V
= 0
CC
60
50
40
30
20
10
0
2.4
2.0
1.6
1.2
0.8
0.4
V
= +15 V
= –15 V
V
CC
EE
V
V
EE
CM
T = 25°C
T = 25°C
A
A
Voltage
Current
0
10
20
30
50
70
100
200
300
10
100
1.0 k
f, FREQUENCY (kHz)
10 k
100 k
f, FREQUENCY (kHz)
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Althoughthebandwidth, slewrate, andsettlingtimeofthe
MC34071 amplifier series are similar to op amp products
utilizing JFET input devices, these amplifiers offer other
additional distinct advantages as a result of the PNP
transistor differential input stage and an all NPN transistor
output stage.
up to approximately 5.0 mA of current from V through
EE
either inputs clamping diode without damage or latching,
although phase reversal may again occur.
If one or both inputs exceed the upper common mode
voltage limit, the amplifier output is readily predictable and
may be in a low or high state depending on the existing input
bias conditions.
Since the input common mode voltage range of this input
stage includes the V potential, single supply operation is
feasible to as low as 3.0 V with the common mode input
voltage at ground potential.
The input stage also allows differential input voltages up
to ±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
Since the input capacitance associated with the small
geometry input device is substantially lower (2.5 pF) than
the typical JFET input gate capacitance (5.0 pF), better
frequency response for a given input source resistance can
be achieved using the MC34071 series of amplifiers. This
performance feature becomes evident, for example, in fast
settling D–to–A current to voltage conversion applications
where the feedback resistance can form an input pole with
the input capacitance of the op amp. This input pole creates
a 2nd order system with the single pole op amp and is
therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
EE
between V
and V
supply voltages as shown by the
EE
maximum rating table. In practice, although not
recommended, the input voltages can exceed the V
CC
CC
voltagebyapproximately3.0VanddecreasebelowtheV
EE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
http://onsemi.com
10
MC34071,2,4,A MC33071,2,4,A
values of feedback resistances (lower current DACs). This
minimum current sink capability, typically to an output
input pole can be compensated for by creating a feedback
zero with a capacitance across the feedback resistance, if
necessary, to reduce overshoot. For 2.0 kΩ of feedback
resistance, the MC34071 series can settle to within 1/2 LSB
of 8 bits in 1.0 µs, and within 1/2 LSB of 12–bits in 2.2 µs
for a 10 V step. In a inverting unity gain fast settling
configuration, the symmetrical slew rate is ±13 V/µs. In the
classic noninverting unity gain configuration, the output
positive slew rate is +10 V/µs, and the corresponding
negative slew rate will exceed the positive slew rate as a
function of the fall time of the input waveform.
Since the bipolar input device matching characteristics
are superior to that of JFETs, a low untrimmed maximum
offset voltage of 3.0 mV prime and 5.0 mV downgrade can
be economically offered with high frequency performance
characteristics. This combination is ideal for low cost
precision, high speed quad op amp applications.
voltage of (V +1.8 V). In single supply applications the
EE
output can directly source or sink base current from a
common emitter NPN transistor for fast high current
switching applications.
In addition, the all NPN transistor output stage is
inherently fast, contributing to the bipolar amplifier’s high
gain bandwidth product and fast settling capability. The
associated high frequency low output impedance (30 Ω typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
10,000 pF without oscillation in the unity closed loop gain
configuration. The 60° phase margin and 12 dB gain margin
as well as the general gain and phase characteristics are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The
high frequency characteristics of the MC34071 series also
allow excellent high frequency active filter capability,
especially for low voltage single supply applications.
Although the single supply specifications is defined at
5.0 V, these amplifiers are functional to 3.0 V @ 25°C
although slight changes in parametrics such as bandwidth,
slew rate, and DC gain may occur.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB
output stage. A 10 kΩ load resistance can swing within 1.0
V of the positive rail (V ), andwithin0.3Vofthenegative
CC
rail(V ),providinga28.7V swingfrom±15Vsupplies.
If power to this integrated circuit is applied in reverse
polarity or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
EE pp
This large output swing becomes most noticeable at lower
supply voltages.
The positive swing is limited by the saturation voltage of
thecurrentsourcetransistorQ , andV oftheNPNpullup
Special static precautions are not necessary for these
bipolar amplifiers since there are no MOS transistors on
the die.
7
BE
transistorQ ,andthevoltagedropassociatedwiththeshort
17
circuit resistance, R . The negative swing is limited by the
7
saturation voltage of the pull–down transistor Q , the
As with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should
be exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input–output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediatelyadjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous “pick up” at this node. Supply decoupling with
adequatecapacitanceimmediatelyadjacenttothesupplypin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However, under
such conditions, it is important not to allow the device to
exceed the maximum junction temperature rating. Typically
for ±15 V supplies, any one output can be shorted
continuously to ground without exceeding the maximum
temperature rating.
16
voltage drop I R , and the voltage drop associated with
L 6
resistance R , where I is the sink load current. For small
7
L
valued sink currents, the above voltage drops are negligible,
allowing the negative swing voltage to approach within
millivolts of V . For large valued sink currents (>5.0 mA),
EE
diode D3 clamps the voltage across R , thus limiting the
6
negative swing to the saturation voltage of Q , plus the
16
forward diode drop of D3 (≈V +1.0 V). Thus for a given
EE
supplyvoltage, unprecedentedpeak–to–peakoutputvoltage
swing is possible as indicated by the output swing
specifications.
If the load resistance is referenced to V
instead of
CC
ground for single supply applications, the maximum
possible output swing can be achieved for a given supply
voltage. For light load currents, the load resistance will pull
the output to V
during the positive swing and the output
CC
will pull the load resistance near ground during the negative
swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull up
capability.
Because the PNP output emitter–follower transistor has
been eliminated, the MC34071 series offers a 20 mA
http://onsemi.com
11
MC34071,2,4,A MC33071,2,4,A
(Typical Single Supply Applications V
CC
= 5.0 V)
Figure 37. AC Coupled Noninverting Amplifer
Figure 38. AC Coupled Inverting Amplifier
V
CC
5.1 M
V
O
3.7 V
pp
0
3.7 V
pp
0
V
CC
100 k
1.0 M
20 k
C
in
C
O
68 k
+
V
O
+
MC34071
C
in
MC34071
–
10 k
V
O
36.6 mV
pp
–
C
O
10 k
100 k
V
in
10 k
R
L
100 k
R
L
V 370 mV
in pp
1.0 k
A = 101
V
A = 10 BW (–3.0 dB) = 450 kHz
V
BW (–3.0 dB) = 45 kHz
Figure 39. DC Coupled Inverting Amplifer
Maximum Output Swing
Figure 40. Unity Gain Buffer TTL Driver
2.5 V
V
O
V
4.75 V
pp
0
0 to 10,000 pF
Cable
CC
2.63 V
+
V
in
MC54/74XX
MC34071
91 k
–
TTL Gate
5.1 k
R
L
5.1 k
100 k
+
MC34071
V
O
–
Figure 42. Active Bandpass Filter
1.0 M
A = 10
V
V
in
BW (–3.0 dB) = 450 kHz
C
0.047
R3
2.2 k
R1
–
V
in
MC34071
1.1 k
R2
5.6 k
Figure 41. Active High–Q Notch Filter
V
O
C
0.047
+
V
CC
f = 30 kHz
o
H = 10
H = 1.0
o
o
V ≥ 0.2 Vdc
in
0.4 V
R2 =
CC
V
–
O
MC34071
Given f = Center Frequency
o
R
R
+
A = Gain at Center Frequency
O
V
in
16 k
16 k
Choose Value f , Q, A , C
o
o
C
Then:
Q
R3
R1 R3
2
0.01
R3 =
R1 =
πf C
o
2H
4Q R1–R3
o
f = 1.0 kHz
o
Q f
o o
2.0 R
32 k
< 0.1
For less than 10% error from operational amplifier
GBW
1
f =
o
4πRC
where f and GBW are expressed in Hz.
o
GBW = 4.5 MHz Typ.
2.0 C
0.02
2.0 C
0.02
http://onsemi.com
12
MC34071,2,4,A MC33071,2,4,A
Figure 43. Low Voltage Fast D/A Converter
Figure 44. High Speed Low Voltage Comparator
C
F
V
in
2.0 V
R
F
V
in
+
V
O
5.0 k
5.0 k
5.0 k
t
MC34071
–
–
V
O
MC34071
2.0 k
R
L
V
O
+
10 k
10 k
10 k
V
CC
0.2 µs
1.0 V
4.0 V
Delay
Bit
Switches
13 V/µs
25 V/µs
(R–2R) Ladder Network
0.1
t
Settling Time
1.0 µs (8–Bits, 1/2 LSB)
Delay
1.0 µs
Figure 45. LED Driver
Figure 46. Transistor Driver
V
CC
V
CC
“ON”
V
CC
V < V
in ref
R
L
+
+
+
V
in
MC34071
–
MC34071
–
MC34071
–
V
ref
R
L
“ON”
(A) PNP
(B) NPN
V > V
in ref
Figure 47. AC/DC Ground Current Monitor
Figure 48. Photovoltaic Cell Amplifier
I
Load
R
F
–
+
I
Cell
V
O
MC34071
MC34071
–
V
O
+
Ground Current
Sense Resistor
R
S
R1
R1
R2
V
Cell
= 0 V
R2
V = I
R
S
1+
O
Load
V = I
Cell
O
R
F
O
V > 0.1 V
For V > 0.1V
O
R2
R1+R2
BW ( –3.0 dB) = GBW
http://onsemi.com
13
MC34071,2,4,A MC33071,2,4,A
Figure 49. Low Input Voltage Comparator
with Hysteresis
Figure 50. High Compliance Voltage to
Sink Current Converter
V
O
Hysteresis
I
out
R2
V
in
V
OH
V
ref R1
+
+
MC34071
–
MC34071
–
V
OL
V
in
V
in
V
V
inH
inL
V
R1
ref
V
inL
=
(V –V )+V
OL ref ref
R1+R2
R
V ±V
R1
in IO
V
inH
=
(V –V )+V
OH ref ref
I
out
=
R1+R2
R
R1
V =
H
(V –V
)
OH OL
R1+R
Figure 51. High Input Impedance
Differential Amplifier
Figure 52. Bridge Current Amplifier
+V
ref
R1
R2
R
F
R4
R
R
–
R3
1/2
–
V
O
–
V
O
MC34072
+
1/2
MC34072
MC34071
+V1
+V2
+
R
+
R = ∆R
R2
R1
R4
R3
∆R R
F
=
(Critical to CMRR)
V = V
ref
O
2
2R
(V ≥ 0.1 V)
R
F
∆R < < R
R > > R
R4
R3
R4
R3
V = 1
O
+
V2–V1
F
O
For (V2 ≥ V1), V > 0
Figure 54. High Frequency Pulse
Width Modulation
Figure 53. Low Voltage Peak Detector
0.85
RC
f
OSC
+
I
B
V
in
+
SC
V
I
+
V = V (pk)
O in
MC34071
V
P
0
–
t
–
Base Charge
Removal
t
+
I
out
R
L
V
P
10,000 pF
R
–
+
1/2
MC34072
1/2
MC34072
C
+
–
±I
B
V
in
V+
100 k
V
P
Pulse Width
Control Group
100 k
V
P
47 k
t
OSC
Comparator
High Current
Output
http://onsemi.com
14
MC34071,2,4,A MC33071,2,4,A
GENERAL ADDITIONAL APPLICATIONS INFORMATION V = ±15.0 V
S
Figure 55. Second Order Low–Pass Active Filter
Figure 56. Second Order High–Pass Active Filter
C2
0.02
R1
46.1 k
C2
0.05
C1
1.0
R2
5.6 k
–
R1
560
R3
510
MC34071
C1
1.0
–
f = 100 Hz
o
H = 20
o
R2
1.1 k
+
MC34071
C1
f = 1.0 kHz
H = 10
o
o
+
0.44
H +0.5
o
Then: R1 =
R2 =
Choose: f , H , C1
o
o
Choose: f , H , C2
o
o
πf C1
o
2
2
Then: C1 = 2C2 (H +1)
o
2πf C1 (1/H +2)
o
o
2
R2
R2
C
R2 =
R3 =
R1 =
C2 =
4πf C2
o
H +1
o
H
o
H
o
Figure 57. Fast Settling Inverter
Figure 58. Basic Inverting Amplifier
C *
F
V = 10 V
O
Step
R
F
+
MC34071
V
O
2.0 k
R1
–
R
L
–
V
in
R2
MC34071
V
O
+
V
O
R2
R1
R1
R1 +R2
I
=
BW (–3.0 dB) = GBW
t = 1.0 µs
V
in
s
Uncompensated
to 1/2 LSB (8–Bits)
SR = 13 V/µs
t = 2.2 µs
s
to 1/2 LSB (12–Bits)
High Speed
DAC
Compensated
SR = 13 V/µs
*Optional Compensation
Figure 59. Basic Noninverting Amplifier
Figure 60. Unity Gain Buffer (A = +1.0)
V
+
+
V
in
MC34071
V
O
MC34071
V
O
–
–
V
in
R2
R
L
BW = 200 kHz
p
R1
V = 20 V
O
pp
V
O
R2
R1
SR = 10 V/µs
=
1 +
V
in
R1
R1 +R2
BW (–3.0 dB) = GBW
http://onsemi.com
15
MC34071,2,4,A MC33071,2,4,A
Figure 61. High Impedance Differential Amplifier
+
R
R
MC34074
–
R
R
–
MC34074
V
O
R
E
+
–
R
Example:
Let: R = R = 12 k
Then: A = 3.0
V
BW = 1.5 MHz
MC34074
E
R
A = 1 + 2
V
+
R
E
R
Figure 62. Dual Voltage Doubler
+V
O
+
+
+
MC34074
R
L
100 k
+10
–
10
10
–
MC34074
220 pF
+
100 k
–10
+
+
R
L
+
10
MC34074
R
+V
–V
O
L
O
100 k
10
–
18.93 –18.78
∞
10 k
5.0 k
18
–18
–V
O
15.4
–15.4
http://onsemi.com
16
MC34071,2,4,A MC33071,2,4,A
ORDERING INFORMATION
Operating
Op Amp
Function
Temperature Range
Device
Package
Shipping
Single
MC34071P, MC34071AP
MC34071D, MC34071AD
MC34071DR2, MC34071ADR2
DIP–8
SO–8
SO–8 / Tape & Reel
50 Units / Rail
98 Units / Rail
2500 Units / Tape & Reel
T
A
= 0° to +70°C
MC33071P, MC33071AP
MC33071D, MC33071AD
MC33071DR2, MC33071ADR2
DIP–8
SO–8
SO–8 / Tape & Reel
50 Units / Rail
98 Units / Rail
2500 Units / Tape & Reel
T
A
= –40° to +85°C
Dual
MC34072P, MC34072AP
MC34072D, MC34072AD
MC34072DR2, MC34072ADR2
DIP–8
SO–8
SO–8 / Tape & Reel
50 Units / Rail
98 Units / Rail
2500 Units / Tape & Reel
T
A
= 0° to +70°C
MC33072P, MC33072AP
MC33072D, MC33072AD
MC33072DR2, MC33072ADR2
DIP–8
SO–8
SO–8 / Tape & Reel
50 Units / Rail
98 Units / Rail
2500 Units / Tape & Reel
T
= –40° to +85°C
= –40° to +125°C
A
MC34072VD
MC34072VDR2
SO–8
SO–8 / Tape & Reel
98 Units / Rail
2500 Units / Tape & Reel
T
A
Quad
MC34074P, MC34074AP
MC34074D, MC34074AD
MC34074DR2, MC34074ADR2
DIP–8
SO–8
SO–8 / Tape & Reel
50 Units / Rail
98 Units / Rail
2500 Units / Tape & Reel
T
A
= 0° to +70°C
MC33074P, MC33074AP
MC33074D, MC33074AD
DIP–8
SO–8
50 Units / Rail
98 Units / Rail
MC33074DR2, MC33074ADR2
MC33074DTB, MC33074ADTB
MC33074DTBR2, MC33074ADTBR2
SO–8 / Tape & Reel
TSSOP–14
TSSOP–14 / Tape & Reel
2500 Units / Tape & Reel
96 Units / Rail
2500 Units / Tape & Reel
T
= –40° to +85°C
= –40° to +125°C
A
MC34074VD
MC34074VDR2
SO–8
SO–8 / Tape & Reel
98 Units / Rail
2500 Units / Tape & Reel
T
A
http://onsemi.com
17
MC34071,2,4,A MC33071,2,4,A
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
8
5
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
–B–
1
4
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
MILLIMETERS
DIM MIN MAX
INCHES
F
MIN
MAX
0.400
0.260
0.175
0.020
0.070
–A–
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
10.16 0.370
6.60 0.240
4.45 0.155
0.51 0.015
1.78 0.040
NOTE 2
L
G
H
J
K
L
2.54 BSC
0.100 BSC
C
0.76
0.20
2.92
1.27 0.030
0.30 0.008
3.43
0.050
0.012
0.135
J
0.115
–T–
SEATING
PLANE
7.62 BSC
0.300 BSC
N
M
N
–––
0.76
10
–––
10
0.040
1.01 0.030
M
D
K
G
H
M
M
M
0.13 (0.005)
T A
B
D SUFFIX
(SO–8)
PLASTIC PACKAGE
CASE 751–05
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
A
E
C
8
1
5
4
M
M
0.25
B
H
MILLIMETERS
h X 45
DIM MIN
MAX
1.75
0.25
0.49
0.25
5.00
4.00
B
C
e
A
A1
B
C
D
E
1.35
0.10
0.35
0.18
4.80
3.80
A
SEATING
PLANE
e
H
h
1.27 BSC
L
5.80
0.25
0.40
0
6.20
0.50
1.25
7
0.10
A1
B
L
M
S
S
0.25
C B
A
http://onsemi.com
18
MC34071,2,4,A MC33071,2,4,A
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
DIM MIN MAX
0.770 18.16
MILLIMETERS
A
F
MIN
MAX
19.56
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
0.260
0.185
0.021
0.070
6.10
3.69
0.38
1.02
L
C
G
H
J
K
L
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
M
N
0
10
0.039
0
0.39
10
1.01
0.015
H
G
D
M
D SUFFIX
(SO–14)
PLASTIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
–B–
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
–T–
SEATING
PLANE
J
M
G
J
K
M
P
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
M
S
S
0.25 (0.010)
T B
A
7
0
5.80
0.25
6.20 0.228
0.50 0.010
0.244
0.019
R
http://onsemi.com
19
MC34071,2,4,A MC33071,2,4,A
PACKAGE DIMENSIONS
DTB SUFFIX
(TSSOP–14)
PLASTIC PACKAGE
CASE 948G–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14X K REF
M
S
S
Y14.5M, 1982.
0.10 (0.004)
T U
V
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
–U–
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
L
N
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
K
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
K1
MIN
MAX
0.200
0.177
0.047
0.006
0.030
–V–
A
B
C
4.90
4.30
–––
5.10 0.193
4.50 0.169
1.20
J J1
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
SECTION N–N
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60 0.020
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.024
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
SEATING
PLANE
–T–
H
G
DETAIL E
D
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
USA/EUROPE Literature Fulfillment:
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Email: ONlit–asia@hibbertco.com
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Phone: 81–3–5487–8345
Fax Response Line*: 303–675–2167
800–344–3810 Toll Free USA/Canada
*To receive a Fax of our publications
Email: r14153@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
N. America Technical Support: 800–282–9855 Toll Free USA/Canada
MC34071/D
相关型号：
©2020 ICPDF网 联系我们和版权申明