MC33151P [ONSEMI]
High Speed Dual MOSFET Drivers; 高速双MOSFET驱动器
| 型号： | MC33151P |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Dual MOSFET Drivers |
| 文件： | 总12页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC34151/MC33151 are dual inverting high speed drivers
specifically designed for applications that require low current digital
circuitry to drive large capacitive loads with high slew rates. These
devices feature low input current making them CMOS and LSTTL
logic compatible, input hysteresis for fast output switching that is
independent of input transition time, and two high current totem pole
outputs ideally suited for driving power MOSFETs. Also included is
an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.
http://onsemi.com
MARKING
DIAGRAMS
8
PDIP–8
P SUFFIX
CASE 626
MC3x151P
AWL
YYWW
Typical applications include switching power supplies, dc to dc
converters, capacitor charge pump voltage doublers/inverters, and
motor controllers.
8
1
1
These devices are available in dual–in–line and surface mount
packages.
• Two Independent Channels with 1.5 A Totem Pole Output
• Output Rise and Fall Times of 15 ns with 1000 pF Load
• CMOS/LSTTL Compatible Inputs with Hysteresis
• Undervoltage Lockout with Hysteresis
• Low Standby Current
• Efficient High Frequency Operation
• Enhanced System Performance with Common Switching Regulator
Control ICs
8
SO–8
D SUFFIX
CASE 751
3x151
ALYW
8
1
1
x
A
= 3 or 4
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
• Pin Out Equivalent to DS0026 and MMH0026
N.C.
1
2
3
4
8
7
6
5
N.C.
Drive Output A
Logic Input A
Gnd
Representative Block Diagram
V
CC
V
CC
6
Logic Input B
Drive Output B
+
+
–
+
+
(Top View)
5.7V
+
Drive Output A
7
Logic Input A
2
ORDERING INFORMATION
Device
Package
SO–8
Shipping
MC34151D
98 Units/Rail
2500 Tape & Reel
50 Units/Rail
+
MC34151DR2
MC34151P
SO–8
+
PDIP–8
SO–8
Drive Output B
5
Logic Input B
4
MC33151D
98 Units/Rail
MC33151DR2
MC33151P
SO–8
2500 Tape & Reel
50 Units/Rail
PDIP–8
SO–8
MC33151VDR2
2500 Units/Rail
3
Gnd
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
April, 2000 – Rev. 1
MC34151/D
MC34151, MC33151
MAXIMUM RATINGS
Rating
Symbol
Value
20
Unit
V
Power Supply Voltage
Logic Inputs (Note 1.)
Drive Outputs (Note 2.)
V
CC
V
in
–0.3 to V
V
CC
A
Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to V
I
1.5
1.0
O
)
I
CC
O(clamp)
Power Dissipation and Thermal Characteristics
D Suffix SO–8 Package Case 751
Maximum Power Dissipation @ T = 50°C
Thermal Resistance, Junction–to–Air
P Suffix 8–Pin Package Case 626
P
0.56
180
W
°C/W
A
D
R
θJA
Maximum Power Dissipation @ T = 50°C
Thermal Resistance, Junction–to–Air
P
1.0
100
W
°C/W
A
D
R
θJA
Operating Junction Temperature
T
+150
°C
°C
J
Operating Ambient Temperature
MC34151
T
A
0 to +70
MC33151
–40 to +85
Storage Temperature Range
T
stg
–65 to +150
°C
ELECTRICAL CHARACTERISTICS (V
CC
= 12 V, for typical values T = 25°C, for min/max values T is the only operating
A A
ambient temperature range that applies [Note 3.], unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
Input Threshold Voltage – High State Logic 1
Input Threshold Voltage – Low State Logic 0
V
V
2.6
–
1.75
1.58
–
0.8
V
IH
IL
Input Current – High State (V = 2.6 V)
Input Current – Low State (V = 0.8 V)
IL
I
I
–
–
200
20
500
100
µA
IH
IH
IL
DRIVE OUTPUT
Output Voltage – Low State (I
Output Voltage – Low State (I
Output Voltage – Low State (I
Output Voltage – High State (I
Output Voltage – High State (I
Output Voltage – High State (I
= 10 mA)
= 50 mA)
= 400 mA)
V
–
–
–
10.5
10.4
9.5
0.8
1.1
1.7
11.2
11.1
10.9
1.2
1.5
2.5
–
–
–
V
Sink
Sink
Sink
OL
= 10 mA)
= 50 mA)
= 400 mA)
V
OH
Source
Source
Source
Output Pull–Down Resistor
R
–
100
–
kΩ
PD
SWITCHING CHARACTERISTICS (T = 25°C)
A
Propagation Delay (10% Input to 10% Output, C = 1.0 nF)
L
Logic Input to Drive Output Rise
Logic Input to Drive Output Fall
ns
t
t
–
–
35
36
100
100
PLH(in/out)
PHL(in/out)
Drive Output Rise Time (10% to 90%) C = 1.0 nF
t
–
–
14
31
30
–
ns
ns
L
r
Drive Output Rise Time (10% to 90%) C = 2.5 nF
L
Drive Output Fall Time (90% to 10%) C = 1.0 nF
t
–
–
16
32
30
–
L
f
Drive Output Fall Time (90% to 10%) C = 2.5 nF
L
TOTAL DEVICE
Power Supply Current
Standby (Logic Inputs Grounded)
I
mA
V
CC
–
–
6.0
10.5
10
15
Operating (C = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)
L
Operating Voltage
V
6.5
–
18
CC
1. For optimum switching speed, the maximum input voltage should be limited to 10 V or V , whichever is less.
CC
2. Maximum package power dissipation limits must be observed.
3. T
=
0°C for MC34151
–40°C for MC33151
T
high
=
+70°C for MC34151
+85°C for MC33151
low
http://onsemi.com
2
MC34151, MC33151
12
V
4.7 0.1
+
6
+
+
–
+
+
5.7V
Drive Output
7
+
+
2
4
Logic Input
50
C
L
5.0 V
Logic Input
90%
+
t , t ≤ 10 ns
r f
10%
0 V
t
5
PLH
t
PHL
90%
10%
Drive Output
3
t
r
t
f
Figure 1. Switching Characteristics Test Circuit
Figure 2. Switching Waveform Definitions
2.4
2.2
V
= 12 V
V
= 12 V
CC
CC
2.0
1.8
1.6
1.4
1.2
1.0
T = 25°C
A
2.0
1.6
1.2
0.8
Upper Threshold
Low State Output
Lower Threshold
High State Output
0.4
0
0
2.0
4.0
6.0
8.0
10
12
–55
–25
0
25
50
75
100
125
V , INPUT VOLTAGE (V)
in
T , AMBIENT TEMPERATURE (°C)
A
Figure 3. Logic Input Current versus
Input Voltage
Figure 4. Logic Input Threshold Voltage
versus Temperature
200
160
200
160
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
V
= 12 V Overdrive Voltage is with Respect
V
= 12 V
CC
CC
C = 1.0 nF to the Logic Input Lower Threshold
C = 1.0 nF
L
L
T = 25°C
T = 25°C
A
A
120
80
40
0
120
80
40
0
V
V
th(upper)
1.0
V , INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)
th(lower)
–1.6
–1.2
–0.8
–0.4
0
0
2.0
3.0
4.0
V , INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)
in
in
Figure 5. Drive Output Low–to–High Propagation
Delay versus Logic Overdrive Voltage
Figure 6. Drive Output High–to–Low Propagation
Delay versus Logic Input Overdrive Voltage
http://onsemi.com
3
MC34151, MC33151
3.0
High State Clamp
(Drive Output Driven Above V
)
CC
V
= 12 V
CC
2.0
1.0
0
90%
10%
80 µs Pulsed Load
120 Hz Rate
T = 25°C
A
V
= 12 V
CC
V = 5 V to 0 V
Logic Input
in
C = 1.0 nF
L
T = 25°C
A
V
CC
Low State Clamp
(Drive Output Driven Below Ground)
Drive Output
0
Gnd
–1.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
50 ns/DIV
I , OUTPUT LOAD CURRENT (A)
O
Figure 7. Propagation Delay
Figure 8. Drive Output Clamp Voltage
versus Clamp Current
0
0
V
= 12 V
Source Saturation
(Load to Ground)
CC
V
CC
= 12 V
Source Saturation
(Load to Ground)
–0.5
–0.7
V
CC
80 µs Pulsed Load
120 Hz Rate
I
= 10 mA
V
CC
source
–1.0
–2.0
–3.0
3.0
2.0
1.0
0
T = 25°C
I
= 400 mA
–0.9
–1.1
A
source
1.9
1.7
I
= 400 mA
sink
1.5
1.0
0.8
I
= 10 mA
sink
Sink Saturation
Gnd
Sink Saturation
Gnd
0.6
0
(Load to V )
CC
(Load to V )
CC
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–55
–25
0
25
50
75
100
125
I , OUTPUT LOAD CURRENT (A)
O
T , AMBIENT TEMPERATURE (°C)
A
Figure 9. Drive Output Saturation Voltage
versus Load Current
Figure 10. Drive Output Saturation Voltage
versus Temperature
V
= 12 V
CC
90%
90%
V = 5 V to 0 V
in
C = 1.0 nF
L
T = 25°C
A
V
= 12 V
CC
V = 5 V to 0 V
in
C = 1.0 nF
L
10%
T = 25°C
10%
A
10 ns/DIV
10 ns/DIV
Figure 11. Drive Output Rise Time
Figure 12. Drive Output Fall Time
http://onsemi.com
4
MC34151, MC33151
80
60
40
20
0
80
V
= 12 V
CC
V
= 12 V
= 0 V to 5.0 V
CC
Both Logic Inputs Driven
0 V to 5.0 V
50% Duty Cycle
Both Drive Outputs Loaded
T = 25°C
A
V
IN
60
40
20
0
T = 25°C
A
f = 200 kHz
f = 50 kHz
f = 500 kHz
t
f
t
r
0.1
1.0
C , OUTPUT LOAD CAPACITANCE (nF)
10
0.1
1.0
C , OUTPUT LOAD CAPACITANCE (nF)
10
L
L
Figure 13. Drive Output Rise and Fall Time
versus Load Capacitance
Figure 14. Supply Current versus Drive Output
Load Capacitance
80
60
8.0
T = 25°C
A
Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle
Both Drive Outputs Loaded
1
Logic Inputs at V
CC
6.0
4.0
2.0
Low State Drive Outputs
2
T = 25°C
A
3
4
1 – V = 18 V, C = 2.5 nF
CC
CC
L
L
L
L
40 2 – V = 12 V, C = 2.5 nF
3 – V = 18 V, C = 1.0 nF
CC
Logic Inputs Grounded
High State Drive Outputs
4 – V = 12 V, C = 1.0 nF
CC
20
0
0
100
f, INPUT FREQUENCY (Hz)
1.0 M
10 k
0
4.0
8.0
, SUPPLY VOLTAGE (V)
12
16
V
CC
Figure 15. Supply Current versus Input Frequency
Figure 16. Supply Current versus Supply Voltage
APPLICATIONS INFORMATION
Description
Output Stage
The MC34151 is a dual inverting high speed driver
specifically designed to interface low current digital
circuitry with power MOSFETs. This device is constructed
with Schottky clamped Bipolar Analog technology which
offers a high degree of performance and ruggedness in
hostile industrial environments.
Each totem pole Drive Output is capable of sourcing and
sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 Ω at
1.0 A. The low ‘on’ resistance allows high output currents
to be attained at a lower V
than with comparative CMOS
drivers. Eachoutputhasa100kΩpull–downresistortokeep
CC
the MOSFET gate low when V is less than 1.4 V. No over
CC
current or thermal protection has been designed into the
Input Stage
device, so output shorting to V
avoided.
or ground must be
CC
TheLogicInputshave170mVofhysteresiswiththeinput
threshold centered at 1.67 V. The input thresholds are
Parasitic inductance in series with the load will cause the
driver outputs to ring above V during the turn–on
insensitive to V
making this device directly compatible
CC
CC
with CMOS and LSTTL logic families over its entire
operating voltage range. Input hysteresis provides fast
output switching that is independent of the input signal
transition time, preventing output oscillations as the input
thresholds are crossed. The inputs are designed to accept a
transition, and below ground during the turn–off transition.
With CMOS drivers, this mode of operation can cause a
destructive output latch–up condition. The MC34151 is
immune to output latch–up. The Drive Outputs contain an
internal diode to V
transients. When operating with V
for clamping positive voltage
at 18 V, proper power
CC
signal amplitude ranging from ground to V . This allows
CC
CC
the output of one channel to directly drive the input of a
second channel for master–slave operation. Each input has
a 30 kΩ pull–down resistor so that an unconnected open
inputwillcausetheassociatedDriveOutputtobeinaknown
high state.
supply bypassing must be observed to prevent the output
ringing from exceeding the maximum 20 V device rating.
Negative output transients are clamped by the internal NPN
pull–uptransistor. Sincefullsupplyvoltageisappliedacross
http://onsemi.com
5
MC34151, MC33151
the NPN pull–upduringthe negative output transient, power
gate charge information on their data sheets. Figure 17
shows a curve of gate voltage versus gate charge for the ON
Semiconductor MTM15N50. Note that there are three
distinct slopes to the curve representing different input
capacitance values. To completely switch the MOSFET
‘on’, the gate must be brought to 10 V with respect to the
dissipation at high frequencies can become excessive.
Figures 19, 20, and 21 show a method of using external
Schottky diode clamps to reduce driver power dissipation.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
source. The graph shows that a gate charge Q of 110 nC is
g
requiredwhenoperatingtheMOSFETwithadraintosource
the Drive Outputs into a low state as V
rises from 1.4 V
CC
voltage V
of 400 V.
DS
to the 5.8 V upper threshold. The lower UVLO threshold is
5.3 V, yielding about 500 mV of hysteresis.
16
MTM15N50
= 15 A
T = 25°C
A
Power Dissipation
I
D
Circuit performance and long term reliability are
enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the
junction temperature with the package in free air is:
12
V
DS
= 400 V
V
DS
= 100 V
8.0
4.0
8.9 nF
T = T + P (R
)
2.0 nF
J
J
A
D
A
D
θJA
∆ Q
g
C
GS
=
where:
T = Junction Temperature
∆ V
GS
T
P
= Ambient Temperature
= Power Dissipation
0
0
40
80
Q , GATE CHARGE (nC)
120
160
g
R
Thermal Resistance Junction to Ambient
θJA =
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
Figure 17. Gate–To–Source Voltage
versus Gate Charge
P
P
P
P + P + P
Q C T
The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
D =
Q
C
T
where:
= Quiescent Power Dissipation
= Capacitive Load Power Dissipation
P = Transition Power Dissipation
P
= V Q f
C g
C(MOSFET)
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 16. The
device’s quiescent power dissipation is:
The flat region from 10 nC to 55 nC is caused by the
drain–to–gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34151 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating
P
= V
I
CCL
(1–D) + I (D)
CCH
Q
CC
where:
I
= Supply Current with Low State Drive
CCL
the MC34151 at a higher V , additional charge can be
CC
Outputs
provided to bring the gate above 10 V. This will reduce the
‘on’ resistance of the MOSFET at the expense of higher
driver dissipation at a given operating frequency.
I
= Supply Current with High State Drive
Outputs
CCH
D = Output Duty Cycle
The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power
dissipation per driver is approximately:
The capacitive load power dissipation is directly related
to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
–4
)
P
P
9 V
CC
must be greater than zero.
(1.08 V
C f – 8 y 10
T
T
CC
L
P
C
= V (V
CC OH
– V ) C f
OL
L
where:
V
V
= High State Drive Output Voltage
= Low State Drive Output Voltage
C = Load Capacitance
L
f = frequency
OH
OL
Switching time characterization of the MC34151 is
performed with fixed capacitive loads. Figure 13 shows that
for small capacitance loads, the switching speed is limited
by transistor turn–on/off time and the slew rate of the
internal nodes. For large capacitance loads, the switching
speed is limited by the maximum output current capability
of the integrated circuit.
When driving a MOSFET, the calculation of capacitive
load power P is somewhat complicated by the changing
C
gatetosourcecapacitanceC asthedeviceswitches.Toaid
GS
in this calculation, power MOSFET manufacturers provide
http://onsemi.com
6
MC34151, MC33151
LAYOUT CONSIDERATIONS
High frequency printed circuit layout techniques are
optimum drive performance, it is recommended that the
initial circuit design contains dual power supply bypass
imperative to prevent excessive output ringing and overshoot.
Do not attempt to construct the driver circuit on
wire–wrap or plug–in prototype boards. When driving
large capacitive loads, the printed circuit board must contain
a low inductance ground plane to minimize the voltage spikes
induced by the high ground ripple currents. All high current
loops should be kept as short as possible using heavy copper
runs to provide a low impedance high frequency path. For
capacitors connected with short leads as close to the V pin
CC
and ground as the layout will permit. Suggested capacitors are
a low inductance 0.1 µF ceramic in parallel with a 4.7 µF
tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.
Proper printed circuit board layout is extremely
critical and cannot be over emphasized.
V
CC
V
in
0.1
47
6
+
–
5.7V
V
in
+
+
+
+
+
+
+
R
g
7
5
2
4
D
1
TL494
or
TL594
1N5819
Series gate resistor R may be needed to damp high frequency parasitic
g
oscillations caused by the MOSFET input capacitance and any series
3
wiring inductance in the gate–source circuit. R will decrease the
g
MOSFET switching speed. Schottky diode D can reduce the driver’s
1
power dissipation due to excessive ringing, by preventing the output pin
from being driven below ground.
The MC34151 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.
Figure 18. Enhanced System Performance with
Common Switching Regulators
Figure 19. MOSFET Parasitic Oscillations
+
+
7
4 X
1N5819
+
+
Isolation
Boundary
+
5
1N
5819
3
3
Output Schottky diodes are recommended when driving inductive loads at
high frequencies. The diodes reduce the driver’s power dissipation by
preventingthe output pins from being driven above V and below ground.
CC
Figure 20. Direct Transformer Drive
Figure 21. Isolated MOSFET Drive
http://onsemi.com
7
MC34151, MC33151
V
in
I
B
V
in
+
0
–
+
Base Charge
Removal
R
g(on)
+
C
1
R
g(off)
In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET’s turn–on and
turn–off times.
The totem–pole outputs can furnish negative base current for enhanced
transistor turn–off, with the addition of capacitor C .
1
Figure 22. Controlled MOSFET Drive
Figure 23. Bipolar Transistor Drive
V
CC
= 15 V
4.7 0.1
+
6
+
–
+
+
+
5.7V
+
+
6.8 10
1N5819
7
5
+
2
+ V ≈ 2.0 V
CC
O
+
47
+
6.8 10
1N5819
47
+
4
– V ≈ – V
O CC
+
330pF
3
10k
Output Load Regulation
I
O
(mA)
+V (V)
O
–V (V)
O
The capacitor’s equivalent series resistance limits the Drive Output Current
to1.5A.Anadditionalseriesresistormayberequiredwhenusingtantalumor
other low ESR capacitors.
0
27.7
27.4
26.4
25.5
24.6
22.6
–13.3
–12.9
–11.9
–11.2
–10.5
–9.4
1.0
10
20
30
50
Figure 24. Dual Charge Pump Converter
http://onsemi.com
8
MC34151, MC33151
PACKAGE DIMENSIONS
PDIP–8
P SUFFIX
CASE 626–05
ISSUE K
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
8
5
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–B–
MILLIMETERS
DIM MIN MAX
9.40 10.16 0.370 0.400
INCHES
MIN MAX
1
4
A
B
C
D
F
6.10
3.94
0.38
1.02
6.60 0.240 0.260
4.45 0.155 0.175
0.51 0.015 0.020
1.78 0.040 0.070
F
–A–
NOTE 2
L
G
H
J
K
L
2.54 BSC
0.100 BSC
1.27 0.030 0.050
0.30 0.008 0.012
0.76
0.20
2.92
3.43
0.115
0.135
C
7.62 BSC
0.300 BSC
M
N
–––
0.76
10
–––
10
1.01 0.030 0.040
J
–T–
SEATING
PLANE
N
M
D
K
G
H
M
M
M
0.13 (0.005)
T A
B
SO–8
D SUFFIX
CASE 751–06
ISSUE T
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
C
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
1
5
4
M
M
0.25
B
H
E
h X 45
MILLIMETERS
B
e
DIM MIN
MAX
1.75
0.25
0.49
0.25
5.00
4.00
A
A1
B
C
D
E
1.35
0.10
0.35
0.19
4.80
3.80
A
C
SEATING
PLANE
L
e
1.27 BSC
0.10
H
h
L
5.80
0.25
0.40
0
6.20
0.50
1.25
7
A1
B
M
S
S
0.25
C B
A
http://onsemi.com
9
MC34151, MC33151
Notes
http://onsemi.com
10
MC34151, MC33151
Notes
http://onsemi.com
11
MC34151, MC33151
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
CENTRAL/SOUTH AMERICA:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–spanish@hibbertco.com
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
001–800–4422–3781
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
Email: ONlit–asia@hibbertco.com
EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)
Email: ONlit–german@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Phone: 81–3–5740–2745
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
For additional information, please contact your local
Sales Representative.
*Available from Germany, France, Italy, England, Ireland
MC34151/D
相关型号：
©2020 ICPDF网 联系我们和版权申明