MC33368D [ONSEMI]
High Voltage GreenLine Power Factor Controller; 高压绿线功率因数控制器
| 型号： | MC33368D |
| 厂家： | 
ONSEMI |
| 描述： | High Voltage GreenLine Power Factor Controller |
| 文件： | 总20页 (文件大小：478K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC33368 is an active power factor controller that functions as a
boost preconverter in off–line power supply applications. MC33368 is
optimized for low power, high density power supplies requiring a
minimum board area, reduced component count and low power
dissipation. The narrow body SOIC package provides a small
footprint. Integration of the high voltage startup saves approximately
0.7 W of power compared to resistor bootstrapped circuits.
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MARKING
DIAGRAMS
16
The MC33368 features a watchdog timer to initiate output
switching, a one quadrant multiplier to force the line current to follow
the instantaneous line voltage a zero current detector to ensure critical
conduction operation, a transconductance error amplifier, a current
sensing comparator, a 5.0 V reference, an undervoltage lockout
DIP–16
P SUFFIX
CASE 648
MC33368P
AWLYYWW
16
1
16
1
SO–16
D SUFFIX
CASE 751K
(UVLO) circuit which monitors the V
supply voltage and a CMOS
CC
MC33368D
AWLYWW
driver for driving MOSFETs. The MC33368 also includes a
programmable output switching frequency clamp. Protection features
include an output overvoltage comparator to minimize overshoot, a
restart delay timer and cycle–by–cycle current limiting.
• Lossless Off–Line Startup
• Output Overvoltage Comparator
• Leading Edge Blanking (LEB) for Noise Immunity
• Watchdog Timer to Initiate Switching
• Restart Delay Timer
16
1
1
A
= Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
PIN CONNECTIONS
Line
16
1
2
3
4
5
6
7
8
5.0 V
ref
Restart Delay
Voltage FB
Comp
15 N/C
14 N/C
13
12
11
10
9
Frequency Clamp
Mult
V
CC
Current Sense
Zero Current
AGnd
Gate
PGnd
LEB
(Top View)
Line
1
2
3
4
5
6
7
8
16
5.0 V
ref
Restart Delay
Voltage FB
Comp
13
12
11
10
9
Frequency Clamp
Mult
V
CC
Current Sense
Zero Current
AGnd
Gate
PGnd
LEB
(Top View)
ORDERING INFORMATION
Device
Package
SO–16
SO–16
DIP–16
Shipping
MC33368D
MC33368DR2
MC33368P
48 Units/Rail
2500 Tape & Reel
25 Units/Rail
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
April, 2000 – Rev. 4
MC33368/D
MC33368
Representative Block Diagram
Line
Restart Delay
Restart Delay
V
CC
Output
Overvoltage
UVLO
Internal Bias
Generator
V
ref
FB
Comp
Mult
Multiplier/
Error
Amplifier
S
PWM
AGnd
S
R
Q
LEB
Current
Sense
Gate
Current Sense
PGnd
WatchdogTimer/
Zero Current Detector
Frequency
Clamp
Frequency
Clamp
ZC Det
This device contains 240 active transistors.
MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)
A
Rating
Power Supply Voltage (Transient)
Power Supply Voltage (Operating)
Line Voltage
Symbol
Value
20
Unit
V
V
V
V
V
V
CC
16
CC
V
Line
500
Current Sense, Multiplier, Compensation, Voltage Feedback, Restart Delay and Zero
Current Input Voltage
V
in1
–1.0 to +10
LEB Input, Frequency Clamp Input
Zero Current Detect Input
Restart Diode Current
V
–1.0 to +20
±5.0
V
in2
I
mA
mA
in
I
5.0
in
Power Dissipation and Thermal Characteristics
P Suffix, Plastic Package Case 648
Maximum Power Dissipation @ T = 70°C
Thermal Resistance, Junction–to–Air
P
1.25
100
mW
°C/W
A
D
R
θJA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package Case 751K
Maximum Power Dissipation @ T = 70°C
P
450
178
mW
°C/W
A
D
Thermal Resistance, Junction–to–Air
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature Range
R
θJA
T
150
°C
°C
°C
J
T
A
–25 to +125
–55 to +150
T
stg
NOTE: ESD data available upon request.
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MC33368
ELECTRICAL CHARACTERISTICS (V
= 14.5 V, for typical values T = 25°C, for min/max values T = –25 to +125°C)
CC
A
J
Characteristic
Symbol
Min
Typ
Max
Unit
ERROR AMPLIFIER
Input Bias Current (V
= 5.0 V)
I
–
–
0
1.0
50
80
µA
mV
FB
IB
Input Offset Voltage (V
= 3.0 V)
V
2.0
51
Comp
IO
Transconductance (V
Comp
= 3.0 V)
g
30
µmho
µA
m
Output Source (V
FB
= 4.6 V, V
= 5.4 V, V
= 3.0 V)
= 3.0 V)
I
I
9.0
9.0
17.5
17.5
30
30
Comp
Comp
O
O
Output Sink (V
FB
OVERVOLTAGE COMPARATOR
Voltage Feedback Input Threshold
V
1.07 V
–
1.084 V
705
1.1 V
–
V
FB(OV)
FB
FB
FB
Propagation Time to Output
T
P
ns
MULTIPLIER
Input Bias Current, V
(V
= 0 V)
I
–
–0.2
2.1
–1.0
2.4
µA
V
Mult FB
IB
Input Threshold, V
V
1.8
Comp
th(M)
Dynamic Input Voltage Range
Multiplier Input
Compensation
V
V
0 to 2.5
to
0 to 3.5
V to
–
–
Mult
V
Comp
V
th(M)
+ 1.0) (V
th(M)
+ 2.0)
(V
th(M)
th(M)
Multiplier Gain (V
V
= 0.5 V, V
= V + 1.0 V)
th(M)
K
0.25
0.51
0.75
1/V
Mult
Comp
Threshold
CS
K
V
V
– V
Comp
Mult
VOLTAGE REFERENCE
th(M)
Voltage Reference (I = 0 mA, T = 25°C)
V
ref
4.95
–
5.0
5.0
5.0
–
5.05
100
100
5.2
–
V
mV
mV
V
O
J
Line Regulation (V
CC
= 10 V to 16 V)
Reg
line
Load Regulation (I = 0 – 5.0 mA)
Reg
–
O
load
Total Output Variation Over Line, Load and Temperature
Maximum Output Current
V
ref
4.8
5.0
–
I
O
10
4.5
mA
V
Reference Undervoltage Lockout Threshold
ZERO CURRENT DETECTOR
V
th
–
Input Threshold Voltage (V Increasing)
in
V
1.0
100
–
1.2
200
127
1.4
300
–
V
th
Hysteresis (V Decreasing)
in
V
mV
ns
H
Delay to Output
T
pd
CURRENT SENSE COMPARATOR
Input Bias Current (V
= 0 to 2.0 V)
I
–
–
0.2
4.0
1.5
1.0
50
µA
mV
V
CS
IB
Input Offset Voltage (V
= –0.2 V)
V
Mult
IO
Maximum Current Sense Input Threshold (V
= 5.0 V,
V
1.3
1.8
Comp
th(max)
V
Mult
= 5.0 V)
Delay to Output (V
(V
= 12 V, V
Comp
= 5.0 V, V
= 5.0 V)
t
PHL(in/out)
50
270
425
ns
LEB
CS
Mult
= 0 to 5.0 V Step, C = 1.0 nF)
L
FREQUENCY CLAMP
Frequency Clamp Input Threshold
V
1.9
0.5
–
2.0
1.7
7.3
2.1
4.0
8.0
V
mA
V
th(FC)
Frequency Clamp Capacitor Reset Current (V
Frequency Clamp Disable Voltage
= 0.5 V)
I
reset
FC
V
DFC
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MC33368
ELECTRICAL CHARACTERISTICS (continued) (V
= 14.5 V, for typical values T = 25°C, for min/max values T = –25 to +125°C)
A J
CC
Characteristic
Symbol
Min
Typ
Max
Unit
DRIVE OUTPUT
Source Resistance (Current Sense = 0 V, V
Gate
= V
CC
= 1.0 V)
– 1.0 V)
R
R
OL
4.0
4.0
8.6
7.2
20
20
Ω
OH
Sink Resistance (Current Sense = 3.0 V, V
Gate
Output Voltage Rise Time (25% – 75%) (C = 1.0 nF)
t
–
–
–
55
70
200
200
0.25
ns
ns
V
L
r
Output Voltage Fall Time (75% – 25%) (C = 1.0 nF)
t
f
L
Output Voltage in Undervoltage (V
= 7.0 V, I
= 1.0 mA)
V
O(UV)
0.01
CC
Sink
LEADING EDGE BLANKING
Input Bias Current
I
–
0.1
2.25
270
0.5
2.75
500
µA
V
bias
Threshold (as Offset from V ) (V
CC LEB
Increasing)
V
1.0
100
LEB
Hysteresis (V
LEB
Decreasing)
V
H
mV
UNDERVOLTAGE LOCKOUT
Startup Threshold (V Increasing)
V
11.5
7.0
–
13
8.5
4.5
14.5
10
–
V
V
V
CC
th(on)
Minimum Operating Voltage After Turn–On (V
Decreasing)
V
V
CC
Shutdown
Hysteresis
V
H
TIMER
Watchdog Timer
t
180
1.5
3.1
385
2.3
5.2
800
3.0
7.1
µs
V
DLY
Restart Timer Threshold
th(restart)
Restart Pin Output Current (V
= 0 V, V = 5.0 V)
ref
I
mA
restart
restart
TOTAL DEVICE
Line Startup Current (V
= 0 V, V
= 50 V)
I
5.0
3.0
16
25
20
mA
mA
mA
CC
Line
, V = 50 V)
th(on) Line
SU
OP
CC
Line Operating Current (V
= V
I
I
12.9
CC
V
CC
V
CC
Dynamic Operating Current (50 kHz, C = 1.0 nF)
Static Operating Current (I = 0)
–
–
5.3
3.0
8.5
–
L
O
Line Pin Leakage (V
Line
= 500 V)
I
–
30
80
µA
Line
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MC33368
0.08
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
V
A
= 14 V
CC
T = 25°C
V
Pin 4
= 4.0 V
V
= 4.0 V
Pin 4
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
= 3.0 V
= 2.75 V
= 3.75 V
= 3.0 V
= 2.75 V
= 2.5 V
= 3.5 V
= 3.25 V
= 2.5 V
= 2.25 V
= 2.0 V
= 2.25 V
= 2.0 V
0
–0.2
0.6
1.4
2.2
3.0
–0.12
–0.06
0
0.06
0.12
0.20
V , MULTIPLIER PIN 5 INPUT VOLTAGE (V)
M
V , MULTIPLIER PIN 5 INPUT VOLTAGE (V)
M
Figure 2. Current Sense Input Threshold
versus Multiplier Input, Expanded View
Figure 1. Current Sense Input Threshold
versus Multiplier Input
16
12
110
109
108
107
V
CC
= 14 V
V
CC
= 14 V
8.0
4.0
0
–4.0
–55
106
–55
–25
0
25
50
75
100
125
–25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 3. Reference Voltage versus Temperature
Figure 4. Overvoltage Comparator Input
Threshold versus Temperature
6.0 V
4.0 V
2.0 V
0 V
100
80
60
40
20
0
Phase
V
A
= 14 V
CC
T = 25°C
30
60
90
120
Transconductance
V
O
L
A
= 14 V
V = 2.0 to 4.0 V
R = 10 kΩ
T = 25°C
CC
0
150
180
–20
10
–1.0 V
100
1.0 k
10 k
100 k
1.0 M
10 M
f, FREQUENCY (Hz)
5.0 µs/DIV
Figure 5. Error Amplifier Transconductance
and Phase versus Frequency
Figure 6. Error Amplifier Transient Response
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MC33368
1.80
1.76
1.72
1.68
1.64
1.50
1.30
1.10
0.90
0.70
500
V
CC
= 14 V
V
CC
= 14 V
Voltage
Current
460
420
380
340
–55
–25
0
25
50
75
100
125
–55
–25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 7. Quickstart Charge Current
versus Temperature
Figure 8. Watchdog Timer Delay
versus Temperature
6.0
4.0
2.0
20
15
Pulse tested with a 4.0 V peak, 50 kHz square
wave through a 22 k resistance into Pin 7.
V
= 14 V
CC
C = 1000 pF
L
T = 25°C
A
10
C
= 1000 pF
O
5.0
Pin 3, 6, 8= Gnd
Pin 5 = 1.0 k to Gnd
T = 25°C
A
0
–5.0
2.0
4.0
6.0
8.0
V , SUPPLY VOLTAGE (V)
CC
10
12
14
5.0 µs/DIV
0
Figure 9. Drive Output Waveform
Figure 10. Supply Current versus
Supply Voltage
1000
400
200
0
3.0
Output
Voltage
2.0
1.0
0
100
10
Load
Current
0.01
0.1
1.0
10
100
t, TIME (s)
200 ms/DIV
Figure 11. Transient Thermal Resistance
Figure 12. Low Load Detection
Response Waveform
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MC33368
FUNCTIONAL DESCRIPTION
INTRODUCTION
input circuits operate at a frequency much higher than that
of the ac line, they are smaller, lighter in weight, and more
efficient than a passive circuit that yields similar results.
With proper control ofthepreconverter, almostanycomplex
load can be made to appear resistive to the ac line, thus
significantly reducing the harmonic current content.
With the goal of exceeding the requirements of legislation
on line current harmonic content, there is an ever increasing
demand for an economical method of obtaining a unity
power factor. This data sheet describes a monolithic control
IC that was specifically designed for power factor control
with minimal external components. It offers the designer a
simple cost effective solution to obtain the benefits of active
power factor correction.
Operating Description
The MC33368 contains many of the building blocks and
protection features that are employed in modern high
performance current mode power supply controllers.
Referring to the block diagram in Figure 15, note that a
multiplier has been added to the current sense loop and that
this device does not contain an oscillator. A description of
each of the functional blocks is given below.
Most electronic ballasts and switching power supplies use
a bridge rectifier and a bulk storage capacitor to derive raw
dc voltage from the utility ac line, Figure 13.
Converter
Rectifiers
Bulk
Storage
Capacitor
Error Amplifier
AC
Line
Load
An Error Amplifier with access to the inverting input and
output is provided. The amplifier is a transconductance type,
meaning that it has high output impedance with controlled
Figure 13. Uncorrected Power Factor Circuit
voltage–to–currentgain(g
50µmhos). Thenoninverting
m
input is internally biased at 5.0 V ±2.0%. The output voltage
of the power factor converter is typically divided down and
monitored by the inverting input. The maximum input bias
current is –1.0 µA which can cause an output voltage error
that is equal to the product of the input bias current and the
value of the upper divider resistor R2. The Error Amplifier
output is internally connected to the Multiplier and is pinned
out (Pin 4) for external loop compensation. Typically, the
bandwidth is set below 20 Hz so that the amplifier’s output
voltage is relatively constant over a given ac line cycle. In
effect, the error amplifier monitors the average output voltage
of the converter over several line cycles resulting in a fixed
Drive Output on–time. The amplifier output stage can sink
andsource 11.5 µA of current and is capable of swinging from
1.7 to 5.0 V, assuring that the Multiplier can be driven over its
entire dynamic range.
This simple rectifying circuit draws power from the line
when the instantaneous ac voltage exceeds the capacitor
voltage. This occurs near the line voltage peak and results in
a high charge current spike, Figure 14. Since power is only
taken near the line voltage peaks, the resulting spikes of
current are extremely nonsinusoidal with a high content of
harmonics. This results in a poor power factor condition
where the apparent input power is much higher than the real
power. Power factor ratios of 0.5 to 0.7 are common.
V
pk
Rectified
DC
0
Line Sag
Note that by using a transconductance type amplifier, the
input is allowed to move independently with respect to the
output, since the compensation capacitor is connected to
ground. This allows dual usage of the Voltage Feedback pin
by the Error Amplifier and Overvoltage Comparator.
AC Line
Voltage
0
Overvoltage Comparator
AC Line
Current
An Overvoltage Comparator is incorporated to eliminate
the possibility of runaway output voltage. This condition
can occur during initial startup, sudden load removal, or
during output arcing and is the result of the low bandwidth
that must be used in the Error Amplifier control loop. The
Overvoltage Comparator monitors the peak output voltage
of the converter, and when exceeded, immediately
terminates MOSFET switching. The comparator threshold
Figure 14. Uncorrected Power Factor Input Waveforms
Power factor correction can be achieved with the use of
either a passive or active input circuit. Passive circuits
usuallycontain a combination of large capacitors, inductors,
and rectifiers that operate at the ac line frequency. Active
circuits incorporate some form of a high frequency
switching converter for the power processing with the boost
converter being the most popular topology. Since active
is internally set to 1.08V .Inordertopreventfalsetripping
ref
during normal operation, the value of the output filter
capacitorC3 must be largeenoughtokeepthepeak–to–peak
ripple less than 16% of the average dc output.
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MC33368
Multiplier
Sense Comparator threshold will be internally clamped to
1.5 V. Therefore, the maximum peak switch current is:
A single quadrant, two input multiplier is the critical
element that enables this device to control power factor. The
ac haversines are monitored at Pin 5 with respect to ground
while the Error Amplifier output at Pin 4 is monitored with
respect to the Voltage Feedback Input threshold. A graph of
the Multiplier transfer curve is shown in Figure 1. Note that
both inputs are extremely linear over a wide dynamic range,
0 to 3.2 V for Pin 5 and 2.5 to 4.0 V for Pin 4. The Multiplier
output controls the Current Sense Comparator threshold as
the ac voltage traverses sinusoidally from zero to peak line.
This has the effect of forcing the MOSFET on–time to track
the input line voltage, thus making the preconverter load
appear to be resistive.
1.5 V
R7
I
pk(max)
With the component values shown in Figure 15, the
Current Sense Comparator threshold, at the peak of the
haversine, varies from 110 mV at 90 Vac to 100 mV at
268 Vac. The Current Sense Input to Drive Output
propagation delay is typically 200 ns.
Timer
A watchdog timer function was added to the IC to
eliminate the need for an external oscillator when used in
stand alone applications. The Timer provides a means to
automatically start or restart the preconverter if the Drive
Output has been off for more than 385 µs after the inductor
current reaches zero.
Pin 6 Threshold
0.55
V
– V
V
Pin 4
Pin 3
Pin 5
Zero Current Detector
The MC33368 operates as a critical conduction current
mode controller, whereby output switch conduction is
initiated by the Zero Current Detector and terminated when
the peak inductor current reaches the threshold level
established by the Multiplier output. The Zero Current
Undervoltage Lockout and Quickstart
The MC33368 has a 5.0 V internal reference brought out
to Pin 1 and capable of sourcing 10 mA typically. It also
contains an Undervoltage Lockout (UVLO) circuit which
suppresses the Gate output at Pin 11 if the V
voltage drops below 8.5 V typical.
supply
CC
Detector initiates the next on–time by setting the R Latch
S
at the instant the inductor current reaches zero. This critical
conduction mode of operation has two significant benefits.
First, since the MOSFET cannot turn–on until the inductor
current reaches zero, the output rectifier’s reverse recovery
timebecomeslesscriticalallowingtheuseofaninexpensive
rectifier. Second, since there are no deadtime gaps between
cycles, the ac line current is continuous thus limiting the
peak switch to twice the average input current
The Zero Current Detector indirectly senses the inductor
current by monitoring when the auxiliary winding voltage
falls below 1.2 V. To prevent false tripping, 200 mV of
hysteresis is provided. The Zero Current Detector input is
internally protected by two clamps. The upper 10 V clamp
prevents input overvoltage breakdown while the lower
–0.7 V clamp prevents substrate injection. An external
resistor must be used in series with the auxiliary winding to
limit the current through the clamps to 5.0 mA or less.
A Quickstart circuit has been incorporated to optimize
converter startup. During initial startup, compensation
capacitorC1 will bedischarged, holding the Error Amplifier
output below the Multiplier’s threshold. This will prevent
Drive Output switching and delay bootstraping of capacitor
C4 by diode D6. If Pin 4 does not reach the multiplier
threshold before C4 discharges below the lower SMPS
UVLO threshold, the converter will hiccup and experience
a significant startup delay. The Quickstart circuit is designed
to precharge C1 to 1.7 V. This level is slightly below the
Pin 4 Multiplier threshold, allowing immediate Drive
Output switching.
Restart Delay
A restart delay pin is provided to allow hiccup mode fault
protection in case of a short circuit condition and to prevent
the SMPS from repeatedly trying to restart after the input
line voltage has been removed. When power is first applied,
Current Sense Comparator and RS Latch
The Current Sense Comparator R Latch configuration
S
there is no startup delay, but subsequent cycling of the V
CC
voltage will result in delay times that are programmed by an
external resistor and capacitor. The Restart Delay, Pin 2, is
a high impedance, so that an external capacitor can provide
delay times as long as several seconds.
used ensures that only a single pulse appears at the Drive
Output during a given cycle. The inductor current is
converted to a voltage by inserting a ground–referenced
sense resistor R7 in series with the source of output switch.
This voltage is monitored by the Current Sense Input and
compared to a level derived from the Multiplier output. The
peak inductor current under normal operating conditions is
controlled by the threshold voltage of Pin 6 where:
If the SMPS output is short circuited, the transformer
winding, which provides the V
and the MC33368, will be unable to sustain V
CC
voltage to the control IC
to the
CC
control circuits. The restart delay capacitor at Pin 2 of the
MC33368prevents the high voltage startup transistor within
the IC from maintaining the voltage on C4. After V drops
CC
Pin 6 Threshold
I
below the UVLO threshold in the SMPS, the SMPS
switching transistors are held off for the time programmed
by the values of the restart capacitor (C9) and resistor (R8).
In this manner, the SMPS switching transistors are operated
pk
R7
Abnormal operating conditions occur when the
preconverter is running at extremely low line or if output
voltage sensing is lost. Under these conditions, the Current
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MC33368
at very low duty cycles, preventing their destruction. If the
Forbestresults, theminimumoff–time, determinedbythe
valuesofR10andC7,shouldbechosensothatt =t
short circuit fault is removed, the power supply system will
turn on by itself in a normal startup mode after the restart
delay has timed out.
s(min) (on)
. Output drive is inhibited when the voltage at the
+ t
(off)fc
frequency clamp input is less than 2.0 V. When the output
drive is high, C7 is discharged through an internal 100 µA
current source. When the output drive switches low, C7 is
charged through R10. The drive output is inhibited until the
voltage across C7 reaches 2.0 V, establishing a minimum
off–time where:
Output Switching Frequency Clamp
In normal operation, the MC33368 operates the boost
inductor in the critical mode. That is, the inductor current
ramps to a peak value, ramps down to zero, then
immediately begins ramping positive again. The peak
current is programmed by the multiplier output within the
IC. As the input voltage haversine declines to near zero, the
output switch on–time becomes constant, rather than going
to zero because of the small integrated dc voltage at Pin 5
caused by C2, R3 and R5. Because of this, the average line
current does not exactly follow the line voltage near the zero
crossings. The Output Switching Frequency Clamp
remedies this situation to improve power factor and
minimize EMI generated in this operating region. The
values of R10 and C7, as shown in Figure 15, program a
minimum off–time in the frequency clamp which overrides
the zero current detect signal, forcing a minimum off–time.
This allows discontinuous conduction operation of the boost
inductor in the zero crossing region, and the average line
current more nearly follows the voltage. The Output
Switching Frequency Clamp function can be disabled by
2
t
R10 C7 log
1
e
(off)fc
V
CC
Output
The IC contains a CMOS output driver that was
specifically designed for direct drive of power MOSFETs.
The Gate Output is capable of up to ±1500 mA peak current
with a typical rise and fall time of 50 ns with a 1.0 nF load.
Additionalinternal circuitryhas beenaddedtokeepthe Gate
Output in a sinking mode whenever the Undervoltage
Lockout is active. This characteristic eliminates the need for
an external gate pull–down resistor. The totem–pole output
has been optimized to minimize cross–conduction current
during high speed operation.
connecting the FC input, Pin 13, to the V
supply Pin 12.
CC
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9
MC33368
Table 1. Design Equations
Calculation
Formula
Notes
Converter Output Power
Calculate the maximum required output power.
P
V
I
O
O O
2 P
Peak Indicator Current
Inductance
Calculated at the minimum required ac line voltage for
output regulation. Let the efficiency η = 0.92 for low line
operation.
2
O
I
L(pk)
Vac
(LL)
Let the switching cycle t = 40 µs for universal input (85
to 265 Vac) operation and 20 µs for fixed input (92 to
138 Vac, or 184 to 276 Vac) operation.
V
O
2
2
t
–Vac
Vac
(LL)
(LL)
L
P
2 V
P
O
O
Switch On–Time
Switch Off–Time
In theory, the on–time t
(on)
is constant. In practice, t
(on)
2 P
L
tends to increase at the ac line zero crossings due to
the charge on capacitor C5. Let Vac = Vac for initial
O
P
t
(on)
(LL)
2
Vac
t
and t
calculations.
(on)
(off)
The off–time t
(off)
is greatest at the peak of the ac line
t
(on)
t
voltage and approaches zero at the ac line zero
crossings. Theta (θ) represents the angle of the ac line
voltage.
(off)
t
V
O
–1
2 Vac Sin
Minimum Switch
Off–Time
The off–time is at a minimum at ac line crossings. This
equation is used to calculate t
zero.
L
I
P L(pk)
as Theta approaches
(off)
(off)
min
V
O
Delay Time
The delay time is used to override the minimum
off–time at the ac line zero crossings by programming
the Frequency Clamp with C7 and R10.
V
– 2
CC
t
– R10 C7 ln
d
V
CC
Switching Frequency
The minimum switching frequency occurs at the peak of
the ac line voltage. As the ac line voltage traverses
1
f
t
t
from peak to zero, t
approaches zero producing an
(off)
(on)
(off)
increase in switching frequency.
Peak Switch Current
Set the current sense threshold V
universal input (85 to 265 Vac) operation and to 0.5 V
for fixed input (92 to 138 Vac, or 184 to 276 Vac)
to 1.0 V for
CS
V
CS
R7
I
L(pk)
operation. Note that V
must be less than 1.4 V.
CS
Multiplier Input Voltage
Set the multiplier input voltage V to 3.0 V at high line.
M
Vac
2
1
Empirically adjust V for the lowest distortion over the
M
V
V
M
R5
R3
ac line voltage range while guaranteeing startup at
minimum line.
Converter Output
Voltage
The I R1 error term can be minimized with a divider
IB
current in excess of 100 µA.
R2
R1
V
– I R1
IB
1
O
ref
Converter Output
Peak–to–Peak
Ripple Voltage
The calculated peak–to–peak ripple must be less than
16% of the average dc output voltage to prevent false
tripping of the Overvoltage Comparator. Refer to the
Overvoltage Comparator Text. ESR is the equivalent
series resistance of C3.
2
1
2
V
I
ESR
O(pp)
L(pk)
2
f
C3
ac
Error Amplifier
Bandwidth
The bandwidth is typically set to 20 Hz. When operating
at high ac line, the value of C1 may need to be
increased.
g
m
C1
BW
2
NOTE: The following converter characteristics must be chosen:
= Desired output voltage. Vac = AC RMS minimum required operating line voltage for output regulation.
V
O
(LL)
O
I
O
= Desired output current.
∆V = Converter output peak–to–peak ripple voltage.
Vac = AC RMS operating line voltage.
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10
MC33368
1N4006
D4
C5
1.0
D2
D1
92 to
270
Vrms
EMI
Filter
D3
16 Line
V
ref
MC33368
V
ref
D8 R13 D6
1N4744
15 V
R8
10 k
V
51 1N4934
CC
RD
UVLO
Q
Timer
R
12
C9
330 µF
2
C4
100
Zero
Current
Detect
AGnd
13/8.0
7
15 V
8
R Latch
S
T
ZCD
R4
22 k
320 µH
MUR130
1.2/1.0
R
1.5 V
R
S
Gate
11
V
O
D5
S
Q1
Q
R11
10
S
C3
220
Set Dominant
To V
CC
Pin 12
Overvoltage
Comparator
PGnd
10
MTP8N50E
R5
1.3 M
R2
470 k
R10
10
C7
10 pF
Low
Load Detect
13
Frequency
Clamp
1.08 x V
ref
FC
9
Quickstart
LEB
6
Leading Edge
Blanking
CS
R7
0.1
0.25 W
Mult
5
5.0 V
Reference
Multiplier
C2
R3
20 k
0.01
4
Comp
C1
0.68
1
V
3
FB
ref
V
ref
R1
C6
0.1
10 k
T: Coilcraft N2881–A
Not Used: D7, C8, R6, R9
Primary = 62 turns of #22 AWG
Secondary = 5 turns of #22 AWG
Core = Coilcraft PT2510, EE25
Gap = 0.072″ total for a primary inductance (Lp) of 320 µH
Power Factor Controller Test Data
DC Output
AC Line Input
Current Harmonic Distortion (% I
)
fund
V
rms
Pin
PF
I
THD
2
3
5
7
V
O(pp)
V
O
I
O
P
O
n(%)
fund
90
79.7 0.999 0.89
0.5
0.5
0.5
0.5
0.5
0.5
0.15 0.09 0.06 0.09
0.14 0.09 0.08 0.10
0.16 0.13 0.08 0.10
0.15 0.12 0.08 0.13
0.14 0.12 0.07 0.14
0.15 0.14 0.08 0.14
3.0
3.0
3.0
3.0
3.0
3.0
244.4 0.31 76.01 95.4
242.9 0.31 75.54 95.3
242.9 0.31 75.30 95.4
243.0 0.31 75.57 96.3
243.0 0.31 75.57 96.7
243.0 0.31 75.57 97.1
100 79.3 0.998 0.79
110 78.9 0.997 0.72
120 78.5 0.996 0.66
130 78.1 0.994 0.60
138 77.8 0.991 0.57
Heatsink = AAVID Engineering Inc., 590302B03600, or 593002B03400
Figure 15. 80 W Power Factor Controller
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11
MC33368
1N5406
D4
C5
1.0
D2
D1
EMI
92 to
D3
Filter
270 Vrms
16 Line
V
ref
MC33368
V
ref
D8 R13 D6
1N4744
15 V
R8
1.0 M
V
51 1N4934
CC
RD
UVLO
Q
Timer
R
12
C9
2.2
2
C4
100
Zero
Current
Detect
AGnd
13/8.0
7
8
15 V
R Latch
S
T
ZCD
6.9 V
R4
22 k
R
1.2/1.0
1.5 V
MUR460
D5
R
S
S
S
Gate
11
V
O
Q
Q1
R11
10
C3
330
Set Dominant
To V
CC
Pin 12
Overvoltage
Comparator
PGnd
10
MTW20N50E
R5
1.3 M
R2
820 k
Low
Load Detect
13
Frequency
Clamp
1.08 x V
ref
FC
9
Quickstart
LEB
6
Leading Edge
Blanking
CS
Mult
5
R7
0.1
5.0 V
Reference
Multiplier
C2
R3
10 k
0.01
4
Comp
1
V
ref
3
FB
C1
2.2
V
ref
T: Coilcraft N2880–A
L = 870 µHy
Primary: 78 turns of #16 AWG
Secondary: 6 turns of #18 AWG
R1
10 k
C6
0.1
Core: Coilcraft PT4215, EE42–15
Gap: 0.104″ total
Not Used: D7, C7, C8, R6, R9, R10
Power Factor Controller Test Data
DC Output
AC Line Input
Current Harmonic Distortion (% I
)
fund
V
rms
Pin
PF
I
THD
2
3
5
7
V
O(pp)
V
O
I
O
P
O
n(%)
fund
90 190.4 0.995 2.11
120 192.1 0.997 1.60
138 192.7 0.997 1.40
180 194.3 0.995 1.08
240 189.3 0.983 0.80
268 186.3 0.972 0.71
5.8
3.2
0.9
0.9
0.7
0.6
0.16 0.32 0.24 0.80
0.08 0.17 0.07 0.30
0.08 0.24 0.03 0.15
0.04 0.18 0.04 0.08
0.08 0.21 0.08 0.06
0.11 0.32 0.10 0.10
3.6
3.6
3.6
3.6
3.6
3.6
398.0 0.44 175.9 92.4
398.9 0.44 177.1 92.2
402.3 0.45 179.0 92.9
409.1 0.45 182.9 94.1
407.0 0.45 181.1 95.7
406.2 0.44 180.4 96.8
Heatsink = AAVID Engineering Inc., 590302B03600
Figure 16. 175 W Universal Input Power Factor Controller
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MC33368
2X Step–up
Isolation
Transformer
EMI Filter
T
Autoformer
Line
AC Power
Analyzer
PM 1000
HI
HI
0 to 270 Vac
Output to
1.0
W
VA PF
V
A
rms rms
0.1
115 Vrms
Input
Power Factor
Correction
Circuit
A
V
V
D
Acf Ainst Freq HARM
1
0
L.O.
L.O.
Voltech
Neutral
An RFI filter is required for best performance when connecting the preconverter directly to the ac line. The filter attenuates the level of high frequency switching that
appears on the ac line current waveform. Figures 15 and 16 work well with commercially available two stage filters such as the Delta Electronics 03DPCG6. Shown
above is a single stage test filter that can easily be constructed with four ac line rated capacitors and a common–mode transformer. Coilcraft CMT3–28–2 was used
to test Figures 15 and 16. It has a minimum inductance of 28 mH and a maximum current rating of 2.0 A. Coilcraft CMT4–17–9 was used to test Figure 19. It has a
minimum inductance of 17 mH and a maximum current rating of 9.0 A. Circuit conversion efficiency η (%) was calculated without the power loss of the RFI filter.
Figure 17. Power Factor Test Setup
D2
D1
D4
C5
1.0
EMI
Filter
92 to
270 Vrms
D3
16 Line
V
ref
V
ref
MC33368
R8
10 k
R13
51
15 V
V
D6
CC
D8
RD
UVLO
Q
Timer
R
12
C9
330 µF
2
C4
100
Zero
Current
Detect
AGnd
13/8.0
7
8
15 V
R Latch
S
T
ZCD
6.9 V
R4
22 k
1.2/1.0
R
1.5 V
1N4148
R
S
DC
Out
Gate
11
D5
S
Q1
Q
R11
10
S
C3
330
On/Off
Input
Set Dominant
PGnd
Overvoltage
Comparator
MTW14N50E
5.0 V Off
0 V On
10
13
R5
1.3 M
R2
820 k
Frequency
Clamp
Low
Load Detect
FC
9
1.08 x V
ref
LEB
6
Quickstart
Leading Edge
Blanking
CS
Mult
5
R7
0.1
5.0 V
Reference
Multiplier
C2
0.01
R3
10 k
V
CC
4
Comp
1
V
3
FB
ref
V
ref
C1
22
C6
0.1
10 k
R1
10 k
1.0 k
2N3904
1.0 k
Figure 18. On/Off Control
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MC33368
1N5406
D4
C5
1.0
D2
D1
92 to
270
Vac
EMI
Filter
D3
16 Line
V
ref
V
ref
MC33368
R8
1.0 M
R13
51
15 V
1N4744
V
D6
CC
D8
RD
1N4934
UVLO
Q
Timer
R
12
C9
330 µF
2
C4
100
Zero
Current
Detect
AGnd
13/8.0
7
8
15 V
R Latch
S
T
ZCD
1.5 V
R4
22 k
1.2/1.0
R
1.5 V
R
S
MUR460
D5
Gate
11
S
Q1
Q
S
C3
330
400 V
R11
10
Set Dominant
Overvoltage
Comparator
PGnd
10
MTW20N50E
V
ref
R5
1.3 M
R2
820 k
R10
10 k
Low
Load Detect
13
Frequency
Clamp
1.08 x V
ref
C7
470 pF
FC
9
Quickstart
LEB
6
R9
10
Leading Edge
Blanking
CS
C8
Mult
5
R7
0.1
0.001
5.0 V
Reference
Multiplier
C2
0.01
R3
10.5 k
4
Comp
1
V
ref
3
FB
V
ref
C1
1.0
C6
0.1
R1
10 k
Figure 19. 400 W Power Factor Controller
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MC33368
D3
AC Input
DC Output
D7
C6
R8
D1
R3
C2
R5
C5
R1
R2
R6
C1
IC1
D2
R7
D4
C4
R4
D6
C9
C8
J
C7
J
R13
R10
J
R11
Transformer
J
R9
C3
D8
Q1
S
D
G
D5
J = Jumper
(Top View)
4.5″
MC33368
3.0″
(Bottom View)
Figure 20. Printed Circuit Board and Component Layout
(Circuits of Figures 15 and 16)
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15
MC33368
PACKAGE DIMENSIONS
DIP–16
P SUFFIX
CASE 648–08
ISSUE R
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
–T–
0.040
0.70
G
H
J
K
L
M
S
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
H
J
0.21
0.38
3.30
7.74
10
G
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
D 16 PL
M
M
0
0.25 (0.010)
T A
0.51
1.01
SO–16
D SUFFIX
CASE 751K–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
–B–
P
F
1
8
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.368
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
C
G
J
K
M
P
1.27 BSC
0.050 BSC
SEATING
PLANE
–T–
0.19
0.10
0
0.25 0.008
0.25 0.004
7
0.009
0.009
7
14 X D
J
K
0
M
S
S
0.25 (0.010)
T A
B
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
R
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MC33368
Notes
http://onsemi.com
17
MC33368
Notes
http://onsemi.com
18
MC33368
Notes
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19
MC33368
GreenLine is a trademark of Motorola, Inc.
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MC33368/D
相关型号：
MC33369TV
Switching Regulator, Voltage-mode, 0.5A, 115kHz Switching Freq-Max, CMOS, PZFM5, TO-220, 5 PIN
MOTOROLA
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