MC34023_05 [ONSEMI]
High Speed Single−Ended PWM Controller; 高速单端PWM控制器
| 型号： | MC34023_05 |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Single−Ended PWM Controller |
| 文件： | 总18页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC34023, MC33023
High Speed Single−Ended
PWM Controller
The MC34023 series are high speed, fixed frequency, single−ended
pulse width modulator controllers optimized for high frequency
operation. They are specifically designed for Off−Line and
DC−to−DC converter applications offering the designer a
cost−effective solution with minimal external components. These
integrated circuits feature an oscillator, a temperature compensated
reference, a wide bandwidth error amplifier, a high speed current
sensing comparator, and a high current totem pole output ideally
suited for driving a power MOSFET.
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PDIP−16
P SUFFIX
CASE 648
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, and a latch for single pulse metering.
16
1
The flexibility of this series allows it to be easily configured for
either current mode or voltage mode control.
SOIC−16W
DW SUFFIX
CASE 751G
16
Features
1
• 50 ns Propagation Delay to Output
• High Current Totem Pole Output
• Wide Bandwidth Error Amplifier
MARKING DIAGRAMS
• Fully−Latched Logic with Double Pulse Suppression
• Latching PWM for Cycle−By−Cycle Current Limiting
• Soft−Start Control with Latched Overcurrent Reset
• Input Undervoltage Lockout with Hysteresis
• Low Startup Current (500 mA Typ)
16
16
MC34023P
AWLYYWWG
MC33023DW
AWLYYWWG
1
1
• Internally Trimmed Reference with Undervoltage Lockout
• 90% Maximum Duty Cycle (Externally Adjustable)
• Precision Trimmed Oscillator
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
= Year
= Work Week
= Pb−Free Package
• Voltage or Current Mode Operation to 1.0 MHz
• Functionally Similar to the UC3823
• Pb−Free Packages are Available*
PIN CONNECTIONS
Error Amp
16
4
15
1
2
16 V
ref
5.1V
Reference
Inverting Input
Error Amp
Noninverting Input
V
ref
V
15
V
CC
CC
Clock
14 Output
13
3
4
5
6
Error Amp Output
5
6
UVLO
R
T
V
Clock
C
Oscillator
C
T
12 Power Ground
R
T
13
14
12
Current Limit
11
Reference
V
C
C
T
7
3
Ramp
Ground
10
9
Ramp
7
8
Output
Error Amp
Output
Noninverting
Input
Latching
PWM
Current Limit/
Shutdown
Power
Ground
Soft−Start
Error
Amp
2
(Top View)
Inverting
Input
11
9
1
8
Current
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Limit Ref
Current
Limit/
Soft−Start
Soft−Start
Shutdown
Ground
10
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
This device contains 176 active transistors.
Figure 1. Simplified Application
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
October, 2005 − Rev. 6
MC34023/D
MC34023, MC33023
ORDERING INFORMATION
Device
†
Package
Shipping
MC33023DW
SOIC−16W
47 Units / Rail
47 Units / Rail
MC33023DWG
SOIC−16W
(Pb−Free)
MC33023DWR2
SOIC−16W
1000 Units / Reel
1000 Units / Reel
MC33023DWR2G
SOIC−16W
(Pb−Free)
MC34023P
PDIP−16
25 Units / Rail
25 Units / Rail
MC34023PG
PDIP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
Rating
Symbol
Value
30
Unit
V
Power Supply Voltage
V
CC
Output Driver Supply Voltage
V
20
V
C
Output Current, Source or Sink (Note 1)
I
A
O
DC
0.5
2.0
Pulsed (0.5 ms)
Current Sense, Soft−Start, Ramp, and Error Amp Inputs
Error Amp Output and Soft−Start Sink Current
V
−0.3 to +7.0
V
in
I
10
mA
mA
O
Clock and R Output Current
I
5.0
T
CO
Power Dissipation and Thermal Characteristics
SO−16L Package (Case 751G)
Maximum Power Dissipation @ T = +25°C
Thermal Resistance, Junction−to−Air
DIP Package (Case 648)
P
862
145
mW
°C/W
A
D
R
q
JA
1.25
100
W
°C/W
Maximum Power Dissipation @ T = +25°C
P
A
D
Thermal Resistance, Junction−to−Air
R
q
JA
Operating Junction Temperature
T
+150
°C
°C
J
Operating Ambient Temperature (Note 2)
MC34023
MC33023
T
A
0 to +70
−40 to +105
Storage Temperature Range
T
stg
−55 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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2
MC34023, MC33023
ELECTRICAL CHARACTERISTICS (V = 15 V, R = 3.65 kW, C = 1.0 nF, for typical values T = +25°C, for min/max values T
CC
T
T
A
A
is the operating ambient temperature range that applies [Note 2], unless otherwise noted.)
Characteristic Symbol
Min
Typ
Max
Unit
REFERENCE SECTION
Reference Output Voltage (I = 1.0 mA, T = +25°C)
V
ref
5.05
−
5.1
2.0
2.0
0.2
−
5.15
15
V
mV
mV
mV/°C
V
O
J
Line Regulation (V = 10 V to 30 V)
Reg
line
CC
Load Regulation (I = 1.0 mA to 10 mA)
Reg
T
−
15
O
load
Temperature Stability
−
−
S
Total Output Variation over Line, Load, and Temperature
V
ref
4.95
−
5.25
−
Output Noise Voltage (f = 10 Hz to 10 kHz, T = +25°C)
V
50
mV
J
n
Long Term Stability (T = +125°C for 1000 Hours)
S
−
5.0
− 65
−
mV
mA
A
Output Short Circuit Current
OSCILLATOR SECTION
Frequency
I
− 30
−100
SC
kHz
T = +25°C
f
380
370
400
400
420
430
J
osc
Line (V = 10 V to 30 V) and Temperature (T = T
to T
)
high
CC
A
low
Frequency Change with Voltage (V = 10 V to 30 V)
Df /DV
−
−
0.2
2.0
2.8
1.0
1.0
−
%
%
V
CC
osc
Frequency Change with Temperature (T = T
to T
)
Df /DT
osc
A
low
high
Sawtooth Peak Voltage
Sawtooth Valley Voltage
V
V
2.6
0.7
3.0
1.25
OSC(P)
OSC(V)
V
Clock Output Voltage
High State
Low State
V
V
V
3.9
−
4.5
2.3
−
2.9
OH
OL
ERROR AMPLIFIER SECTION
Input Offset Voltage
V
−
−
−
15
3.0
1.0
−
mV
mA
IO
Input Bias Current
I
0.6
0.1
95
IB
Input Offset Current
I
−
mA
IO
Open−Loop Voltage Gain (V = 1.0 V to 4.0 V)
A
VOL
60
4.0
75
85
dB
O
Gain Bandwidth Product (T = +25°C)
GBW
CMRR
PSRR
8.3
95
−
MHz
dB
J
Common Mode Rejection Ratio (V
= 1.5 V to 5.5 V)
−
CM
Power Supply Rejection Ratio (V = 10 V to 30 V)
110
−
dB
CC
Output Current, Source (V = 4.0 V)
I
0.5
1.0
3.0
3.6
−
−
mA
O
Source
I
Sink
Output Current, Sink (V = 1.0 V)
O
Output Voltage Swing, High State (I = −0.5 mA)
V
V
OL
4.5
0
4.75
0.4
5.0
1.0
V
O
OH
Output Voltage Swing, Low State (I = 1 mA)
O
Slew Rate
SR
6.0
12
−
V/ms
PWM COMPARATOR SECTION
Ramp Input Bias Current
I
−
−0.5
−5.0
mA
IB
Duty Cycle, Maximum
Duty Cycle, Minimum
DC
DC
80
−
90
−
−
0
%
(max)
(min)
Zero Duty Cycle Threshold Voltage Pin 3(4) (Pin 7(9) = 0 V)
V
1.1
−
1.25
60
1.4
V
th
PLH(in/out)
Propagation Delay (Ramp Input to Output, T = +25°C)
t
100
ns
J
SOFT−START SECTION
Charge Current (V
= 0.5 V)
I
3.0
1.0
9.0
4.0
20
−
mA
Soft−Start
chg
Discharge Current (V
= 1.5 V)
I
mA
Soft−Start
dischg
1. Maximum package power dissipation limits must be observed.
2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
= 0°C for MC34023
= −40°C for MC33023
T
= +70°C for MC34023
= +105°C for MC33023
low
high
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3
MC34023, MC33023
ELECTRICAL CHARACTERISTICS (V = 15 V, R = 3.65 kW, C = 1.0 nF, for typical values T = +25°C, for min/max values T
CC
T
T
A
A
is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)
Characteristic Symbol
Min
Typ
Max
Unit
CURRENT SENSE SECTION
Input Bias Current (Pin 9(12) = 0 V to 4.0 V)
I
−
−
−
−
15
45
mA
mV
V
IB
Current Limit Comparator Input Offset Voltage (Pin 11(14) = 1.1 V)
V
IO
Current Limit Reference Input Common Mode Range (Pin 11(14)) T = +25°C
V
1.0
1.25
−
−
3.0
1.55
80
J
CMR
Shutdown Comparator Threshold
V
1.40
50
V
th
PLH(in/out)
Propagation Delay (Current Limit/Shutdown to Output, T = +25°C)
t
ns
J
OUTPUT SECTION
Output Voltage
V
Low State (I
= 20 mA)
= 200 mA)
V
−
−
13
12
0.25
1.2
13.5
13
0.4
2.2
−
Sink
OL
(I
High State (I
(I
Sink
= 20 mA)
= 200 mA)
V
Source
Source
OH
−
Output Voltage with UVLO Activated (V = 6.0 V, I
= 0.5 mA)
V
−
−
−
−
0.25
100
30
1.0
500
60
V
CC
Sink
OL(UVLO)
Output Leakage Current (V = 20 V)
I
mA
ns
ns
C
L
Output Voltage Rise Time (C = 1.0 nF, T = +25°C)
t
L
J
r
f
Output Voltage Fall Time (C = 1.0 nF, T = +25°C)
t
30
60
L
J
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (V Increasing)
V
8.8
0.4
9.2
0.8
9.6
1.2
V
V
CC
th(on)
UVLO Hysteresis Voltage (V Decreasing After Turn−On)
V
H
CC
TOTAL DEVICE
Power Supply Current
Startup (VCC = 8.0 V)
Operating
I
mA
CC
−
−
0.5
20
1.2
30
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
= 0°C for MC34023
= −40°C for MC33023
T
= +70°C for MC34023
= +105°C for MC33023
low
high
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4
MC34023, MC33023
100 k
1200
R = 1.2 k
T
C = 1.0 nF
V
= 15 V
CC
9
1
3
5
7
T = +25°C
A
1.0 MHz
T
1000
800
2
4
6
8
CT =
1. 100 nF
2. 47 nF
3. 22 nF
4. 10 nF
5. 4.7 nF
6. 2.2 nF
7. 1.0 nF
8. 470 pF
9. 220 pF
10 k
V
= 15 V
CC
600
R = 3.6 k
T
C = 1.0 nF
400 kHz
50 kHz
T
400
200
0
R = 36 k
T
C = 1.0 nF
1.0 k
470
T
4
5
6
7
100
1000
f
10
10
10
10
−ꢀ55
−ꢀ25
0
25
50
75
100
125
, OSCILLATOR FREQUENCY (Hz)
T , AMBIENT TEMPERATURE (°C)
osc
A
Figure 2. Timing Resistor versus
Oscillator Frequency
Figure 3. Oscillator Frequency
versus Temperature
120
100
80
0
1.30
1.28
1.26
1.24
V
= 15 V
Pin 7(9) = 0 V
45
CC
Gain
60
Phase
40
90
20
1.22
1.20
135
0
−ꢀ20
10
100
1.0 k
10 k
100 k
1.0 M
10 M
−ꢀ55
−ꢀ25
0
25
50
75
100
125
f, FREQUENCY (Hz)
T , AMBIENT TEMPERATURE (°C)
A
Figure 4. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 5. PWM Comparator Zero Duty Cycle
Threshold Voltage versus Temperature
3.0 V
2.5 V
2.0 V
2.55 V
2.5 V
2.45 V
0.1 ms/DIV
0.1 ms/DIV
Figure 6. Error Amp Small Signal
Transient Response
Figure 7. Error Amp Large Signal
Transient Response
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5
MC34023, MC33023
0
66
V
= 15 V
−ꢀ5.0
CC
65.6
65.2
64.8
64.4
64
T = −ꢀ55°C
A
V
= 15 V
CC
−ꢀ10
−ꢀ15
T = +25°C
A
T = +125°C
A
−ꢀ20
−ꢀ25
−ꢀ30
10
20 30
, SOURCE CURRENT (mA)
40
50
−ꢀ55
−ꢀ25
0
25
50
75
100
125
0
I
T , AMBIENT TEMPERATURE (°C)
Source
A
Figure 8. Reference Voltage Change
versus Source Current
Figure 9. Reference Short Circuit Current
versus Temperature
V
ref
LINE REGULATION 10 V to 24 V
(2.0 ms/DIV)
V
ref
LOAD REGULATION 1.0 mA to 10 mA
(2.0 ms/DIV)
Figure 10. Reference Line Regulation
Figure 11. Reference Load Regulation
100
60
1.50
1.46
V
= 15 V
CC
V
= 15 V
Pin 11(14) = 1.1 V
CC
20
1.42
1.38
−ꢀ20
−ꢀ60
1.34
1.30
−ꢀ100
−ꢀ55
−ꢀ25
0
25
50
75
100
125
−ꢀ55
−ꢀ25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 12. Current Limit Comparator Input
Offset Voltage versus Temperature
Figure 13. Shutdown Comparator Threshold
Voltage versus Temperature
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6
MC34023, MC33023
0
10
9.5
9.0
Source Saturation
(Load to Ground)
V
= 15 V
V
CC
CC
−ꢀ1.0
V
= 15 V
80 ms Pulsed Load
CC
120 Hz Rate
T = 25°C
−ꢀ2.0
A
8.5
8.0
7.5
7.0
2.0
1.0
0
Sink Saturation
(Load to V
Ground
)
CC
−ꢀ55
−ꢀ25
0
25
50
75
100
125
0
0.2
0.4
0.6
0.8
1.0
T , AMBIENT TEMPERATURE (°C)
A
I , OUTPUT LOAD CURRENT (A)
O
Figure 14. Soft−Start Charge Current
versus Temperature
Figure 15. Output Saturation Voltage
versus Load Current
OUTPUT RISE & FALL TIME 1.0 nF LOAD
50 ns/DIV
OUTPUT RISE & FALL TIME 10 nF LOAD
50 ns/DIV
Figure 16. Drive Output Rise and Fall Time
Figure 17. Drive Output Rise and Fall Time
30
R = 3.65 kW
T
C = 1.0 nF
25
20
15
10
5.0
0
T
V
Increasing
CC
V
Decreasing
CC
0
4.0
8.0
12
16
20
V
, SUPPLY VOLTAGE (V)
CC
Figure 18. Supply Voltage versus Supply Current
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7
MC34023, MC33023
V
in
V
CC
16
15
Reference
Regulator
V
ref
V
CC
V
CC
UVLO
4
5
Clock
9.2 V
13
V
ref
UVLO
4.2 V
V
Oscillator
C
R
T
14
6
7
C
T
Output
12
R
PWM
Comparator
Q
Power Ground
1.25 V
Ramp
S
PWM Latch
Error Amp Output
3
2
Current
Limit
Error
Amp
+
11
Noninverting Input
Inverting Input
Current Limit Reference
9.0 mA
1
8
9
Current Limit/Shutdown
Soft−Start
0.5 V
Soft−Start Latch
R
1.4 V
C
SS
Q
S
Shutdown
10
Ground
Figure 19. Representative Block Diagram
C
T
Clock
Soft−Start
Error Amp
Output Ramp
PWM
Comparator
Output
Figure 20. Current Limit Operating Waveforms
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8
MC34023, MC33023
OPERATING DESCRIPTION
The MC33023 and MC34023 series are high speed, fixed
output of the error amplifier to less than its normal output
voltage, thus limiting the duty cycle. The time it takes for a
capacitor to reach full charge is given by:
frequency, single−ended pulse width modulator controllers
optimized for high frequency operation. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost effective
5
t [ (4.5 • 10 ) C
Soft-Start
A Soft−Start latch is incorporated to prevent erratic
operation of this circuitry. Two conditions can cause the
Soft−Start circuit to latch so that the Soft−Start capacitor
stays discharged. The first condition is activation of an
solution with minimal external components.
representative block diagram is shown in Figure 19.
A
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components R and C . The R pin
undervoltage lockout of either V or V . The second
CC
ref
T
T
T
condition is when current sense input exceeds 1.4 V. Since
this latch is “set dominant”, it cannot be reset until either of
is set to a temperature compensated 3.0 V. By selecting the
value of R , the charge current is set through a current mirror
T
these signals is removed and, the voltage at C
than 0.5 V.
is less
Soft−Start
for the timing capacitor C . This charge current runs
T
continuously through C . The discharge current is ratioed to
T
PWM Comparator and Latch
be 10 times the charge current, which yields the maximum
A PWM circuit typically compares an error voltage with
a ramp signal. The outcome of this comparison determines
the state of the output. In voltage mode operation the ramp
signal is the voltage ramp of the timing capacitor. In current
mode operation the ramp signal is the voltage ramp induced
in a current sensing element. The ramp input of the PWM
comparator is pinned out so that the user can decide which
mode of operation best suits the application requirements.
The ramp input has a 1.25 V offset such that whenever the
voltage at this pin exceeds the error amplifier output voltage
minus 1.25 V, the PWM comparator will cause the PWM
latch to set, disabling the outputs. Once the PWM latch is set,
only a blanking pulse by the oscillator can reset it, thus
initiating the next cycle.
duty cycle of 90%. C is charged to 2.8 V and discharged to
T
1.0 V. During the discharge of C , the oscillator generates an
T
internal blanking pulse that resets the PWM Latch and,
inhibits the outputs. The threshold voltage on the oscillator
comparator is trimmed to guarantee an oscillator accuracy
of 5.0% at 25°C.
Additional dead time can be added by externally
increasing the charge current to C as shown in Figure 24.
T
This changes the charge to discharge ratio of C which is set
T
internally to I
ratio will be:
/10 I
. The new charge to discharge
charge
charge
I
) I
l
additiona
10 (I
charge
)
% Deadtime +
charge
A bidirectional clock pin is provided for synchronization
or for master/slave operation. As a master, the clock pin
Current Limiting and Shutdown
A pin is provided to perform current limiting and
shutdown operations. Two comparators are connected to the
input of this pin. The reference voltage for the current limit
comparator is not set internally. A pin is provided so the user
can set the voltage. When the voltage at the current limit
input pin exceeds the externally set voltage, the PWM latch
is set, disabling the output. In this way cycle−by−cycle
current limiting is accomplished. If a current limit resistor is
used in series with the power devices, the value of the
resistor is found by:
provides a positive output pulse during the discharge of C .
T
As a slave, the clock pin is an input that resets the PWM latch
and blanks the drive output, but does not discharge C .
T
Therefore, the oscillator is not synchronized by driving the
clock pin alone. Figures 28, 29 and 30 provide suggested
synchronization.
Error Amplifier
A fully compensated Error Amplifier is provided. It
features a typical DC voltage gain of 95 dB and a gain
bandwidth product of 8.3 MHz with 75 degrees of phase
margin (Figure 4). Typical application circuits will have the
noninverting input tied to the reference. The inverting input
will typically be connected to a feedback voltage generated
from the output of the switching power supply. Both inputs
I
Limit Reference Voltage
R
+
Sense
I
pk (switch)
If the voltage at this pin exceeds 1.4 V, the second
comparator is activated. This comparator sets a latch which,
in turn, causes the soft start capacitor to be discharged. In this
way a “hiccup” mode of recovery is possible in the case of
output short circuits. If a current limit resistor is used in
series with the output devices, the peak current at which the
controller will enter a “hiccup” mode is given by:
have a common mode voltage (V ) input range of 1.5 V to
CM
5.5 V. The Error Amplifier Output is provided for external
loop compensation.
Soft−Start Latch
Soft−Start is accomplished in conjunction with an
external capacitor. The Soft−Start capacitor is charged by an
internal 9.0 mA current source. This capacitor clamps the
1.4 V
R
I
+
shutdown
Sense
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9
MC34023, MC33023
In certain applications, it may be desirable to disable the
specific part in question. The PC board lead lengths must be
less than 0.5 inches for effective bypassing for snubbing.
current limit comparator. This can be accomplished by
biasing pin 11 to a level greater than 1.4 V but less than 3.0 V.
Under these conditions, the shutdown comparator and
soft−start latch are activated during an overcurrent event
causing the converter to enter an hiccup mode.
Instabilities
In current mode control, an instability can be encountered
at any given duty cycle. The instability is caused by the
current feedback loop. It has been shown that the instability
is caused by a double pole at half the switching frequency.
Undervoltage Lockout
There are two undervoltage lockout circuits within the IC.
If an external ramp (S ) is added to the on−time ramp (S )
e
n
The first senses V and the second V . During power−up,
of the current−sense waveform, stability can be achieved.
One must be careful not to add too much ramp
compensation. If too much is added the system will start to
perform like a voltage mode regulator. All benefits of
current mode control will be lost. Figure 26 is an example of
one way in which external ramp compensation can be
implemented.
CC
ref
V
CC
must exceed 9.2 V and V must exceed 4.2 V before
ref
the outputs can be enabled and the Soft−Start latch released.
If V falls below 8.4 V or V falls below 3.6 V, the outputs
CC
ref
are disabled and the Soft−Start latch is activated. When the
UVLO is active, the part is in a low current standby mode
allowing the IC to have an off−line bootstrap startup circuit.
Typical startup current is 500 mA.
Ramp Compensation
Output
Ramp Input
The MC34023 has a high current totem pole output
specifically designed for direct drive of power MOSFETs.
It is capable of up to 2.0 A peak drive current with a typical
rise and fall time of 30 ns driving a 1.0 nF load.
Separate pins for V and Power Ground are provided.
With proper implementation, a significant reduction of
switching transient noise imposed on the control circuitry is
1.25 V
Ramp
Compensation S
e
Current
Signal S
C
n
Figure 21. Ramp Compensation
possible. The separate V supply input also allows the
C
designer added flexibility in tailoring the drive voltage
A simple equation can be used to calculate the amount of
external ramp slope necessary to add that will achieve
stability in the current loop. For the following equations, the
calculated values for the application circuit in Figure 35 are
also shown.
independent of V
.
CC
Reference
A 5.1 V bandgap reference is pinned out and is trimmed
to an initial accuracy of 1.0% at 25°C. This reference has
short circuit protection and can source in excess of 10 mA
for powering additional control system circuitry.
V
N
O
L
S
S
+
ǒ Ǔ(R )Ai
e
S
N
P
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. With high
frequency, high power, switching power supplies it is
imperative to have separate current loops for the signal paths
and for the power paths. The printed circuit layout should
contain a ground plane with low current signal and high
current switch and output grounds returning on separate
paths back to the input filter capacitor. Shown in Figure 36
is a printed circuit layout of the application circuit. Note how
the power and ground traces are run. All bypass capacitors
and snubbers should be connected as close as possible to the
where:
VO = DC output voltage
NP, NS = number of power transformer primary
= or secondary turns
Ai = gain of the current sense network
= (see Figures 24 and 25)
L = output inductor
RS = current sense resistance
5
2
8
ǒ Ǔ(
)(
0.3 0.55
)
S
+
For the application circuit:
e
1.8 μ
= 0.115 V/ms
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MC34023, MC33023
PIN FUNCTION DESCRIPTION
Pin
DIP/SOIC
1
Function
Description
Error Amp
This pin is usually used for feedback from the output of the power supply.
Inverting Input
2
3
Error Amp
Noninverting
Input
This pin is used to provide a reference in which an error signal can be produced on the output of the
error amp. Usually this is connected to V , however an external reference can also be used.
ref
Error Amp
Output
This pin is provided for compensating the error amp for poles and zeros encountered in the power
supply system, mostly the output LC filter.
4
5
6
7
Clock
This is a bidirectional pin used for synchronization.
R
T
C
T
The value of R sets the charge current through timing Capacitor, C .
T T
In conjunction with R , the timing Capacitor sets the switching frequency.
T
Ramp Input
For voltage mode operation this pin is connected to C . For current mode operation this pin is
T
connected through a filter to the current sensing element.
8
9
Soft−Start
A capacitor at this pin sets the Soft−Start time.
Current Limit/
Shutdown
This pin has two functions. First, it provides cycle−by−cycle current limiting. Second, if the current is
excessive, this pin will reinitiate a Soft−Start cycle.
10
11
Ground
This pin is the ground for the control circuitry.
Current Limit
This pin voltage sets the threshold for cycle−by−cycle current limiting.
Reference Input
12
13
Power Ground
This is a separate power ground return that is connected back to the power source. It is used to
reduce the effects of switching transient noise on the control circuitry.
V
This is a separate power source connection for the outputs that is connected back to the power source
input. With a separate power source connection, it can reduce the effects of switching transient noise
on the control circuitry.
C
14
15
16
Output
This is a high current totem pole output.
V
This pin is the positive supply of the control IC.
CC
V
ref
This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier.
4
5
4
5
Oscillator
Oscillator
6
C
T
6
7
C
T
From Current
Sense Element
1.25 V
1.25 V
7
3
1
3
1
Output Voltage
Feedback Input
Output Voltage
Feedback Input
2
V
ref
2
V
ref
In voltage mode operation, the control range on the output of the Error
Amplifier from 0% to 90% duty cycle is from 2.25 V to 4.05 V.
In current mode control, an RC filter should be placed at the ramp input
to filter the leading edge spike caused by turn−on of a power MOSFET.
Figure 22. Voltage Mode Operation
Figure 23. Current Mode Operation
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11
MC34023, MC33023
9
R
w
9
I
I
Sense
Sense
The addition of an RC filter will eliminate instability caused by the
leading edge spike on the current waveform. This sense signal can also
be used at the ramp input pin for current mode control. For ramp
compensation it is necessary to know the gain of the current feedback
loop. If a transformer is used, the gain can be calculated by:
The addition of an RC filter will eliminate instability caused by the
leading edge spike on the current waveform. This sense signal can also
be used at the ramp input pin for current mode control. For ramp
compensation it is necessary to know the gain of the current feedback
loop. The gain can be calculated by:
R
R
w
Sense
A +
A +
i
turns ratio
i
turns ratio
Figure 24. Resistive Current Sensing
Figure 25. Primary Side Current Sensing
4
5
6
Oscillator
C
C
T
1
1.25 V
R
1
Current Sense
Information
7
3
R
2
This method of slope compensation is easy to implement, however, it
is noise sensitive. Capacitor C provides AC coupling. The oscillator
1
signal is added to the current signal by a voltage divider consisting of
resistors R and R .
1
2
Figure 26A. Slope Compensation (Noise Sensitive)
Output
Current Sense
Transformer
Ramp
Input
R
w
R
Ramp
Input
M
1.25 V
7
3
R
1.25 V
f
7
Output
C
M
R
Current Sense
Resistor
M
C
f
R
f
C
C
M
f
3
When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor R and capacitor C provide the added
M
M
slope necessary. By choosing R and C with a larger time constant than the switching frequency, you can assume that its charge is linear. First choose C , then
M
M
M
R
M
can be adjusted to achieve the required slope. The diode provides a reset pulse at the ramp input at the end of every cycle. The charge current I can be calculated
M
by I = C S . Then R can be calculated by R = V /I
CC M.
M
M
e
M
M
Figure 26B. Slope Compensation (Noise Immune)
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MC34023, MC33023
5.0 V
0 V
4
5
6
Oscillator
R
T
C
T
V
ref
4
5
6
R
DT
Oscillator
R
T
C
T
The sync pulse fed into the clock pin must be at least 3.9 V. R and C
T
T
need to be set 10% slower than the sync frequency. This circuit is also
Additional dead time can be added by the addition of a dead time
used in Voltage Mode operation for master/slave operation. The clock
signal would be coming from the master which is set at the desired
operating frequency, while the slave is set 10% slower.
resistor from V
information.
to C . See text on Oscillator section for more
T
ref
Figure 27. Dead Time Addition
Figure 28. External Clock Synchronization
4
4
V
ref
5
6
5
6
Master
Oscillator
Slave
Oscillator
R
T
C
T
Figure 29. Current Mode Master/Slave Operation Over Short Distances
20
16
Reference
MMBT3906
MMBD0914
1.0 k
4.7 k
4
NC
4
2200
5
6
1.15 R
T
Slave
Oscillator
5
6
430
Master
Oscillator
MMBT3904
C
T
R
T
C
T
Figure 30. Synchronization Over Long Distances
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MC34023, MC33023
1
2
+
V
ref
I
B
8
R
R
+
0
−
1
V
in
V
C
C
SS
2
Base Charge
Removal
15
14
12
In voltage mode operation, the maximum duty cycle can be clamped. By
the addition of a PNP transistor to buffer the clamp voltage, the Soft−Start
current is not affected by R .
1
R
To Current
Sense Input
S
V
) 0.6
clamp
9.0 μA
The new equation for Soft−Start is t [
(C
)
SS
The totem pole output can furnish negative base current for enhanced
transistor turn−off, with the addition of the capacitor in series with the base.
In current mode operation, this circuit will limit the maximum voltage
allowed at the ramp input to end a cycle.
Figure 31. Buffered Maximum Clamp Level
Figure 32. Bipolar Transistor Drive
V
in
V
C
V
C
15
14
15
14
12
R
To Current
Sense Input
S
12
A series gate resistor may be needed to dampen high frequency parasitic
oscillation caused by the MOSFET’s input capacitance and any series
wiring inductance in the gate−source circuit. The series resistor will also
decrease the MOSFET switching speed. A Schottky diode can reduce
the driver’s power dissipation due to excessive ringing, by preventing the
output pin from being driven below ground. The Schottky diode also
prevents substrate injection when the output pin is driven below ground.
The totem pole output can easily drive pulse transformers. A Schottky
diode is recommended when driving inductive loads at high frequencies.
The diode can reduce the driver’s power dissipation due to excessive
ringing, by preventing the output pin from being driven below ground.
Figure 33. MOSFET Parasitic Oscillations
Figure 34. Isolated MOSFET Drive
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MC34023, MC33023
+
Figure 35. Application Circuit
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15
MC34023, MC33023
1500 pF
100 pF
4.0″
1N5819
1000 pF
0.01
0.01
1500 pF
6.5″
(Top View)
Figure 36. PC Board With Components
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16
MC34023, MC33023
(Top View)
4.0″
6.5″
(Bottom View)
Figure 37. PC Board Without Components
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MC34023, MC33023
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16W
DW SUFFIX
CASE 751G−03
ISSUE C
NOTES:
A
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
q
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
1
8
A
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
B
16X B
M
S
S
B
0.25
T A
0.25
0.50
0
0.75
0.90
7
_
_
SEATING
PLANE
14X
e
C
T
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC34023/D
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