MC44608P100 [ONSEMI]
SWITCHING CONTROLLER, 110kHz SWITCHING FREQ-MAX, PDIP8, PLASTIC, DIP-8;型号: | MC44608P100 |
厂家: | ONSEMI |
描述: | SWITCHING CONTROLLER, 110kHz SWITCHING FREQ-MAX, PDIP8, PLASTIC, DIP-8 开关 光电二极管 |
文件: | 总15页 (文件大小:266K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC44608
Few External Components
Reliable and Flexible
SMPS Controller
The MC44608 is a high performance voltage mode controller
designed for off--line converters. This high voltage circuit that
integrates the startup current source and the oscillator capacitor,
requires few external components while offering a high flexibility and
reliability.
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The device also features a very high efficiency standby management
consisting of an effective Pulsed Mode operation. This technique
enables the reduction of the standby power consumption to
approximately 1.0 W while delivering 300 mW in a 150 W SMPS.
8
1
General Features
PDIP--8
P SUFFIX
CASE 626
Integrated Startup Current Source
Lossless Off--Line Startup
Direct Off--Line Operation
Fast Startup
MARKING DIAGRAM
Flexibility
Duty Cycle Control
Undervoltage Lockout with Hysteresis
On Chip Oscillator Switching Frequency 40 or 75
Secondary Control with Few External Components
These are Pb--Free Devices*
8
MC44608Pxx
AWL
YYWWG
1
Protections
Maximum Duty Cycle Limitation
Cycle by Cycle Current Limitation
Demagnetization (Zero Current Detection) Protection
“Over VCC Protection” Against Open Loop
Programmable Low Inertia Over Voltage Protection
Against Open Loop
MC44608Pxx = Device Code
xx = 40 or 75
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
= Year
= Work Week
= Pb--Free Package
Internal Thermal Protection
PIN CONNECTIONS
SMPS Controller
Pulsed Mode Techniques for a Very High Efficiency
Low Power Mode
Lossless Startup
Demag
1
2
8
7
V
i
I
sense
Low dV/dT for Low EMI Radiations
Control Input
GND
3
4
6
5
V
CC
Driver
(Top View)
*For additional information on our Pb--Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
Seedetailedorderingandshippinginformationinthepackage
dimensions section on page 2 of this data sheet.
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
December, 2010 -- Rev. 10
MC44608/D
MC44608
Demag
Vi
1
8
DMG
+
--
UVLO2
Startup
Source
50 mV
/20 mV
9 mA
>24 mA
>120 mA
Latched off Phase
Startup Phase
Demag
Logic
V
CC
Management
6
Switching Phase
Latched off
Phase
V
CC
Output
OVP
UVLO1
UVLO2
Startup
2mS
Phase
Startup
Phase
Switching
Phase
&
200 mA
OUT Disable
DMG
1
0
OSC
S1
Buffer
5
4
Enable
Clock
&
Thermal
Shutdown
&
S
Standby
Management
OSC
&
Driver
GND
Standby
+
PWM
Latch
PWM
--
&
R
OC NOC
Output
Q
Leading Edge
Blanking
VPWM
+
2
Latched off Phase
Standby
CS
&
Isense
--
S2
S3
Regulation
Block
3
1 V
4 kHz Filter
Switching Phase
Control
Input
Figure 1. Representative Block Diagram
ORDERING INFORMATION
Device
Switching Frequency
Package
Shipping
MC44608P40G
PDIP--8
(Pb--Free)
50 Units / Rail
40 kHz
MC44608P75G
PDIP--8
(Pb--Free)
50 Units / Rail
75 kHz
MAXIMUM RATINGS
Rating
Symbol
Value
30
Unit
mA
V
Total Power Supply Current
I
CC
Output Supply Voltage with Respect to Ground
All Inputs except Vi
V
16
CC
V
inputs
--1.0 to +16
500
V
Line Voltage Absolute Rating
V
i
V
Recommended Line Voltage Operating Condition
Power Dissipation and Thermal Characteristics
V
i
400
V
Maximum Power Dissipation at T = 85C
Thermal Resistance, Junction--to--Air
P
600
100
mW
C/W
A
D
R
θ
JA
Operating Junction Temperature
T
150
C
C
J
Operating Ambient Temperature
T
A
-- 2 5 t o + 8 5
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC44608
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUT SECTION
Output Resistor
Ω
Sink Resistance
R
5.0
--
8.5
15
50
50
15
--
OL
Source Resistance
R
OH
Output Voltage Rise Time (from 3.0 V up to 9.0 V) (Note 1)
t
--
--
ns
ns
r
Output Voltage Falling Edge Slew--Rate (from 9.0 V down to 3.0 V) (Note 1)
t
--
--
f
CONTROL INPUT SECTION
Duty Cycle @ I
Duty Cycle @ I
= 2.5 mA
= 1.0 mA
d
d
--
--
2.0
48
%
%
V
pin3
pin3
2mA
1mA
36
43
Control Input Clamp Voltage (Switching Phase) @ I
Latched Phase Control Input Voltage (Standby) @ I
Latched Phase Control Input Voltage (Standby) @ I
current sense section
= --1.0 mA
= +500 mA
= +1.0 mA
4.75
3.4
2.4
5.0
3.9
3.0
5.25
4.3
3.7
pin3
pin3
pin3
V
V
V
LP--stby
LP--stby
V
Maximum Current Sense Input Threshold
Input Bias Current
V
0.95
-- 1 . 8
180
180
--
1.0
--
1.05
1.8
220
220
--
V
CS--th
I
mA
mA
mA
ns
ns
ns
ns
ns
B--cs
Standby Current Sense Input Current
Startup Phase Current Sense Input Current
I
200
200
220
480
250
680
470
CS--stby
CS--stup
I
Propagation Delay (Current Sense Input to Output @ V T MOS = 3.0 V)
T
PLH(In/Out)
TH
Leading Edge Blanking Duration
MC44608P40
MC44608P75
MC44608P40
MC44608P75
T
T
T
T
--
--
LEB
LEB
DLY
DLY
Leading Edge Blanking Duration
--
--
Leading Edge Blanking + Propagation Delay
Leading Edge Blanking + Propagation Delay
oscillator section
500
370
900
570
Normal Operation Frequency MC44608P40
Normal Operation Frequency MC44608P75
f
f
36
68
78
40
75
82
44
82
86
kHz
kHz
%
osc
osc
max
Maximum Duty Cycle @ f = f
OVERvoltage section
d
osc
Quick OVP Input Filtering (R
= 100 kΩ)
T
--
250
2.0
120
15.3
--
--
--
ns
ms
mA
V
demag
filt
Propagation Delay (I
> I
to output low)
ovp
T
--
demag
PHL(In/Out)
Quick OVP Current Threshold
Protection Threshold Level on V
I
105
14.8
1.0
140
15.8
--
OVP
V
CC
CC--OVP
Minimum Gap Between V
and V
V
-- V
stup
V
CC--OVP
stup--th
CC--OVP
1. This parameter is measured using 1.0 nF connected between the output and the ground.
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3
MC44608
ELECTRICAL CHARACTERISTICS (V = 12 V, for typical values T = 25C, for min/max values T = --25C to +85C unless
CC
A
A
otherwise noted) (Note 2)
Characteristic
DEMAGNETIZATION DETECTION section (note 3)
Demag Comparator Threshold (V increasing)
Symbol
Min
Typ
Max
Unit
V
30
--
50
30
69
--
mV
mV
ns
mA
V
pin1
dmg--th
Demag Comparator Hysteresis (Note 4)
H
dmg
PHL(In/Out)
Propagation Delay (Input to Output, Low to High)
t
--
300
--
--
Input Bias Current (V
= 50 mV)
I
-- 0 . 6
-- 0 . 9
2.05
1.4
--
demag
dem--lb
Negative Clamp Level (I
= --1.0 mA)
V
-- 0 . 7
2.3
1.7
-- 0 . 4
2.8
1.9
demag
cl--neg--dem
Positive Clamp Level @ I
Positive Clamp Level @ I
= 125 mA
= 25 mA
V
V
demag
demag
cl--pos--dem--H
V
V
cl--pos--dem--L
OVERTEMPERATURE section
Trip Level Over Temperature
Hysteresis
T
T
--
--
160
30
--
--
C
C
high
hyst
STANDBY MAXIMUM CURRENT REDUCTION section
Normal Mode Recovery Demag Pin Current Threshold
I
20
25
30
mA
dem--NM
K FACTORS SECTION FOR PULSED MODE OPERATION
I
I
I
/ I
MC44608P40
MC44608P75
10 x K1
10 x K1
2.4
2.8
46
1.8
90
175
3.0
--
2.9
3.3
3.8
4.2
63
--
--
CCS stup
/ I
CCS stup
3
/ I
10 x K2
52
--
CCL stup
2
(V
-- UVLO2) / (V
-- UVLO1)
10 x K
2.2
2.6
150
225
5.5
--
--
stup
stup
sstup
2
(UVLO1 -- UVLO2) / (V
-- UVLO1)
10 x K
120
198
4.7
--
stup
sl
6
I
/ V
10 x Y
--
CS
csth
cstby
Demag ratio I
/ I
NM
Dmgr
R3
--
ovp dem
(V3
-- V 3
) / (1.0 mA -- 0.5 mA)
0.5 mA
1800
4.8
Ω
V
1.0 mA
V
Latchoff
V3
--
--
control
SUPPLY SECTION
Minimum Startup Voltage
Startup Voltage
V
--
12.5
9.5
--
--
50
13.8
10.5
--
V
V
ilow
V
V
13.1
10
CC
stup--th
Output Disabling V Voltage After Turn On
V
V
CC
uvlo1
stup--uvlo1
Hysteresis (V
-- V
)
H
3.1
6.6
3.4
9.5
V
stup--th
uvlo1
V
Undervoltage Lockout Voltage
V
6.2
--
7.0
--
V
CC
uvlo2
uvlo1--uvlo2
Hysteresis (V
-- V
)
H
V
uvlo1
uvlo2
Absolute Normal Condition V Start Current @ (V = 100 V) and
-- ( I
)
7.0
12.8
mA
CC
i
CC
(V = 9.0 V)
CC
Switching Phase Supply Current (no load)
MC44608P40
MC44608P75
I
2.0
2.4
2.6
3.2
3.6
4.0
mA
CCS
Latched Off Phase Supply Current
Hiccup Mode Duty Cycle (no load)
I
0.3
--
0.5
10
0.68
--
mA
%
CC--latch
δ
Hiccup
2. Adjust V above the startup threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction
CC
temperature as close to ambient as possible.
3. This function can be inhibited by connecting pin 1 to GND.
4. Guaranteed by design (non tested).
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4
MC44608
PIN FUNCTION DESCRIPTION
Description
Pin
Name
1
Demag
The Demag pin offers 3 different functions: Zero voltage crossing detection (50 mV), 24 mA current detection
and 120 mA current detection. The 24 mA level is used to detect the secondary reconfiguration status and the
120 mA level to detect an Over Voltage status called Quick OVP.
2
3
I
The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the power
sense
MOSFET. When I
reaches 1.0 V, the Driver output (pin 5) is disabled. This is known as the Over Current
sense
Protection function. A 200 mA current source is flowing out of the pin 3 during the startup phase and during the
switching phase in case of the Pulsed Mode of operation. A resistor can be inserted between the sense resistor
and the pin 2, thus a programmable peak current detection can be performed during the SMPS standby mode.
Control Input
A feedback current from the secondary side of the SMPS via the Opto--coupler is injected into this pin. A
resistor can be connected between this pin and GND to allow the programming of the Burst duty cycle during
the standby mode.
4
5
6
Ground
Driver
This pin is the ground of the primary side of the SMPS.
The current and slew rate capability of this pin are suited to drive Power MOSFETs.
V
This pin is the positive supply of the IC. The driver output gets disabled when the voltage becomes higher than
15 V and the operating range is between 6.6 V and 13 V. An intermediate voltage level of 10 V creates a
disabling condition called Latched Off phase.
CC
7
8
This pin is to provide isolation between the V pin 8 and the V pin 6.
i CC
V
i
This pin can be directly connected to a 500 V voltage source for startup function of the IC. During the startup
phase a 9.0 mA current source is internally delivered to the V pin 6 allowing a rapid charge of the V
CC
CC
capacitor. As soon as the IC starts--up, this current source is disabled.
OPERATING DESCRIPTION
Regulation
The switch S3 is closed in standby mode during the
Latched Off Phase while the switch S2 remains open. (See
section PULSED MODE DUTY CYCLE CONTROL).
The resistor Rdpulsed(Rdutycycle burst) hasno effecton
the regulation process. This resistor is used to determine the
burstdutycycledescribedinthechapter“PulsedDutyCycle
Control” on page 8.
V
LP--stby
V
CC
1
0
Stand--by
Latched off Phase
Control
Input
&
S3
3
1
S2
0
Switching Phase
PWM Latch
V
dd
The MC44608 works in voltage mode. The on--time is
controlled by the PWM comparator that compares the
oscillator sawtoothwiththe regulationblockoutput(referto
the block diagram on page 2).
The PWM latch is initialized by the oscillator and is reset
by the PWM comparator or by the current sense comparator
in case of an over current. This configuration ensures that
only a single pulse appears at the circuit output during an
oscillator cycle.
PWM
Regulation
20 Ω
Comparator
Output
5 V
4 kHz
Filter
1.6 V
Figure 2. Regulator
The pin 3 senses the feedback current provided by the
Opto coupler. During the switching phase the switch S2 is
closed and the shunt regulator is accessible by the pin 3. The
shunt regulator voltage is typically 5.0 V. The dynamic
resistance of the shunt regulator represented by the zener
diode is 20 Ω. The gain of the Control input is given on
Figure 11 which shows the duty cycle as a function of the
current injected into the pin 3.
Current Sense
The inductor current is converted to a positive voltage by
inserting a ground reference sense resistor RSense in series
with the power switch.
The maximum current sense threshold is fixed at 1.0 V.
The peak current is given by the following equation:
1
Ipk
=
(A)
max
R
(Ω)
sense
A 4.0 kHz filter network is inserted between the shunt
regulator and the PWM comparator to cancel the high
frequency residual noise.
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5
MC44608
Oscillator Buffer Output
In standby mode, this current can be lowered as due to the
activation of a 200 mA current source:
R
DMG
Q
1 − (R (kΩ) × 0, 2)
cs
Ipk
=
(A)
max−stby
R
(Ω)
S
sense
Demag
1
+
--
Switching Phase
&
DMG
&
50/20 mV
200 mA
STANDBY
STARTUP
Idemag
> 24 mA
>120 mA
1
0
Current Mirror
Overcurrent
Figure 4. Demagnetization Block
Comparator
L.E.B.
Isense
OC
+
--
2
This function can be inhibited by grounding it but in this
case, the quick and programmable OVP is also disabled.
Rcs
Rsense
1 V
Oscillator
The MC44608 contains a fixed frequency oscillator. It is
built around a fixed value capacitor CT successively
charged and discharged by two distinct current sources ICH
and IDCH. The window comparator senses the CT voltage
value and activates the sources when the voltage is reaching
the 2.4 V/4.0 V levels.
Figure 3. Current Sense
Thecurrentsenseinputconsistsofafilter(6.0 kΩ, 4.0 pF)
and of a leading edge blanking. Thanks to that, this pin is not
sensitive to the power switch turn on noise and spikes and
practically in most applications, no filtering network is
required to sense the current.
Finally, this pin is used:
ICH
-- as a protection against over currents (Isense > I)
-- as a reduction of the peak current during a Pulsed Mode
switching phase.
The overcurrent propagation delay is reduced by
producing a sharp output turn off (high slew rate). This
results in an abrupt output turn off in the event of an over
current and in the majority of the pulsed mode switching
sequence.
DMG
OSC
SCH
&
from Demag
logic block
Window
comp
4 V
+
--
Clock
2.4 V
SDCH
CT
IDCH
Demagnetization Section
The MC44608 demagnetization detection consists of a
comparator designed to compare the VCC winding voltage
to a reference that is typically equal to 50 mV.
Figure 5. Oscillator Block
This reference is chosen low to increase effectiveness of
the demagnetization detection even during startup.
A latch is incorporated to turn the demagnetization block
output into a low level as soon as a voltage less than 50 mV
is detected, and to keep it in this state until a new pulse is
generatedontheoutput. Thisavoidsanyringingontheinput
signal which may alter the demagnetization detection.
For a higher safety, the demagnetization block output is
also directly connected to the output, which is disabled
during the demagnetization phase.
The demagnetization pin is also used for the quick,
programmable OVP. In fact, the demagnetization input
currentissensedsothatthe circuitoutputislatchedoffwhen
this current is detected as higher than 120 mA.
The complete demagnetization status DMG is used to
inhibit the recharge of the CT capacitor. Thus in case of
incomplete transformer demagnetization the next switching
cycle is postpone until the DMG signal appears. The
oscillator remains at 2.4 V corresponding to the sawtooth
valley voltage. In this way the SMPS is working in the so
called SOPS mode (Self Oscillating Power Supply). In that
case the effective switching frequency is variable and no
longer depends on the oscillator timing but on the external
working conditions (Refer to DMG signal in the Figure 6).
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6
MC44608
OSC
4 V
V
CC
13 V
Vcont
2.4 V
10 V
Clock
6.5 V
DMG
Iprim
Startup
Phase
Latched off
Phase
Switching
Phase
Figure 7. Hiccup Mode
Figure 6.
Incase of the hiccupmode, the dutycycle of the switching
phase is in the range of 10%.
The OSC and Clock signals are provided according to the
Figure 6. The Clock signals correspond to the CT capacitor
discharge. The bottom curve represents the current flowing
in the sense resistor Rcs. It starts from zero and stops when
the sawtooth value is equal to the control voltage Vcont. In
this way the SMPS is regulated with a voltage mode control.
Mode Transition
TheLWlatchFigure8isthememoryoftheworkingstatus
at the end of every switching sequence.
Two different cases must be considered for the logic at the
termination of the SWITCHING PHASE:
1. No Over Current was observed
2. An Over Current was observed
Overvoltage Protection
The MC44608 offers two OVP functions:
-- a fixed function that detects when VCC is higher than
15.4 V
-- a programmable function that uses the demag pin. The
current flowing into the demag pin is mirrored and
compared to the reference current Iovp (120 mA). Thus this
OVP is quicker as it is not impacted by the VCC inertia and
is called QOVP.
These 2 cases are corresponding to the signal labelled
NOCincaseof“NoOverCurrent”and“OC”incaseofOver
Current. So the effective working status at the end of the ON
time memorized in LW corresponds to Q=1 for no over
current and Q=0 for over current.
This sequence is repeated during the Switching phase.
Several events can occur:
1. SMPS switch OFF
2. SMPS output overload
3. Transition from Normal to Pulsed Mode
4. Transition from Pulsed Mode to Normal Mode
In both cases, once an OVP condition is detected, the
output is latched off until a new circuit startup.
Startup Management
The Vi pin 8 is directly connected to the HV DC rail Vin.
This high voltage current source is internally connected to
theVCC pinandthusisusedtochargetheVCC capacitor.The
VCC capacitor charge period corresponds to the startup
phase. When the VCC voltage reaches 13 V, the high voltage
9.0 mA current source is disabled and the device starts
working. The device enters into the switching phase.
It is to be noticed that the maximum rating of the Vi pin 8
is 500 V. ESD protection circuitry is not currently added to
this pin due to size limitations and technology constraints.
Protection is limited by the drain--substrate junction in
avalanche breakdown. To help increase the application
safety against high voltage spike on that pin it is possible to
insert a small wattage 1.0 kΩ series resistor between the Vin
rail and pin 8.
The Figure 7 shows the VCC voltage evolution in case of
no external current source providing current into the VCC
pin during the switching phase. This case can be
encountered in SMPS when the self supply through an
auxiliary winding is not present (strong overload on the
SMPS output for example). The Figure 17 also depicts this
working configuration.
Latched Off
Phase
VPWM
OUT
NOC
OC
S
R
Q
Standby
&
&
S
Mode
R1
R2
&
&
Q
LW
S1
Switch
Q
LEB out
1 V
+
CS
--
I
Startup
Switching Startup
demag
Phase > 24 mA Phase Phase
Figure 8. Transition Logic
1. SMPS SWITCH OFF
When the mains is switched OFF, so long as the bulk
electrolithic bulk capacitor provides energy to the SMPS,
the controller remains in the switching phase. Then the peak
current reaches its maximum peak value, the switching
frequency decreases and all the secondary voltages are
reduced. The VCC voltage is also reduced. When VCC is
equal to 10 V, the SMPS stops working.
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MC44608
2. Overload
according to the equation of the current sense section,
page 5. The C.S. clamping level depends on the power to be
delivered to the load during the SMPS standby mode. Every
switchingsequence ON/OFF isterminatedbyanOC aslong
as the secondary Zener diode voltage has not been reached.
When the Zener voltage is reached the ON cycle is
terminatedbya true PWMaction. The proper SWITCHING
PHASE termination must correspond to a NOC condition.
The LW latch stores this NOC status.
The LATCHED OFF PHASE: The MODE latch is set.
The startup PHASE is similar to the Overload Mode. The
MODE latch remains in its set status (Q=1).
The SWITCHING PHASE: The standby signal is
validatedandthe 200 mAissourcedoutof the CurrentSense
pin 2.
In the hiccup mode the 3 distinct phases are described as
follows (refer to Figure 7):
The SWITCHING PHASE: The SMPS output is low and
the regulation block reacts by increasing the ON time (dmax
= 80%). The OC is reached at the end of every switching
cycle. The LW latch (Figure 8) is reset before the VPWM
signal appears. The SMPS output voltage is low. The VCC
voltage cannot be maintained at a normal level as the
auxiliary winding provides a voltage which is also reduced
in a ratio similar to the one on the output (i.e. Vout nominal
/ Vout short--circuit). Consequently the VCC voltage is
reduced at an operating rate given by the combination VCC
capacitor value together with the ICC working consumption
(3.2 mA) according to the equation 2. When VCC crosses
10V the WORKING PHASE gets terminated. The LW latch
remains in the reset status.
The LATCHED--OFF PHASE: The VCC capacitor
voltage continues to drop. When it reaches 6.5 V this phase
is terminated. Its duration is governed by equation 3.
ThestartupPHASEisreinitiated.Thehighvoltagestartup
current source (--ICC1 = 9.0 mA) is activated and the MODE
latch is reset. The VCC voltage ramps up according to the
equation 1. When it reaches 13 V, the IC enters into the
SWITCHING PHASE.
4. Transition from Standby to Normal
The secondary reconfiguration is removed. The
regulation on the low voltage secondary rail can no longer
beachieved, thusattheendof theSWITCHINGPHASE, no
PWM condition can be encountered. The LW latch is reset.
At the next WORKING PHASE a NORMAL mode status
takes place.
In order to become independent of the recovery time
constant on the secondary side of the SMPS an additional
resetinputR2isprovidedontheMODElatch. Thecondition
Idemag<24 mA corresponds to the activation of the
secondary reconfiguration status. The R2 reset insures a
direct return into the Normal Mode.
The NEXT SWITCHING PHASE: The high voltage
current source is inhibited, the MODE latch (Q=0) activates
the NORMAL mode of operation. Figure 3 shows that no
current is injected out pin 2. The over current sense level
corresponds to 1.0 V.
Pulsed Mode Duty Cycle Control
As long as the overload is present, this sequence repeats.
TheSWITCHINGPHASEdutycycleisintherangeof10%.
During the sleep mode of the SMPS the switch S3 is
closed and the control input pin 3 is connected to a 4.6 V
voltage source thru a 500 Ω resistor. The discharge rate of
the VCC capacitor is given by ICC--latch (device consumption
during the LATCHED OFF phase) in addition to the current
drawn out of the pin 3. Connecting a resistor between the
Pin 3 and GND (RDPULSED) a programmable current is
drawn from the VCC through pin 3. The duration of the
LATCHED OFF phase is impacted by the presence of the
resistor RDPULSED. The equation 3 shows the relation to the
pin 3 current.
3. Transition from Normal to Pulsed Mode
In this sequence the secondary side is reconfigured (refer
to the typical application schematic on page 13). The high
voltage output value becomes lower than the NORMAL
mode regulated value. The TL431 shunt regulator is fully
OFF. In the SMPS standby mode all the SMPS outputs are
lowered except for the low voltage output that supply the
wake--up circuit located at the isolated side of the power
supply. In that mode the secondary regulation is performed
by the zener diode connected in parallel to the TL431.
The secondary reconfiguration status can be detected on
the SMPS primary side by measuring the voltage level
present on the auxiliary winding Laux. (Refer to the
Demagnetization Section). In the reconfigured status, the
Laux voltage is also reduced. The VCC self--powering is no
longer possible thus the SMPS enters in a hiccup mode
similar to the one described under the Overload condition.
In the SMPS standby mode the 3 distinct phases are:
The SWITCHING PHASE: Similar to the Overload
mode. The current sense clamping level is reduced
Pulsed Mode Phases
Equations 1 through 8 define and predict the effective
behavior during the PULSED MODE operation. The
equations 6, 7, and 8 contain K, Y, and D factors. These
factors are combinations of measured parameters. They
appear in the parameter section “Kfactors for pulsed mode
operation” page 4. In equations 3 through 8 the pin 3 current
is the current defined in the above section “Pulsed Mode
Duty Cycle Control”.
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MC44608
EQUATION 1
Startup Phase Duration:
C
× (V
− UVLO2)
stup
Vcc
t
=
start–up
I
stup
where: Istup is the startup current flowing through VCC pin
Vcc is the VCC capacitor value
C
EQUATION 2
Switching Phase Duration:
C
× (V
− UVLO1)
+ I
stup
Vcc
t
=
switch
I
ccS
G
where: IccS is the no load circuit consumption in switching phase
G is the current consumed by the Power Switch
I
EQUATION 3
Latched--off Phase Duration:
C
× (UVLO1 − UVLO2)
Vcc
t
=
latched−off
I
+ I
ccL
pin3
where: IccL is the latched off phase consumption
Ipin3 is the current drawn from pin3 adding a resistor
EQUATION 4
Burst Mode Duty Cycle:
t
switch
d
=
BM
t
+ t
+ t
start−up
switch
latched−off
EQUATION 5
C
× (V
−UVLO1)
+ I
stup
Vcc
I
ccS
G
d
=
BM
C
×(V
− UVLO2)
C
× (V
−UVLO1)
C
× (UVLO1−UVLO2)
stup
I
stup
+ I
Vcc
Vcc
Vcc
+
+
I
I
+ I
ccL pin3
stup
ccS
G
EQUATION 6
1
d
=
BM
I
+ I
I
+ I
ccS
I
G
ccS
+ I
G
1 +
k
×
+
k
×
S∕Stup
S∕L
I
stup
ccL pin3
where: kS/Stup = (Vstup -- UVLO2)/(Vstup -- UVLO1)
S/L = (UVLO1 -- UVLO2)/(Vstup -- UVLO1)
k
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MC44608
EQUATION 7
1
d
=
BM
I
I
+ I
⎧
⎫
⎫
⎧
stup
ccS
I
G
1 +
×
⎩
k
+
k
×
⎪⎪
⎪
⎪
S∕Stup
S∕L
I
+ I
stup
ccL
pin3
⎭
⎭
⎩
EQUATION 8
1
d
=
BM
⎧
⎫
⎫
⎧
⎪
⎪
I
⎪
⎪
⎪
⎪
G
1
I
1 +
k1 +
× k
+ (k
×
)
⎨
⎬
⎪
⎪
S∕Stup
S∕L
I
stup
pin3
⎪
⎪
⎪
⎪
k2+
I
stup
⎩
⎭
⎩
⎭
where: k1 = Iccs/Istup
k2 = IccL/ stup
I
kS/Stup = (Vstup--UVLO2)/(Vstup--UVLO1)
kS/L = (UVLO1--UVLO2)/(Vstup--UVLO1)
PULSED MODE CURRENT SENSE CLAMPING LEVEL
Equations 9, 10, 11 and 12 allow the calculation of the Rcs value for the desired maximum current peak value during the
SMPS standby mode.
EQUATION 9
V
− (R × I
)
cs
cs
cs–th
Ipk
=
stby
R
S
where: Vcs--th is the CS comparator threshold
cs is the CS internal current source
I
RS is the sensing resistor
Rcs is the resistor connected between pin 2 and RS
EQUATION 10
I
cs
1 − cs
R
×
V
cs–th
Ipk
= V
×
×
stby
EQUATION 11
Ipk = V
cs–th
R
S
1 − (R × Y
cs
)
cs–stby
stby
cs–th
R
S
where: Ycs--stby = Ics/Vcs--th
Taking into account the circuit propagation delay (δtcs) and the Power Switch reaction time (δtps):
EQUATION 12
1 − (R × Y
cs
)
V
× (δt + δt
)
ps
cs–stby
cs
in
Ipk
=
V
×
+
stby
cs–th
R
L
p
S
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10
MC44608
60
50
79.0
77.0
85 C
t_rise
-- 2 5 C
75.0
25 C
40
30
73.0
71.0
t_fall
69.0
67.0
65.0
20
10
10
11
12
V
13
14
15
2.5
15
10
11
12
13
14
15
2.5
0.0
Voltage (V)
Pin6 V Voltage (V)
CC
CC
Figure 9. Output Switching Speed
Figure 10. Frequency Stability
90
80
70
60
50
40
5.08
5.07
5.06
5.05
85 C
5.04
5.03
85 C
25 C
-- 2 5 C
5.02
5.01
30
20
10
0
-- 2 5 C
5.00
4.99
25 C
4.98
0.0
0.5
1.0
1.5
2.0
0.5
1
1.5
2
Current Injected in Pin3 (mA)
Current Injected in Pin 3 (mA)
Figure 12. Vpin3 During the Working Period
Figure 11. Duty Cycle Control
5.0
4.80
4.60
4.40
4.20
4.00
4.5
4.0
3.5
3.0
2.5
2.0
1.5
-- 2 5 C
-- 2 5 C
25 C
25 C
3.80
3.60
3.40
3.20
3.00
85 C
85 C
-- 1 . 6
--1.4
--1.2
--1.0 --.08
--.06
--.04
--.02
10
11
12
13
14
Current Injected in Pin 3 (mA)
Pin6 V Voltage (V)
CC
Figure 14. Device Consumption when Switching
Figure 13. Vpin3 During the Latched Off Period
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11
MC44608
11.00
10.00
9.00
12.00
-- 2 5 C
11.00
10.00
-- 2 5 C
9.00
8.00
7.00
6.00
25 C
85 C
8.00
25 C
85 C
7.00
6.00
5.00
5.00
500
0
100
200
300
400
0
100
200
300
400
500
Vi Pin8 Voltage (Vi)
Vi Pin Voltage (V)
Figure 15. High Voltage Current Source
Figure 16. Overload Burst Mode
Figure 17. Hiccup Mode Waveforms
The data in Figure 16 corresponds to the waveform in
Figure 17. The Figure 17 shows VCC, ICC, Isense (pin 2) and
output switching pulses. This mode corresponds to an
overload condition.
Vout (pin 5). Vout (pin 5) in fact shows the envelope of the
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MC44608
The Figure 19 represents a complete power supply using the secondary reconfiguration.
The specification is as follows:
Input source:
3 Outputs
85 Vac to 265 Vac
112 V/0.45 A
16 V/1.5 A
8.0 V/1.0 A
80 W
@ Pout = 300 mW, 1.3 W
Output power
Standby mode
R F6
47288900
FI
C20
2N2FY
C11
220 pF
500 V
RFI
WIDE
MAINS
C1
FILTER
100 nF
R16
4.7 k Ω
4 kV
D18
MR856
112 V/0.45 A
1
14
C3
1 nF
D1, D2, D3, D4
1N5404
+
C12
C13
100 nF
47 mF
J3
2
250 V
12
C5
3
+
C17
120 pF
R7
47 kΩ
R1
220 mF
16 V/1.5 A
22 kΩ
400 V
5 W
C4
1 nF
D12
C6
47 nF
630 V
1
D6
MR856
R5
J4
2
D5
1N4007
1N4934
DZ1
MCR22--6
100 kΩ
D9
MR852
3
1
6
11
10
8 V/1 A
D7
C14
+
1N4148
1000 mF
1
8
35 V
7
C7
I
sense
+
22 mF
2
2
3
4
7
6
C16
120 pF
16 V
R19
18 kΩ
V
CC
C9
D13
470 pF
630 V
R2
1N4148
10 Ω
5
D10
MR852
D14
MR856
MTP6N60E
8
Post
Reg.
C8
100 nF
R17
2.2 kΩ
5 W
mP
+
C15
1000 mF
R4
3.9 k Ω
16 V
9
R3
0.27 Ω
R21
R9
100 kΩ
47 Ω
OPT1
C18
100 nF
R12
1 kΩ
R10
10 kΩ
C19
33 nF
DZ3
10 V
ON
OFF
R11
4.7 kΩ
DZ2
TL431CLP
R8
2.4 kΩ
ON = Normal Mode
OFF = Pulsed Mode
Figure 18. Typical Application
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13
MC44608
The secondary reconfiguration is activated by the mP
applied to the secondary windings 12--14, 10--11 and 6--7
(Vaux) are thus divided by ratio N12--14 / N9--8 (number of
turns of the winding 12--14 over number of turns of the
winding 9--8). In this reconfigured status all the secondary
voltages are lowered except the 8.0 V one. The regulation
during every pulsed or burst is performed by the zener diode
DZ3 which value has to be chosen higher than the normal
mode regulation level. This working mode creates a voltage
ripple on the 8.0 V rail which generally must be post
regulated for the microProcessor supply.
through the switch. The dV/dt appearing on the high voltage
winding (pins 14 of the transformer) at every TMOS switch
off, produces a current spike through the series RC network
R7, C17. Accordingtothe switchpositionthisspike iseither
absorbed by the ground (switch closed) or flows into the
thyristor gate (switch open) thus firing the MCR22--6. The
closed position of the switch corresponds to the Pulsed
Mode activation. In this secondary side SMPS status the
highvoltagewinding(12--14)isconnectedthroughD12and
DZ1 to the 8.0 V low voltage secondary rail. The voltages
Figure 19. SMPS Pulsed Mode
The Figure 19 shows the SMPS behavior while working
in the reconfigured mode. The top curve represents the VCC
voltage (pin 6 of the MC44608). The middle curve
represents the 8.0 V rail. The regulation is taking place at
11.68 V. On the bottom curve the pin 2 voltage is shown.
This voltage represents the current sense signal. The pin 2
voltage is the result of the 200 mA current source activated
during the startup phase and also during the working phase
which flows through the R4 resistor. The used high
resolution mode of the oscilloscope does not allow to show
the effective ton current flowing in the sensing resistor R11.
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MC44608
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626--05
ISSUE M
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
A
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION E IS MEASURED WITH THE LEADS RE-
STRAINED PARALLEL AT WIDTH E2.
4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
D1
E
8
5
4
INCHES
NOM
-- -- -- -- 0 . 2 1 0
-- -- -- -- -- -- -- --
MILLIMETERS
E1
DIM MIN
-- -- -- --
A1 0 . 0 1 5
b
C
D
MAX
MIN
NOM
-- -- -- --
-- -- -- --
0.46
0.25
MAX
A
-- -- -- --
0 . 3 8
0.35
0.20
9.02
0 . 1 3
7.62
6.10
5 . 3 3
-- -- -- --
0.56
0.36
1
0.014 0.018 0.022
0.008 0.010 0.014
0.355 0.365 0.400
NOTE 5
9.27 10.02
F
c
D1 0 . 0 0 5
0.300 0.310 0.325
E1 0.240 0.250 0.280
-- -- -- --
-- -- -- --
-- -- -- --
7.87
6.35
-- -- -- --
8.26
7.11
E
E2
TOP VIEW
END VIEW
E2
E3
e
0.300 BSC
-- -- -- -- 0 . 4 3 0
0.100 BSC
7.62 BSC
NOTE 3
-- -- -- --
-- -- -- --
2.92
-- -- -- -- 1 0 . 9 2
2.54 BSC
3.30
e/2
L
0.115 0.130 0.150
3.81
A
L
A1
SEATING
PLANE
C
E3
e
8X
b
M
0.010
C A
END VIEW
SIDE VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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