MC54HC4051 [ONSEMI]
Analog Multiplexers/Demultiplexers; 模拟多路复用器/多路解复用器
| 型号： | MC54HC4051 |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexers/Demultiplexers |
| 文件： | 总15页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize sili-
con–gate CMOS technology to achieve fast propagation delays, low ON
resistances, and low OFF leakage currents. These analog multiplexers/
demultiplexers control analog voltages that may vary across the complete
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
power supply range (from V
to V ).
CC
EE
16
16
The HC4051, HC4052 and HC4053 are identical in pinout to the
metal–gate MC14051B, MC14052B and MC14053B. The Channel–Select
inputs determine which one of the Analog Inputs/Outputs is to be connected,
by means of an analog switch, to the Common Output/Input. When the
Enable pin is HIGH, all analog switches are turned off.
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
These devices have been designed so that the ON resistance (R ) is
on
of metal–gate CMOS analog
1
more linear over input voltage than R
switches.
on
DW SUFFIX
SOIC PACKAGE
CASE 751G–02
16
16
For multiplexers/demultiplexers with channel–select latches, see
HC4351, HC4352 and HC4353.
1
1
•
•
•
•
•
•
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
Analog Power Supply Range (V
– V ) = 2.0 to 12.0 V
CC
EE
ORDERING INFORMATION
Digital (Control) Power Supply Range (V
CC
Improved Linearity and Lower ON Resistance Than Metal–Gate
– GND) = 2.0 to 6.0 V
MC54HCXXXXJ
Ceramic
Plastic
SOIC
SOIC Wide
TSSOP
MC74HCXXXXN
MC74HCXXXXD
MC74HCXXXXDW
MC74HCXXXXDT
Counterparts
•
•
•
Low Noise
In Compliance With the Requirements of JEDEC Standard No. 7A
Chip Complexity: HC4051 — 184 FETs or 46 Equivalent Gates
HC4052 — 168 FETs or 42 Equivalent Gates
HC4053 — 156 FETs or 39 Equivalent Gates
FUNCTION TABLE – MC54/74HC4051
Control Inputs
LOGIC DIAGRAM
MC54/74HC4051
Select
Single–Pole, 8–Position Plus Common Off
Enable
C
B
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
NONE
13
X0
14
X1
L
15
X2
H
H
H
H
X
ANALOG
12
1
MULTIPLEXER/
DEMULTIPLEXER
X3
X4
X5
X6
X7
A
3
COMMON
OUTPUT/
INPUT
L
INPUTS/
X
V
OUTPUTS
H
H
X
5
2
4
X = Don’t Care
Pinout: MC54/74HC4051 (Top View)
11
10
9
X2
X1
X0
X3
A
B
C
9
CC
CHANNEL
SELECT
INPUTS
B
16
15
14
13
12
11
10
C
6
ENABLE
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
1
2
3
4
5
6
7
8
X4
X6
X
X7
X5 Enable
V
GND
EE
10/95
Motorola, Inc. 1995
REV 7
MC54/74HC4051 MC74HC4052 MC54/74HC4053
FUNCTION TABLE – MC74HC4052
LOGIC DIAGRAM
MC74HC4052
Double–Pole, 4–Position Plus Common Off
Control Inputs
Select
Enable
B
A
ON Channels
12
X0
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
Y0
Y1
Y2
Y3
X0
X1
X2
X3
14
X1
X2
X3
13
X SWITCH
Y SWITCH
X
Y
15
11
COMMON
OUTPUTS/INPUTS
ANALOG
NONE
INPUTS/OUTPUTS
1
5
Y0
Y1
Y2
Y3
A
X = Don’t Care
3
2
4
Pinout: MC74HC4052 (Top View)
10
9
V
X2
15
X1
14
X
X0
12
X3
11
A
B
CHANNEL-SELECT
INPUTS
CC
PIN 16 = V
CC
B
16
13
10
9
PIN 7 = V
EE
PIN 8 = GND
6
ENABLE
1
2
3
4
5
6
7
8
Y0
Y2
Y
Y3
Y1 Enable
V
GND
EE
FUNCTION TABLE – MC54/74HC4053
Control Inputs
LOGIC DIAGRAM
MC54/74HC4053
Triple Single–Pole, Double–Position Plus Common Off
Select
Enable
C
B
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
Z0
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
12
Z0
Z0
Z0
Z1
Z1
Z1
Z1
X1
X0
X1
X0
X1
X0
X1
X0
X1
14
X
13
X SWITCH
L
H
H
H
H
X
2
1
L
Y0
Y1
15
4
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
Y
Z
H
H
X
Y SWITCH
Z SWITCH
5
3
Z0
Z1
X = Don’t Care
11
10
9
A
B
C
PIN 16 = V
PIN 7 = V
PIN 8 = GND
CHANNEL-SELECT
INPUTS
CC
EE
Pinout: MC54/74HC4053 (Top View)
6
V
Y
X
X1
13
X0
12
A
B
C
9
CC
ENABLE
16
15
14
11
10
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch
1
2
3
4
Z
5
6
7
8
Y1
Y0
Z1
Z0 Enable
V
GND
EE
MOTOROLA
2
MC54/74HC4051 MC74HC4052 MC54/74HC4053
MAXIMUM RATINGS*
Symbol
Parameter
(Referenced to GND)
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
CC
Positive DC Supply Voltage
– 0.5 to + 7.0
– 0.5 to + 14.0
V
(Referenced to V
)
EE
V
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
– 7.0 to + 5.0
V
V
EE
V
V
V
– 0.5 to
IS
EE
+ 0.5
CC
cuit. For proper operation, V and
in
V
should be constrained to the
V
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
– 0.5 to V
+ 0.5
V
out
in
CC
range GND (V or V
)
V
CC
.
in out
I
± 25
mA
mW
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
TSSOP Package†
T
Storage Temperature Range
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP
L
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Positive DC Supply Voltage
Min
Max
Unit
V
CC
(Referenced to GND)
(Referenced to V
2.0
2.0
6.0
12.0
V
)
EE
V
EE
Negative DC Supply Voltage, Output (Referenced to
GND)
– 6.0 GND
V
V
Analog Input Voltage
V
V
V
V
V
IS
EE
CC
V
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
GND
in
CC
V
IO
*
1.2
– 55 + 125
V
T
C
ns
A
t , t
r f
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
* For voltage drops across switch greater than 1.2V (switch on), excessive V
drawn;i.e., thecurrentoutoftheswitchmaycontainbothV
CC
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
current may be
CC
andswitchinputcomponents. The
3
MOTOROLA
MC54/74HC4051 MC74HC4052 MC54/74HC4053
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) V
= GND, Except Where Noted
EE
Guaranteed Limit
–55 to 25°C ≤85°C ≤125°C
V
CC
V
Symbol
Parameter
Condition
= Per Spec
Unit
V
IH
Minimum High–Level Input Voltage,
Channel–Select or Enable Inputs
R
R
2.0
4.5
6.0
1.50
3.15
4.20
1.50
3.15
4.20
1.50
3.15
4.20
V
on
on
V
Maximum Low–Level Input Voltage,
Channel–Select or Enable Inputs
= Per Spec
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
IL
in
I
Maximum Input Leakage Current,
Channel–Select or Enable Inputs
V
V
= V
= – 6.0 V
or GND,
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
EE
CC
I
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
CC
V
V
= V
CC
= 0 V
or GND;
V
V
= GND
= – 6.0
6.0
6.0
2
8
20
80
40
160
IS
IO
EE
EE
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
Symbol
Parameter
Condition
V
CC
V
EE
Unit
–55 to 25°C ≤85°C ≤125°C
R
Maximum “ON” Resistance
V
V
= V or V ; V = V
to
4.5
4.5
6.0
0.0
– 4.5
– 6.0
190
120
100
240
150
125
280
170
140
Ω
on
in
IL IH IS
CC
; I ≤ 2.0 mA
EE
S
(Figures 1, 2)
V
V
= V or V ; V = V
IL IH IS
or
4.5
4.5
6.0
0.0
– 4.5
– 6.0
150
100
80
190
125
100
230
140
115
in
CC
(Endpoints); I ≤ 2.0 mA
EE
S
(Figures 1, 2)
∆R
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
= V or V
IL
;
4.5
4.5
6.0
0.0
– 4.5
– 6.0
30
12
10
35
15
12
40
18
14
Ω
on
in
IS
IH
= 1/2 (V
– V );
EE
CC
I
S
≤ 2.0 mA
I
off
Maximum Off–Channel Leakage
Current, Any One Channel
V
V
= V or V
;
µA
in
IL
IH
= V
CC
– V
;
6.0
– 6.0
0.1
0.5
1.0
IO
EE
Switch Off (Figure 3)
Maximum Off–Channel HC4051
V
V
= V or V
IL IH
;
6.0
6.0
6.0
– 6.0
– 6.0
– 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
in
Leakage Current,
Common Channel
HC4052
HC4053 Switch Off (Figure 4)
= V
– V
;
IO
CC EE
I
on
Maximum On–Channel HC4051
Leakage Current,
V
= V or V
IL IH
;
6.0
6.0
6.0
– 6.0
– 6.0
– 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
µA
in
HC4052 Switch–to–Switch =
Channel–to–Channel
HC4053
V
CC
– V ; (Figure 5)
EE
MOTOROLA
4
MC54/74HC4051 MC74HC4052 MC54/74HC4053
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
V
CC
V
Symbol
Parameter
Unit
–55 to 25°C
≤85°C
≤125°C
t
t
t
,
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
4.5
6.0
370
74
63
465
93
79
550
110
94
ns
PLH
t
PHL
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
4.5
6.0
290
58
49
364
73
62
430
86
73
PLZ
t
PHZ
t
t
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
4.5
6.0
345
69
59
435
87
74
515
103
87
PZL
PZH
C
Maximum Input Capacitance, Channel–Select or Enable Inputs
10
35
10
35
10
35
pF
pF
in
C
Maximum Capacitance
(All Switches Off)
Analog I/O
I/O
Common O/I: HC4051
HC4052
130
80
130
80
130
80
HC4053
50
50
50
Feedthrough
1.0
1.0
1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V, V = 0 V
EE
CC
C
Power Dissipation Capacitance (Figure 13)*
HC4051
HC4052
HC4053
pF
45
80
45
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
5
MOTOROLA
MC54/74HC4051 MC74HC4052 MC54/74HC4053
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Limit*
25°C
‘52
V
V
CC
V
EE
V
Symbol
Parameter
Condition
= 1MHz Sine Wave; Adjust f Voltage to
Unit
BW
Maximum On–Channel Bandwidth
or Minimum Frequency Response
(Figure 6)
f
‘51
‘53
MHz
in
in
Obtain 0dBm at V ; Increase f Frequency
OS
in
2.25
4.50
6.00
80
80
80
95
95
95
120
120
120
–2.25
–4.50
–6.00
Until dB Meter Reads –3dB;
R
= 50Ω, C = 10pF
L
L
—
—
Off–Channel Feedthrough Isolation
(Figure 7)
f
= Sine Wave; Adjust f Voltage to Obtain
in
2.25 –2.25
4.50 –4.50
–50
–50
–50
dB
in
0dBm at V
IS
in
f
= 10kHz, R = 600Ω, C = 50pF 6.00 –6.00
L L
2.25 –2.25
4.50 –4.50
–40
–40
–40
f
in
= 1.0MHz, R = 50Ω, C = 10pF 6.00 –6.00
L L
Feedthrough Noise.
Channel–Select Input to Common
I/O (Figure 8)
V
≤ 1MHz Square Wave (t = t = 6ns);
2.25 –2.25
4.50 –4.50
25
105
135
mV
PP
in
r
f
Adjust R at Setup so that I = 0A;
Enable = GND
L
S
R
= 600Ω, C = 50pF 6.00 –6.00
L
L
2.25 –2.25
4.50 –4.50
= 10kΩ, C = 10pF 6.00 –6.00
35
145
190
R
L
L
—
Crosstalk Between Any Two
Switches (Figure 12)
(Test does not apply to HC4051)
f
= Sine Wave; Adjust f Voltage to Obtain
in
2.25 –2.25
4.50 –4.50
–50
–50
–50
dB
in
0dBm at V
IS
f
in
= 10kHz, R = 600Ω, C = 50pF 6.00 –6.00
L L
2.25 –2.25
4.50 –4.50
= 1.0MHz, R = 50Ω, C = 10pF 6.00 –6.00
–60
–60
–60
f
in
L
L
THD
Total Harmonic Distortion
(Figure 14)
f
= 1kHz, R = 10kΩ, C = 50pF
%
in
THD = THD
L
L
– THD
measured
source
PP
V
IS
IS
= 4.0V
sine wave
sine wave
sine wave
2.25 –2.25
4.50 –4.50
6.00 –6.00
0.10
0.08
0.05
V
= 8.0V
PP
PP
V
IS
= 11.0V
* Limits not tested. Determined by design and verified by qualification.
MOTOROLA
6
MC54/74HC4051 MC74HC4052 MC54/74HC4053
300
250
200
150
100
120
100
80
125°C
25°C
125
°C
60
25°C
–55°C
40
–55°C
50
0
20
0
0
0.25 0.50
0.75
1.0
1.25
1.5
1.75
2.0
2.25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
, INPUT VOLTAGE (VOLTS), REFERENCED TO V
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS EE
IS EE
Figure 1a. Typical On Resistance, V
– V
EE
= 2.0 V
Figure 1b. Typical On Resistance, V
– V = 4.5 V
EE
CC
CC
120
105
90
90
75
60
45
30
125°C
125°C
75
25°C
25°C
60
–55°C
45
–55°C
30
15
0
15
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
V
, INPUT VOLTAGE (VOLTS), REFERENCED TO V
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS EE
IS EE
Figure 1c. Typical On Resistance, V
– V
EE
= 6.0 V
Figure 1d. Typical On Resistance, V
– V = 9.0 V
EE
CC
CC
80
70
60
50
40
30
20
PLOTTER
125°C
PROGRAMMABLE
POWER
SUPPLY
MINI COMPUTER
DC ANALYZER
25°C
–
+
V
CC
–55°C
DEVICE
UNDER TEST
10
0
ANALOG IN
COMMON OUT
EE
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
GND
V
V
, INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS EE
Figure 1e. Typical On Resistance, V
– V
EE
= 12.0 V
Figure 2. On Resistance Test Set–Up
CC
7
MOTOROLA
MC54/74HC4051 MC74HC4052 MC54/74HC4053
V
V
CC
CC
V
V
CC
CC
16
16
V
V
V
V
EE
EE
ANALOG I/O
OFF
OFF
OFF
OFF
A
V
CC
CC
COMMON O/I
NC
COMMON O/I
V
6
7
8
6
7
8
IH
IH
V
V
EE
EE
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set–Up
V
CC
16
V
OS
V
V
CC
V
CC
16
0.1µF
A
dB
METER
f
ON
ON
in
N/C
R
L
C *
EE
CC
L
COMMON O/I
OFF
V
ANALOG I/O
V
6
7
8
6
7
8
IL
V
V
EE
EE
*Includes all probe and jig capacitance
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set–Up
Figure 6. Maximum On Channel Bandwidth,
Test Set–Up
V
V
V
CC
16
V
CC
16
IS
OS
0.1µF
dB
METER
R
L
f
OFF
ON/OFF
OFF/ON
COMMON O/I
in
TEST
ANALOG I/O
R
R
L
L
C *
POINT
L
R
L
C *
L
R
L
6
7
8
6
7
8
V
CC
V
≤
1 MHz
11
in
t = t = 6 ns
r
f
V
V
EE
EE
V
GND
CC
CHANNEL SELECT
CHANNEL SELECT
V
or V
IH
IL
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7. Off Channel Feedthrough Isolation,
Test Set–Up
Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set–Up
MOTOROLA
8
MC54/74HC4051 MC74HC4052 MC54/74HC4053
V
CC
16
V
CC
V
CC
ON/OFF
OFF/ON
COMMON O/I
C *
CHANNEL
SELECT
TEST
POINT
50%
ANALOG I/O
GND
L
t
t
PHL
PLH
6
7
8
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set–Up Channel
Select to Analog Out
V
CC
16
COMMON O/I
C *
ANALOG I/O
TEST
POINT
V
CC
ON
ANALOG
IN
50%
L
GND
t
t
PHL
PLH
6
7
8
ANALOG
OUT
50%
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In
to Analog Out
Figure 10b. Propagation Delay, Test Set–Up
Analog In to Analog Out
t
t
POSITION 1 WHEN TESTING t
POSITION 2 WHEN TESTING t
AND t
AND t
f
r
PHZ
PLZ
PZH
PZL
1
2
V
CC
90%
50%
10%
ENABLE
V
CC
16
GND
1kΩ
V
CC
t
t
PLZ
PZL
HIGH
IMPEDANCE
1
2
ANALOG I/O
ENABLE
TEST
POINT
ON/OFF
ANALOG
OUT
50%
C *
L
10%
V
OL
t
t
PZH PHZ
6
7
8
V
90%
OH
ANALOG
OUT
50%
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set–Up
Enable to Analog Out
9
MOTOROLA
MC54/74HC4051 MC74HC4052 MC54/74HC4053
V
CC
V
IS
A
V
CC
16
16
R
V
L
OS
ON/OFF
OFF/ON
COMMON O/I
f
ON
in
NC
ANALOG I/O
0.1µF
OFF
V
R
L
R
EE
C *
L
C *
V
L
L
CC
R
6
7
8
L
6
7
8
11
V
EE
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 12. Crosstalk Between Any Two
Switches, Test Set–Up
Figure 13. Power Dissipation Capacitance,
Test Set–Up
0
–10
–20
–30
–40
V
IS
FUNDAMENTAL FREQUENCY
V
CC
16
V
OS
0.1µF
TO
f
in
DISTORTION
METER
ON
R
L
C *
L
–50
–60
–70
DEVICE
SOURCE
6
7
8
–80
–90
V
EE
*Includes all probe and jig capacitance
–100
1.0
2.0
3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set–Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
or GND logic levels. V being recognized as a logic
high and GND being recognized as a logic low. In this exam-
ple:
V
or GND through a low value resistor helps minimize
CC
V
crosstalk and feedthrough noise that may be picked up by an
unused switch.
Although used here, balanced supplies are not a require-
ment. The only constraints on the power supplies are that:
CC
CC
V
= +5V = logic high
CC
GND = 0V = logic low
V
– GND = 2 to 6 volts
– GND = 0 to –6 volts
CC
The maximum analog voltage swings are determined by
V
V
EE
the supply voltages V
voltage should not exceed V . Similarly, the negative peak
analog voltage should not go below V . In this example, the
difference between V
and V . The positive peak analog
CC
EE
– V
= 2 to 12 volts
≤ GND
CC
EE
CC
and V
EE
EE
When voltage transients above V
and/or below V
are
EE
and V
is ten volts. Therefore,
EE
CC
CC
anticipated on the analog channels, external Germanium or
Schottky diodes (D ) are recommended as shown in Figure
16. These diodes should be able to absorb the maximum
anticipated current surges during clipping.
using the configuration of Figure 15, a maximum analog sig-
nal of ten volts peak–to–peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not con-
nected). However, tying unused analog inputs and outputs to
x
MOTOROLA
10
MC54/74HC4051 MC74HC4052 MC54/74HC4053
V
V
CC
CC
+5V
V
CC
16
ON/OFF
D
D
16
x
x
+5V
–5V
+5V
–5V
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
D
D
x
x
V
V
EE
EE
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
6
7
8
11
10
9
7
8
–5V
V
EE
Figure 15. Application Example
Figure 16. External Germanium or
Schottky Clipping Diodes
+5V
+5V
16
ON/OFF
16
ON/OFF
+5V
+5V
+5V
+5V
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
V
V
V
V
EE
EE
EE
EE
+5V
*
R
R
R
+5V
6
7
8
11
10
9
6
7
8
11
10
9
LSTTL/NMOS
CIRCUITRY
LSTTL/NMOS
CIRCUITRY
V
V
EE
EE
* 2K
≤ R ≤ 10K
HCT
BUFFER
a. Using Pull–Up Resistors
b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
11
10
9
13
X0
LEVEL
SHIFTER
A
14
X1
15
X2
LEVEL
SHIFTER
B
C
12
X3
1
LEVEL
SHIFTER
X4
5
X5
6
2
LEVEL
SHIFTER
ENABLE
X6
4
X7
3
X
Figure 18. Function Diagram, HC4051
11
MOTOROLA
MC54/74HC4051 MC74HC4052 MC54/74HC4053
10
12
14
15
LEVEL
SHIFTER
A
X0
X1
X2
9
LEVEL
SHIFTER
B
11
13
1
X3
X
6
LEVEL
SHIFTER
ENABLE
Y0
5
2
4
3
Y1
Y2
Y3
Y
Figure 19. Function Diagram, HC4052
11
10
9
13
LEVEL
SHIFTER
A
X1
12
14
1
X0
X
LEVEL
SHIFTER
B
C
Y1
2
15
3
Y0
Y
LEVEL
SHIFTER
Z1
5
4
Z0
Z
6
LEVEL
SHIFTER
ENABLE
Figure 20. Function Diagram, HC4053
MOTOROLA
12
MC54/74HC4051 MC74HC4052 MC54/74HC4053
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
NOTES:
16
1
9
8
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
–B
–
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.93
7.49
5.08
0.50
0.750
0.240
—
0.015
0.050 BSC
–T
SEAT
–
ING
N
K
PLANE
F
G
J
K
L
M
N
0.055
0.100 BSC
0.008
0.125
0.065
1.40
2.54 BSC
0.21
3.18
1.65
E
M
0.015
0.170
0.38
4.31
J 16 PL
F
G
0.300 BSC
15
0.040
7.62 BSC
15
1.01
0.51
M
S
0.25 (0.010)
T
B
D 16 PL
°
°
0°
0°
M
S
0.25 (0.010)
T
A
0.020
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
9
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
1
8
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
PLANE
–T
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
–
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
M
S
0°
10°
0°
10°
M
M
0.25 (0.010)
T
A
0.020
0.040
0.51
1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
0.050 BSC
0.008
0.004
F
K
R X 45°
C
1.25
1.27 BSC
–T
0.19
0.10
0.25
0.25
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
13
MOTOROLA
MC54/74HC4051 MC74HC4052 MC54/74HC4053
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
16
9
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–B–
8X P
0.010 (0.25)
M
M
B
1
8
J
16X D
MILLIMETERS
INCHES
M
S
S
DIM
A
B
C
D
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
MAX
0.411
0.299
0.104
0.019
0.035
0.010 (0.25)
T
A
B
0.400
0.292
0.093
0.014
0.020
F
R X 45
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
C
–T–
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
M
SEATING
14X G
K
PLANE
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T
U
V
NOTES:
S
0.15 (0.006) T
U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
B
–U–
SECTION N–N
L
0.25 (0.010) PER SIDE.
J
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T
U
A
M
MILLIMETERS
INCHES
–V–
DIM
A
B
C
D
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
0.193
0.169
–––
0.002
0.020
F
F
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
MOTOROLA
14
MC54/74HC4051 MC74HC4052 MC54/74HC4053
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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