MC74AC161D [ONSEMI]
Synchronous Presettable Binary Counter; 同步可预置二进制计数器
| 型号： | MC74AC161D |
| 厂家： | 
ONSEMI |
| 描述： | Synchronous Presettable Binary Counter |
| 文件： | 总15页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC161, MC74ACT161,
MC74AC163, MC74ACT163
Synchronous Presettable
Binary Counter
The MC74AC161/74ACT161 and MC74AC163/74ACT163 are
high−speed synchronous modulo−16 binary counters. They are
synchronously presettable for application in programmable dividers
and have two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multistage counters.
The MC74AC161/74ACT161 has an asynchronous Master Reset
input that overrides all other inputs and forces the outputs LOW. The
MC74AC163/74ACT163 has a Synchronous Reset input that
overrides counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
http://onsemi.com
DIP−16
N SUFFIX
CASE 648
16
1
• Synchronous Counting and Loading
• High−Speed Synchronous Expansion
• Typical Count Rate of 125 MHz
• Outputs Source/Sink 24 mA
• ′ACT161 and ′ACT163 Have TTL Compatible Inputs
w These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
SO−16
D SUFFIX
CASE 751B
16
1
1
EIAJ−16
M SUFFIX
CASE 966
16
V
TC
15
Q
Q
Q
Q
3
CET PE
10 9
CC
0
1
2
16
14
13
12
11
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
1
2
3
4
5
6
7
CEP GND
8
DEVICE MARKING INFORMATION
*R
CP
P
0
P
1
P
2
P
3
See general marking information in the device marking
section on page 11 of this data sheet.
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
CEP
CET
CP
FUNCTION
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
MR
SR
(′161) Asynchronous Master Reset Input
(′163) Synchronous Reset Input
Parallel Data Inputs
P −P
0
3
PE
Parallel Enable Input
Q −Q
0
Flip−Flop Outputs
3
TC
Terminal Count Output
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 7
MC74AC161/D
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
operation, as shown in the Mode Select Table. A LOW
signal on MR overrides all other inputs and asynchronously
forces all outputs LOW. A LOW signal on SR overrides
counting and parallel loading and allows all outputs to go
LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
PE P
P P P
1 2 3
0
CEP
CET
CP
TC
*R Q
Q Q Q
1 2 3
0
Data (P ) inputs to be loaded into the flip−flops on the next
n
rising edge of CP. With PE and MR (′161) or SR (′163)
HIGH, CEP and CET permit counting when both are HIGH.
Conversely, a LOW signal on either CEP or CET inhibits
counting.
*MR for ′161
*SR for ′163
Figure 2. Logic Symbol
The MC74AC161/ACT161 and MC74AC163/ACT163 use
D−type edge−triggered flip−flops and changing the SR, PE,
CEP and CET inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold
times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchronous
multistage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the MC74AC568 data sheet. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or
asynchronous reset for flip−flops, counters or registers.
Logic Equations:
FUNCTIONAL DESCRIPTION
The MC74AC161/ACT161 and MC74AC163/ACT163
count modulo−16 binary sequence. From state 15 (HHHH)
they increment to state 0 (LLLL). The clock inputs of all
flip−flops are driven in parallel through a clock buffer. Thus
all changes of the Q outputs (except due to Master Reset of
the ′161) occur as a result of, and synchronous with, the
LOW−to−HIGH transition of the CP input signal. The
circuits have four fundamental modes of operation, in order
of precedence: asynchronous reset (′161), synchronous reset
(′163), parallel load, count−up and hold. Five control inputs
− Master Reset (MR, ′161), Synchronous Reset (SR, ′163),
Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET) − determine the mode of
Count Enable = CEP•CET•PE
TC = Q •Q •Q •Q •CET
0
1
2
3
0
1
2
3
4
5
6
7
8
MODE SELECT TABLE
Action on the Rising
15
14
13
12
PE
*SR
CET
CEP Clock Edge ( )
L
X
L
H
H
H
X
X
H
L
X
X
H
X
L
Reset (Clear)
Load (P → Q )
Count (Increment)
No Change (Hold)
No Change (Hold)
H
H
H
H
n
n
X
11
10
9
*For ′163 only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Figure 3. State Diagram
http://onsemi.com
2
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
P
P
P
P
3
0
1
2
PE
′161
′163
CEP
CET
′163
ONLY
TC
′161
ONLY
CP
CP
CP
D
D
CP
Q
D
Q
C
DETAIL A
DETAIL A
DETAIL A
Q
0
Q
0
DETAIL A
MR ′161
SR ′163
Q
3
Q
2
Q
Q
1
0
NOTE: This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
Figure 4. Logic Diagram
MAXIMUM RATINGS*
Symbol
Parameter
Value
−0.5 to +7.0
−0.5 to V +0.5
Unit
V
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
CC
V
IN
CC
−0.5 to V +0.5
V
OUT
CC
I
I
I
±20
±50
mA
mA
mA
°C
IN
DC Output Sink/Source Current, per Pin
OUT
CC
DC V or GND Current per Output Pin
±50
CC
T
stg
Storage Temperature
−65 to +150
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
mended Operating Conditions.
http://onsemi.com
3
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
−
Max
6.0
Unit
′AC
V
V
Supply Voltage
V
V
CC
′ACT
5.5
, V
OUT
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
IN
V
CC
V
CC
V
CC
V
CC
V
CC
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
−
150
40
25
10
8.0
−
−
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
−
−
−
−
−
ns/V
t , t
r
f
−
−
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
t , t
ns/V
r
f
−
T
J
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
−
140
85
°C
°C
T
A
−40
−
25
−
I
−24
24
mA
mA
OH
OL
I
Output Current − Low
−
−
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
DC CHARACTERISTICS
74AC
74AC
T
=
A
V
(V)
CC
T
A
= +25°C
−40°C to
+85°C
Symbol
Parameter
Unit
Conditions
Typ
Guaranteed Limits
V
V
V
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
= 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V − 0.1 V
CC
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
OUT
= 0.1 V
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= −50 mA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IH
IN
IL
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
−12 mA
−24 mA
−24 mA
V
V
I
OH
V
OL
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 mA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
24 mA
24 mA
V
I
OL
I
IN
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
mA
V = V , GND
I
CC
I
I
I
5.5
5.5
−
−
−
−
75
mA
mA
V
V
= 1.65 V Max
= 3.85 V Min
†Minimum Dynamic
Output Current
OLD
OHD
CC
OLD
−75
OHD
Maximum Quiescent
Supply Current
5.5
−
8.0
80
mA
V
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
I
IN
and I @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
CC
CC
http://onsemi.com
4
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC161
74AC161
T
= −40°C
A
T
= +25°C
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Min
Typ
Max
Min
Max
Maximum Count
Frequency
3.3
5.0
70
110
111
167
−
−
60
95
−
−
f
t
t
t
t
t
t
t
t
MHz
ns
3−3
3−6
3−6
3−6
3−6
3−6
3−6
3−6
3−6
max
Propagation Delay
3.3
5.0
2.0
1.5
7.0
5.0
12.0
9.0
1.5
1.0
13.5
9.5
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PHL
CP to Q (PE Input HIGH or LOW)
n
Propagation Delay
3.3
5.0
1.5
1.5
7.0
5.0
12.0
9.5
1.5
1.5
13.0
10.0
ns
CP to Q (PE Input HIGH or LOW)
n
Propagation Delay
CP to TC
3.3
5.0
3.0
2.0
9.0
6.0
15.0
10.5
2.5
1.5
16.5
11.5
ns
Propagation Delay
CP to TC
3.3
5.0
3.5
2.0
8.5
6.5
14.0
11.0
2.5
2.0
15.5
11.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.0
1.5
5.5
3.5
9.5
6.5
1.5
1.0
11.0
7.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.5
2.0
6.5
5.0
11.0
8.5
2.0
1.5
12.5
9.5
ns
Propagation Delay
3.3
5.0
2.0
1.5
6.0
5.5
12.0
9.5
1.5
1.5
13.5
10.0
ns
MR to Q
n
Propagation Delay
MR to TC
3.3
5.0
3.5
2.5
10.0
8.5
15.0
13.0
3.0
2.5
17.5
13.5
ns
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC163 74AC163
= −40°C
T
A
T
A
= +25°C
V
CC
*
Fig.
No.
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
(V)
L
Min
Typ
Max
Min
Max
Maximum Count
Frequency
3.3
5.0
70
110
95
140
−
−
60
95
−
−
f
t
t
t
t
t
t
MHz
ns
3−3
3−6
3−6
3−6
3−6
3−6
3−6
max
Propagation Delay
3.3
5.0
2.0
1.5
7.5
5.5
12.5
9.0
1.5
1.0
13.5
9.5
PLH
PHL
PLH
PHL
PLH
PHL
CP to Q (PE Input HIGH or LOW)
n
Propagation Delay
3.3
5.0
1.5
1.5
8.5
6.0
12.0
9.5
1.5
1.5
13.0
10.0
ns
CP to Q (PE Input HIGH or LOW)
n
Propagation Delay
CP to TC
3.3
5.0
3.0
2.0
9.5
7.0
15.0
10.5
2.5
1.5
16.5
11.5
ns
Propagation Delay
CP to TC
3.3
5.0
3.5
2.0
11.0
8.0
14.0
11.0
2.5
2.0
15.5
11.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.0
1.5
7.5
5.5
9.5
6.5
1.5
1.0
11.0
7.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.5
2.0
8.5
6.0
11.0
8.5
2.0
1.5
12.5
9.5
ns
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
http://onsemi.com
5
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC OPERATING REQUIREMENTS
74AC161
= +25°C
74AC161
= −40°C
T
A
T
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
P to CP
n
3.3
5.0
6.0
3.5
13.5
8.5
16.0
10.5
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3−9
3−9
3−9
3−9
3−9
3−9
3−6
3−6
3−6
3−9
s
Hold Time, HIGH or LOW
P to CP
n
3.3
5.0
−7.0
−4.0
−1.0
0
−0.5
0
h
s
Setup Time, HIGH or LOW
PE to CP
3.3
5.0
6.5
4.0
11.5
7.5
14.0
8.5
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
−6.0
−3.5
0
0.5
0
1.0
h
s
Setup Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
3.0
2.0
6.0
4.5
7.0
5.0
Hold Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
−3.5
−2.0
0
0
0
0.5
h
w
w
w
Clock Pulse Width (Load)
HIGH or LOW
3.3
5.0
2.0
2.0
3.5
2.5
4.0
3.0
Clock Pulse Width (Count)
HIGH or LOW
3.3
5.0
2.0
2.0
4.0
3.0
4.5
3.5
3.3
5.0
3.0
2.5
5.5
4.5
7.5
6.0
MR Pulse Width, LOW
Recovery TIme
MR to CP
3.3
5.0
−2.0
−1.0
−0.5
0
0
0.5
rec
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
http://onsemi.com
6
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC OPERATING REQUIREMENTS
74AC163
= +25°C
74AC163
= −40°C
T
A
T
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
P to CP
n
3.3
5.0
5.5
4.0
13.5
8.5
16.0
10.5
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3−9
3−9
3−9
3−9
3−9
3−9
3−9
3−9
3−6
3−6
s
Hold Time, HIGH or LOW
P to CP
n
3.3
5.0
−7.0
−5.0
−1.0
0
−0.5
0
h
s
Setup Time, HIGH or LOW
SR to CP
3.3
5.0
5.5
4.0
14
9.5
16.5
11.0
Hold Time, HIGH or LOW
SR to CP
3.3
5.0
−7.5
−5.5
−1.0
−0.5
−0.5
0
h
s
Setup Time, HIGH or LOW
PE to CP
3.3
5.0
5.5
4.0
11.5
7.5
14.0
8.5
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
−7.5
−5.0
−1.0
−0.5
−0.5
0
h
s
Setup Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
3.5
2.5
6.0
4.5
7.0
5.0
Hold Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
−4.5
−3.0
0
0
0
0.5
h
w
w
Clock Pulse Width (Load)
HIGH or LOW
3.3
5.0
3.0
2.0
3.5
2.5
4.0
3.0
Clock Pulse Width (Count)
HIGH or LOW
3.3
5.0
3.0
2.0
4.0
3.0
4.5
3.5
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
http://onsemi.com
7
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
DC CHARACTERISTICS
74ACT
74ACT
T
=
A
V
(V)
CC
T
A
= +25°C
−40°C to
+85°C
Symbol
Parameter
Unit
Conditions
Typ
Guaranteed Limits
V
V
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V − 0.1 V
CC
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
OUT
= 0.1 V
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= −50 mA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IH
IN
IL
4.5
5.5
−
−
3.86
4.86
3.76
4.76
V
V
V
−24 mA
−24 mA
I
I
OH
V
OL
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
= 50 mA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN
IL
IH
4.5
5.5
−
−
0.36
0.36
0.44
0.44
24 mA
24 mA
I
OL
I
IN
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
mA
V = V , GND
I CC
DI
Additional Max. I /Input
5.5
5.5
5.5
0.6
−
−
−
−
1.5
75
mA
mA
mA
V = V − 2.1 V
CCT
CC
I
CC
I
V
OLD
V
OHD
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
I
−
−75
= 3.85 V Min
OHD
CC
I
Maximum Quiescent
Supply Current
5.5
−
8.0
80
mA
V = V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
http://onsemi.com
8
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT161
74ACT161
T
= −40°C
A
T
= +25°C
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Min
Typ
Max
Min
Max
Maximum Count
Frequency
f
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
115
125
−
100
−
MHz
ns
3−3
3−6
3−6
3−6
3−6
3−6
3−6
3−6
3−6
max
Propagation Delay
1.5
1.5
2.0
1.5
1.5
1.5
1.5
2.5
8.0
8.0
9.5
10.5
11.0
12.5
8.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
10.5
11.5
12.5
13.5
10.0
10.5
11.0
14.5
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PHL
CP to Q (PE Input HIGH or LOW)
n
Propagation Delay
ns
CP or Q (PE Input HIGH or LOW)
n
Propagation Delay
CP to TC
11.0
11.0
7.5
ns
Propagation Delay
CP to TC
ns
Propagation Delay
CET to TC
ns
Propagation Delay
CET to TC
8.0
9.5
ns
Propagation Delay
8.0
10.0
13.5
ns
MR to Q
n
Propagation Delay
MR to TC
10.0
ns
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT163 74ACT163
= −40°C
T
A
T
A
= +25°C
V
CC
*
Fig.
No.
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
(V)
L
Min
Typ
Max
Min
Max
Maximum Count
Frequency
f
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
120
140
−
105
−
MHz
ns
3−3
3−6
3−6
3−6
3−6
3−6
3−6
max
Propagation Delay
1.5
1.5
2.5
3.0
2.0
2.0
5.5
6.0
7.0
8.0
5.5
6.0
10.0
11.0
11.5
13.5
9.0
1.5
1.5
2.0
2.0
1.5
2.0
11.0
12.0
13.5
15.0
10.5
11.0
PLH
PHL
PLH
PHL
PLH
PHL
CP to Q (PE Input HIGH or LOW)
n
Propagation Delay
ns
CP to Q (PE Input HIGH or LOW)
n
Propagation Delay
CP to TC
ns
Propagation Delay
CP to TC
ns
Propagation Delay
CET to TC
ns
Propagation Delay
CET to TC
10.0
ns
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
http://onsemi.com
9
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC OPERATING REQUIREMENTS
74ACT161
= +25°C
74ACT161
= −40°C
T
A
T
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
P to CP
n
t
t
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
7.0
9.5
0
11.5
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3−9
3−9
3−9
3−9
3−9
3−9
3−6
3−6
3−6
3−9
s
Hold Time, HIGH or LOW
P to CP
n
−3.0
6.0
−3.5
4.0
−2.0
2.0
2.0
3.0
0
h
s
Setup Time, HIGH or LOW
PE to CP
8.5
− 0.5
5.5
0
9.5
− 0.5
6.5
0
Hold Time, HIGH or LOW
PE to CP
h
s
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
h
w
w
w
Clock Pulse Width (Load)
HIGH or LOW
3.0
3.0
3.0
0
3.5
3.5
7.5
0.5
Clock Pulse Width (Count)
HIGH or LOW
MR Pulse Width, LOW
Recovery Time
MR to CP
rec
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
http://onsemi.com
10
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC OPERATING REQUIREMENTS
74ACT163
= +25°C
74ACT163
= −40°C
T
A
T
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
P to CP
n
t
t
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.0
10.0
0.5
12.0
0.5
11.5
−0.5
10.5
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3−9
3−9
3−9
3−9
3−9
3−9
3−9
3−9
3−6
3−6
s
Hold Time, HIGH or LOW
P to CP
n
−5.0
4.0
h
s
Setup Time, HIGH or LOW
SR to CP
10.0
−0.5
8.5
Hold Time, HIGH or LOW
SR to CP
−5.5
4.0
h
s
Setup Time, HIGH or LOW
PE to CP
Hold Time, HIGH or LOW
PE to CP
−5.5
2.5
−0.5
5.5
h
s
Setup Time, HIGH or LOW
CEP or CET to CP
6.5
0.5
3.5
3.5
Hold Time, HIGH or LOW
CEP or CET to CP
−3.0
2.0
0
h
w
w
Clock Pulse Width
HIGH or LOW
3.5
Clock Pulse Width (Count)
HIGH or LOW
2.0
3.5
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Value
Parameter
Unit
Test Conditions
Typ
4.5
45
C
C
Input Capacitance
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
Power Dissipation Capacitance
PD
CC
MARKING DIAGRAMS
DIP−16
SO−16
EIAJ−16
MC74AC16xN
AWLYYWW
AC16x
AWLYWW
74AC16x
ALYW
ACT16x
AWLYWW
MC74ACT16xN
AWLYYWW
74ACT16x
ALYW
x
= 1 or 3
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
http://onsemi.com
11
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
ORDERING INFORMATION
Device
Package
PDIP−16
PDIP−16
SOIC−16
SOIC−16
SOIC−16
SOIC−16
EIAJ−16
EIAJ−16
PDIP−16
PDIP−16
SOIC−16
SOIC−16
SOIC−16
SOIC−16
EIAJ−16
EIAJ−16
Shipping
25 Units/Rail
MC74AC161N
MC74ACT161N
MC74AC161D
25 Units/Rail
48 Units/Rail
MC74AC161DR2
MC74ACT161D
MC74ACT161DR2
MC74AC161M
2500 Tape & Reel
48 Units/Rail
2500 Tape & Reel
50 Units/Rail
MC74ACT161MEL
MC74AC163N
2000 Tape & Reel
25 Units/Rail
MC74ACT163N
MC74AC163D
25 Units/Rail
48 Units/Rail
MC74AC163DR2
MC74ACT163D
MC74ACT163DR2
MC74AC163MEL
MC74ACT163MEL
2500 Tape & Reel
48 Units/Rail
2500 Tape & Reel
2000 Tape & Reel
2000 Tape & Reel
http://onsemi.com
12
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
16 PIN PLASTIC DIP PACKAGE
CASE 648−08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
SEATING
PLANE
−T−
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
K
L
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
_
_
_
_
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
SO−16
D SUFFIX
16 PIN PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
G
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
R X 45
K
_
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
C
G
J
1.27 BSC
0.050 BSC
−T−
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
7
0
_
_
_
_
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
A
0.25 (0.010)
T
B
http://onsemi.com
13
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
PACKAGE DIMENSIONS
EIAJ−16
M SUFFIX
16 PIN PLASTIC EIAJ PACKAGE
CASE966−01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE O
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
16
9
E
Q
1
H
E
M
_
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN
−−−
A
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
−−−
0.05
0.35
0.18
9.90
5.10
2.05
A
1
0.20 0.002
0.50 0.014
0.27 0.007
b
c
D
E
10.50 0.390
5.45 0.201
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
_
0.035
0.031
0
_
_
_
0.70
−−−
1
Z
0.78
−−−
http://onsemi.com
14
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
Notes
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC74AC161/D
相关型号：
MC74AC161DCR1
Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, PLASTIC, SOIC-16
MOTOROLA
MC74AC161DG
Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, PLASTIC, SOIC-16
ROCHESTER
MC74AC161DR2
AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, PLASTIC, SOIC-16
MOTOROLA
MC74AC161DT
IC AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, PLASTIC, TSSOP-16, Counter
ONSEMI
MC74AC161DTR2
IC AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, PLASTIC, TSSOP-16, Counter
ONSEMI
MC74AC161DW
AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, PLASTIC, SOIC-16
ONSEMI
©2020 ICPDF网 联系我们和版权申明