MC74AC373NG [ONSEMI]
Octal Transparent Latch with 3−State Outputs; 八路透明锁存器具有三态输出
| 型号： | MC74AC373NG |
| 厂家： | 
ONSEMI |
| 描述： | Octal Transparent Latch with 3−State Outputs |
| 文件： | 总12页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC373, MC74ACT373
Octal Transparent Latch
with 3−State Outputs
The MC74AC373/74ACT373 consists of eight latches with 3−state
outputs for bus organized system applications. The flip−flops appear
transparent to the data when Latch Enable (LE) is HIGH. When LE is
LOW, the data that meets the setup time is latched. Data appears on the
bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
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Features
PDIP−20
• Eight Latches in a Single Package
• 3−State Outputs for Bus Interfacing
• Outputs Source/Sink 24 mA
N SUFFIX
CASE 738
1
• ′ACT373 Has TTL Compatible Inputs
• Pb−Free Packages are Available
SOIC−20W
DW SUFFIX
CASE 751D
V
O
D
D
O
O
D
D
O
4
LE
11
CC
7
7
6
6
5
5
4
1
20
19
18
17
16
15
14
12
13
TSSOP−20
DT SUFFIX
CASE 948E
1
1
2
3
4
5
6
7
9
8
10
OE
O
D
D
O
O
D
D
O
3
GND
0
0
1
1
2
2
3
Figure 1. Pinout: 20−Lead Packages Conductors
SOEIAJ−20
M SUFFIX
CASE 967
(Top View)
1
PIN ASSIGNMENT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
PIN
FUNCTION
dimensions section on page 8 of this data sheet.
D −D
Data Inputs
0
7
LE
Latch Enable Input
Output Enable Input
3−State Latch Outputs
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
OE
O −O
0
7
D
D
D
D
D
D
D
D
6 7
0
1
2
3
4
5
LE
OE
O
O O O O O O O
1 2 3 4 5 6 7
0
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 8
MC74AC373/D
MC74AC373, MC74ACT373
FUNCTIONAL DESCRIPTION
TRUTH TABLE
The MC74AC373/74ACT373 contains eight D−type
latches with 3−state standard outputs. When the Latch
Inputs
Outputs
OE
LE
D
O
n
n
Enable (LE) input is HIGH, data on the D inputs enters the
n
H
L
L
L
X
H
H
L
X
Z
L
H
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGH−to−LOW transition of LE. The 3-state standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2−state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
L
H
X
O
0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O before LOW-to-HIGH Transition of Clock
0
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
D
D
D
D
D
D
D
D
O
O
O
O
O
O
O
O
G
G
G
G
G
G
G
G
LE
OE
NOTE: This diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2
MC74AC373, MC74ACT373
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
CC
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to V +0.5
V
IN
CC
V
−0.5 to V +0.5
V
OUT
CC
I
20
50
mA
mA
mA
°C
IN
I
DC Output Sink/Source Current, per Pin
OUT
I
DC V or GND Current per Output Pin
50
CC
CC
T
stg
Storage Temperature
−65 to +150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
−
Max
6.0
Unit
′AC
V
Supply Voltage
V
V
CC
′ACT
5.5
V
, V
IN
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
OUT
V
V
V
V
V
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
−
150
40
25
10
8.0
−
−
CC
CC
CC
CC
CC
Input Rise and Fall Time (Note 1)
−
−
−
−
−
ns/V
t , t
r
f
′AC Devices except Schmitt Inputs
−
−
Input Rise and Fall Time (Note 2)
t , t
r
ns/V
f
′ACT Devices except Schmitt Inputs
−
T
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
−
140
85
°C
°C
J
T
A
−40
−
25
−
I
−24
24
mA
mA
OH
I
Output Current − Low
−
−
OL
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
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3
MC74AC373, MC74ACT373
DC CHARACTERISTICS
Symbol
74AC
74AC
T
A
=
V
(V)
CC
T
A
= +25°C
Parameter
Unit
Conditions
−40°C to +85°C
Typ
Guaranteed Limits
V
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
= 0.1 V
OUT
Minimum High Level
IH
V
V
V
or V − 0.1 V
CC
Input Voltage
V
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
= 0.1 V
OUT
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
V
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= −50 mA
OUT
Minimum High Level
Output Voltage
OH
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
−12 mA
−24 mA
−24 mA
V
V
I
I
OH
V
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
= 50 mA
OUT
Maximum Low Level
Output Voltage
OL
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
24 mA
24 mA
V
I
OL
I
Maximum Input
Leakage Current
IN
5.5
−
0.1
1.0
mA
V = V , GND
I CC
I
V (OE) = V , V
I IL IH
Maximum
3−State
Current
OZ
5.5
5.5
−
−
0.5
−
5.0
75
mA
V = V , GND
I
CC
V
= V , GND
O
CC
I
mA
V
= 1.65 V
OLD
†Minimum Dynamic
Output Current
OLD
Max
I
5.5
5.5
−
−
−
−75
80
mA
V
V
= 3.85 V Min
OHD
OHD
I
Maximum Quiescent
Supply Current
CC
8.0
mA
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
I
and I @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
IN
CC
CC
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4
MC74AC373, MC74ACT373
AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
74AC
74AC
T
= −40°C
A
Fig.
No.
T
C
= +25°C
= 50 pF
V
(V)
*
A
CC
to +85°C
C
Symbol
Parameter
Unit
L
= 50 pF
L
Min
Typ
Max
Min
Max
Propagation Delay
D to O
3.3
5.0
1.5
1.5
10
7.0
13.5
9.5
1.5
1.5
15
10.5
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
3−5
3−5
3−6
3−6
3−7
3−8
3−7
3−8
PLH
PHL
PLH
PHL
PZH
n
n
Propagation Delay
D to O
3.3
5.0
1.5
1.5
9.5
7.0
13
9.5
1.5
1.5
14.5
10.5
n
n
Propagation Delay
LE to O
3.3
5.0
1.5
1.5
10
7.5
13.5
9.5
1.5
1.5
15
10.5
n
Propagation Delay
LE to O
3.3
5.0
1.5
1.5
9.5
7.0
12.5
9.5
1.5
1.5
14
10.5
n
3.3
5.0
1.5
1.5
9.0
7.0
11.5
8.5
1.0
1.0
13
9.5
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
3.3
5.0
1.5
1.5
8.5
6.5
11.5
8.5
1.0
1.0
13
9.5
t
PZL
3.3
5.0
1.5
1.5
10
8.0
12.5
11
1.0
1.0
14.5
12.5
t
PHZ
3.3
5.0
1.5
1.5
8.0
6.5
11.5
8.5
1.0
1.0
12.5
10
t
PLZ
*Voltage Range 3.3 V is 3.3 V 0.3 V.
Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74AC
74AC
= −40°C
T
A
Fig.
No.
T
C
= +25°C
= 50 pF
V
(V)
*
A
CC
to +85°C
= 50 pF
Symbol
Parameter
Unit
L
C
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
D to LE
n
3.3
5.0
3.5
2.0
5.5
4.0
6.0
4.5
t
t
ns
ns
ns
3−9
3−9
3−6
s
Hold Time, HIGH or LOW
D to LE
n
3.3
5.0
−3.0
−1.5
1.0
1.0
1.0
1.0
h
3.3
5.0
4.0
2.0
5.5
4.0
6.0
4.5
t
LE Pulse Width, HIGH
w
*Voltage Range 3.3 V is 3.3 V 0.3 V.
Voltage Range 5.0 V is 5.0 V 0.5 V.
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5
MC74AC373, MC74ACT373
DC CHARACTERISTICS
Symbol
74ACT
74ACT
T
A
=
V
(V)
CC
T
= +25°C
Parameter
Unit
Conditions
A
−40°C to +85°C
Typ
Guaranteed Limits
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
OUT
Minimum High Level
IH
V
V
V
or V − 0.1 V
CC
Input Voltage
V
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
= 0.1 V
OUT
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
V
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= −50 mA
OUT
Minimum High Level
Output Voltage
OH
*V = V or V
IN
IL
IH
IH
4.5
5.5
−
−
3.86
4.86
3.76
4.76
V
V
V
−24 mA
I
OH
−24 mA
V
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
I
= 50 mA
OUT
Maximum Low Level
Output Voltage
OL
*V = V or V
IN
IL
4.5
5.5
−
−
0.36
0.36
0.44
0.44
24 mA
24 mA
I
OL
I
Maximum Input
Leakage Current
IN
5.5
5.5
−
0.1
−
1.0
1.5
mA
V = V , GND
I CC
DI
Additional Max. I /Input
0.6
mA
V = V − 2.1 V
I CC
CCT
CC
I
V (OE) = V , V
I IL IH
Maximum
3-State
OZ
5.5
−
0.5
5.0
mA
V = V , GND
I
CC
V
V
V
= V , GND
Current
O
CC
I
5.5
5.5
−
−
−
−
75
mA
mA
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
OLD
I
−75
= 3.85 V Min
OHD
OHD
I
Maximum Quiescent
Supply Current
CC
5.5
−
8.0
80
mA
V
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
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6
MC74AC373, MC74ACT373
AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
74ACT
74ACT
T
= −40°C
A
Fig.
No.
T
C
= +25°C
= 50 pF
V
(V)
*
A
CC
to +85°C
C
Symbol
Parameter
Unit
L
= 50 pF
L
Min
Typ
Max
Min
Max
Propagation Delay
D to O
t
t
t
5.0
5.0
5.0
5.0
2.5
8.5
10
1.5
11.5
11.5
11.5
11.5
ns
ns
ns
ns
3−5
3−5
3−6
3−6
PLH
PHL
PLH
n
n
Propagation Delay
D to O
2.0
2.5
2.0
8.0
8.5
8.0
10
11
10
1.5
2.0
1.5
n
n
Propagation Delay
LE to O
n
Propagation Delay
LE to O
t
t
PHL
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
2.0
2.5
1.5
8.0
7.5
9.0
7.5
9.5
9.0
11
1.5
1.5
2.5
1.0
10.5
10.5
12.5
10
ns
ns
ns
ns
3−7
3−8
3−7
3−8
PZH
t
PZL
PHZ
t
t
8.5
PLZ
*Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
74ACT
74ACT
T
= −40°C
A
Fig.
No.
T
C
= +25°C
= 50 pF
V
(V)
*
A
CC
to +85°C
C
Symbol
Parameter
Unit
L
= 50 pF
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
t
t
5.0
3.0
7.0
8.0
ns
3−9
s
D to LE
n
Hold Time, HIGH or LOW
5.0
5.0
0
0
1.0
8.0
ns
ns
3−9
3−6
h
D to LE
n
t
LE Pulse Width, HIGH
2.0
7.0
w
*Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Value
Typ
Symbol
Parameter
Unit
Test Conditions
C
Input Capacitance
4.5
40
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
CC
C
PD
Power Dissipation Capacitance
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7
MC74AC373, MC74ACT373
ORDERING INFORMATION
Device
†
Package
Shipping
MC74AC373N
PDIP−20
MC74AC373NG
PDIP−20
(Pb−Free)
18 Units / Rail
MC74ACT373N
PDIP−20
MC74ACT373NG
PDIP−20
(Pb−Free)
MC74AC373DW
SOIC−20
38 Units / Rail
1000 / Tape & Reel
38 Units / Rail
MC74AC373DWG
SOIC−20
(Pb−Free)
MC74AC373DWR2
MC74AC373DWR2G
SOIC−20
SOIC−20
(Pb−Free)
MC74ACT373DW
MC74ACT373DWG
SOIC−20
SOIC−20
(Pb−Free)
MC74ACT373DWR2
MC74ACT373DWR2G
SOIC−20
1000 / Tape & Reel
SOIC−20
(Pb−Free)
MC74AC373DT
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
SOEIAJ−20
75 Units / Rail
2500 / Tape & Reel
75 Units / Rail
MC74AC373DTG
MC74AC373DTR2
MC74AC373DTR2G
MC74ACT373DT
MC74ACT373DTG
MC74ACT373DTR2
MC74ACT373DTR2G
MC74AC373MEL
MC74AC373MELG
2500 / Tape & Reel
2000 / Tape & Reel
2000 / Tape & Reel
SOEIAJ−20
(Pb−Free)
MC74ACT373MEL
MC74ACT373MELG
SOEIAJ−20
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*These packages are inherently Pb−Free.
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8
MC74AC373, MC74ACT373
MARKING DIAGRAMS
PDIP−20
SOIC−20W
TSSOP−20
SOEIAJ−20
20
20
20
1
20
1
AC
373
AC373
AWLYYWWG
MC74AC373N
AWLYYWWG
74AC373
AWLYWWG
ALYWG
G
1
1
20
20
20
1
20
1
ACT
373
ACT373
AWLYYWWG
74ACT373
AWLYWWG
MC74ACT373N
AWLYYWWG
ALYWG
G
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
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9
MC74AC373, MC74ACT373
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
MILLIMETERS
L
C
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
1.070
0.260
0.180
0.022
0.050 BSC
1.27 BSC
−T−
SEATING
PLANE
K
0.050
0.070
1.27
1.77
G
J
0.100 BSC
2.54 BSC
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
J 20 PL
_
_
_
D 20 PL
M
M
T B
0.25 (0.010)
M
M
T A
0.25 (0.010)
SOIC−20W
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
MILLIMETERS
1
10
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
0.25
T A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
http://onsemi.com
10
MC74AC373, MC74ACT373
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
20X K REF
K
M
S
S
V
0.10 (0.004)
T U
S
K1
0.15 (0.006) T U
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
MC74AC373, MC74ACT373
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
20
11
E
Q
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
1
H
E
E
_
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.25
12.80
5.45
A
−−−
0.05
A
1
A
b
1
0.002
0.008
0.020
0.010
0.504
0.215
b
c
0.35
0.15
0.014
0.006
0.486
0.201
M
0.10 (0.004)
0.13 (0.005)
D
E
e
12.35
5.10
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
10
0.035
0
0.028
_
_
_
_
0.70
−−−
0.90
0.81
1
Z
−−− 0.032
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MC74AC373/D
相关型号：
MC74AC374DWCR2
Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, PLASTIC, SOIC-20
MOTOROLA
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