MC74AC377MEL [ONSEMI]
Octal D Flip-Flop with Clock Enable; 八路D触发器与时钟使能
| 型号： | MC74AC377MEL |
| 厂家： | 
ONSEMI |
| 描述： | Octal D Flip-Flop with Clock Enable |
| 文件： | 总12页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC377, MC74ACT377
Octal D Flip-Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
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PDIP–20
N SUFFIX
CASE 738
20
• Ideal for Addressable Register Applications
• Clock Enable for Address and Data Synchronization Applications
• Eight Edge-Triggered D Flip-Flops
1
SO–20
DW SUFFIX
CASE 751
• Buffered Common Clock
20
1
• Outputs Source/Sink 24 mA
• See MC74AC273 for Master Reset Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• ACT377 Has TTL Compatible Inputs
• MSL = 1 for all Surface Mount
TSSOP–20
DT SUFFIX
CASE 948E
20
1
EIAJ–20
M SUFFIX
CASE 967
• Chip Complexity: 292 FETS or 73 Gates
20
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 8 of this data sheet.
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
May, 2001 – Rev.6
MC74AC377/D
MC74AC377, MC74ACT377
V
O
D
D
O
O
D
D
O
4
CP
11
CC
7
7
6
6
5
5
4
20
19
18
17
16
15
14
12
13
D
D
O
D
O
D
O
D
O
D
O
D
O
D
O
0
1
2
3
4
5
6
7
CP
CE
O
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
9
8
10
CE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
Figure 2. LOGIC SYMBOL
Figure 1. Pinout: 20–Lead Packages Conductors
(Top View)
PIN NAMES
MODE SELECT-FUNCTION TABLE
PIN
FUNCTION
Inputs
Outputs
Operating Mode
CP
CE
L
D
Q
n
D –D
0
Data Inputs
n
7
Load ′1′
Load ′0′
H
H
CE
Clock Enable (Active LOW)
Data Outputs
L
L
L
Q –Q
0
7
H
H
X
X
No Change
No Change
Hold (Do Nothing)
X
CP
Clock Pulse Input
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
D
D
D
D
D
D
D
6
D
7
0
1
2
3
4
5
CE
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
CP
O
O
O
O
O
O
O
O
7
0
1
2
3
4
5
6
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. LOGIC DIAGRAM
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2
MC74AC377, MC74ACT377
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
V
DC Supply Voltage (Referenced to GND)
–0.5 to +7.0
CC
in
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
–0.5 to V
+0.5
V
CC
V
out
–0.5 to V
+0.5
V
CC
I
I
I
±20
mA
mA
mA
°C
in
DC Output Sink/Source Current, per Pin
±50
±50
out
CC
DC V
CC
or GND Current per Output Pin
T
stg
Storage Temperature
–65 to +150
θ
Thermal Resistance (Junction to Ambient)
SOIC, DW
TSSOP, DT
PDIP, N
97
129
69
°C/W
JA
V
ESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
> 2000
> 200
V
Charged Device Model (Note 3)
> 1000
I
Latch–Up Performance
V
= 5.5 V; TA = 125°C (Note 4)
CC
> 100
mA
Latch–Up
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
1. Tested to EIA/JESD22–A114–A
2. Tested to EIA/JESD22–A115–A
3. Tested to JESD22–C101–A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
Max
6.0
Unit
′AC
V
Supply Voltage
V
V
CC
′ACT
5.5
V , V
in out
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
150
40
Input Rise and Fall Time (Note 5)
′AC Devices except Schmitt Inputs
ns/V
t , t
r f
25
10
Input Rise and Fall Time (Note 6)
′ACT Devices except Schmitt Inputs
t , t
r f
ns/V
8.0
T
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current — High
140
85
°C
°C
J
T
A
–40
25
I
I
–24
24
mA
mA
OH
Output Current — Low
OL
5. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
CC
6. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
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3
MC74AC377, MC74ACT377
74AC – DC CHARACTERISTICS
T
A
= +25°C
T =
A
–40°C to +85°C
Typ
Guaranteed Limits
Symbol
Parameter
V
CC
(V)
Unit
Conditions
V
V
V
Minimum High Level Input Voltage
3.0
4.5
5.5
1.50
2.25
2.75
2.10
3.15
3.85
2.10
3.15
3.85
V
V
V
V
= 0.1 V
IH
OUT
or
– 0.1 V
V
V
CC
Maximum Low Level Input Voltage
Minimum High Level Output Voltage
3.0
4.5
5.5
1.50
2.25
2.75
0.90
1.35
1.65
0.90
1.35
1.65
V
V
V
= 0.1 V
OUT
IL
or
– 0.1 V
V
CC
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
V
V
I
= –50 µA
OH
OUT
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
V
V
V
*V = V or V
–12 mA
–24 mA
–24 mA
IN
IL
IH
I
OH
V
OL
Maximum Low Level Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
I = 50 µA
OUT
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
V
V
V
*V = V or V
IN IL
OH
–12 mA
–24 mA
–24 mA
IH
I
I
Maximum Input Leakage Current
Maximum Input Leakage Current
5.5
±0.1
±1.0
µA
V = V , GND
IN
I
CC
I
I
5.5
5.5
75
–75
mA
mA
V
V
= 1.65 V Max
= 3.85 V Min
OLD
OHD
OLD
OHD
I
Maximum Quiescent Supply Current
5.5
8.0
80
µA
V
IN
= V or GND
CC
CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
I
IN
and I
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
CC
CC
74AC – AC CHARACTERISTICS For Figures and Waveforms, See Figures 4, 5, and 6.
T
C
= +25°C
= 50 pF
T = –40°C to +85°C
A
A
L
C = 50 pF
L
Min
Typ
Max
Min
Max
Symbol
Parameter
V
CC
* (V)
Unit
3.3
5.0
90
140
75
125
f
t
t
Maximum Clock Frequency
MHz
max
PLH
PHL
3.3
5.0
3.0
2.0
13.0
9.0
1.5
1.5
14.0
10.0
Propagation Delay
Propagation Delay
CP to Q
CP to Q
ns
ns
n
n
3.3
5.0
3.5
2.5
13.0
10.0
2.0
1.5
14.5
11.0
* Voltage Range 3.3 V is 3.3 V ±0.3 V; Voltage Range 5.0 V is 5.0 V ±0.5 V.
74AC – AC OPERATING REQUIREMENTS
T
C
= +25°C
= 50 pF
T = –40°C to +85°C
A
A
L
Typ
Guaranteed Minimum
Symbol
Parameter
V
CC
* (V)
Unit
3.3
5.0
5.5
4.0
6.0
4.5
ns
t
t
t
t
t
Setup Time, HIGH or LOW
D
D
to CP
to CP
s
n
3.3
5.0
0
1.0
0
1.0
ns
ns
ns
Hold Time, HIGH or LOW
Setup Time, HIGH or LOW
Hold Time, HIGH or LOW
CP Pulse Width
h
s
n
3.3
5.0
6.0
4.0
7.5
4.5
CE to CP
CE to CP
3.3
5.0
0
1.0
0
1.0
h
w
3.3
5.0
5.5
4.0
6.0
4.5
HIGH or LOW
ns
* Voltage Range 3.3 V is 3.3 V ±0.3 V; Voltage Range 5.0 V is 5.0 V ±0.5 V.
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4
MC74AC377, MC74ACT377
74ACT – DC CHARACTERISTICS
T
A
=
T
= +255C
A
–405C to +855C
Symbol
Parameter
V
CC
(V)
Unit
Conditions
Typ
Guaranteed Limits
V
V
V
Minimum High Level Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
IH
OUT
or
– 0.1 V
V
V
V
CC
Maximum Low Level Input Voltage
Minimum High Level Output Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
= 0.1 V
OUT
IL
V
or
– 0.1 V
V
CC
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= –50 µA
V
V
V
V
OH
OUT
4.5
5.5
3.86
4.86
3.76
4.76
*V = V or V
–24 mA
–24 mA
IN
IL
IH
I
OH
V
OL
Maximum Low Level Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
I = 50 µA
OUT
4.5
5.5
0.36
0.36
0.44
0.44
*V = V or V
IN IL
–24 mA
–24 mA
IH
I
OH
I
Maximum Input Leakage Current
5.5
5.5
5.5
±0.1
±1.0
µA
V = V , GND
IN
I
CC
∆I
Additional Max. I /Input
CC
0.6
1.5
mA
V = V
– 2.1 V
CCT
I
CC
I
I
†Minimum Dynamic Output Current
75
–75
V
OLD
V
OHD
= 1.65 V Max
= 3.85 V Min
OLD
OHD
mA
I
Maximum Quiescent Supply Current
5.5
8.0
80
µA
V
IN
= V or GND
CC
CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
74ACT – AC CHARACTERISTICS For Figures and Waveforms — See Figures 4, 5, and 6.
T
A
= +25°C
T = –40°C to +85°C
A
C
= 50 pF
C = 50 pF
L
L
Symbol
Parameter
V
CC
* (V)
Unit
Min
Typ
Max
Min
Max
f
t
t
Maximum Clock Frequency
Propagation Delay
5.0
140
3.0
3.5
125
2.5
2.5
MHz
ns
max
PLH
PHL
CP to Q
CP to Q
5.0
5.0
9.0
10
10
11
n
n
Propagation Delay
ns
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
74ACT – AC OPERATING REQUIREMENTS
T
C
= +25°C
= 50 pF
T = –40°C to +85°C
A
A
L
C = 50 pF
L
Symbol
Parameter
Setup Time, HIGH or LOW
V
CC
* (V)
Unit
Typ
Guaranteed Minimum
t
t
t
t
t
D
D
to CP
to CP
5.0
4.5
1.0
5.5
1.0
5.5
1.0
4.5
ns
ns
ns
ns
ns
s
n
Hold Time, HIGH or LOW
Setup Time, HIGH or LOW
Hold Time, HIGH or LOW
CP Pulse Width
5.0
5.0
5.0
5.0
h
s
n
CE to CP
CE to CP
4.5
1.0
4.0
h
w
HIGH or LOW
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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5
MC74AC377, MC74ACT377
CAPACITANCE
Symbol
Value
Parameter
Unit
Test Conditions
Typ
4.5
90
C
C
Input Capacitance
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
Power Dissipation Capacitance
PD
CC
SWITCHING WAVEFORMS
t
r
t
f
V
CC
V
CC
50%
CE
CLOCK
50%
GND
t
w
t
su
t
h
1/f
max
V
CC
t
t
PHL
CLOCK
50%
PLH
GND
Q
50%
Figure 4.
Figure 5.
VALID
V
CC
DATA
50%
t
GND
t
h
su
V
CC
CLOCK
50%
GND
Figure 6.
450 W
OUTPUT
50 W SCOPE
DEVICE
TEST POINT
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 7. Test Circuit
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6
MC74AC377, MC74ACT377
ORDERING INFORMATION
Device
MC74AC377N
Package
PDIP–20
PDIP–20
SOIC–20
SOIC–20
SOIC–20
SOIC–20
TSSOP–20
TSSOP–20
TSSOP–20
TSSOP–20
EIAJ–20
Shipping
18 Units/Rail
MC74ACT377N
18 Units/Rail
MC74AC377DW
MC74AC377DWR2
MC74ACT377DW
MC74ACT377DWR2
MC74AC377DT
38 Units/Rail
1000 Tape & Reel
38 Units/Rail
1000 Tape & Reel
75 Units/Rail
MC74AC377DTR2
MC74ACT377DT
MC74ACT377DTR2
MC74AC377M
2500 Tape & Reel
75 Units/Rail
2500 Tape & Reel
40 Units/Rail
MC74AC377MEL
MC74ACT377M
MC74ACT377MEL
EIAJ–20
2000 Tape & Reel
40 Units/Rail
EIAJ–20
EIAJ–20
2000 Tape & Reel
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7
MC74AC377, MC74ACT377
MARKING DIAGRAMS
PDIP–20
SO–20
TSSOP–20
EIAJ–20
AC377
AWLYYWW
MC74AC377N
AWLYYWW
74AC377
AWLYWW
AC
377
ALYW
ACT377
AWLYYWW
MC74ACT377N
AWLYYWW
74ACT377
AWLYWW
ACT
377
ALYW
A
= Assembly Location
WL, L
YY, Y
= Wafer Lot
= Year
WW, W = Work Week
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8
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
20 PIN PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
L
C
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
–T–
SEATING
PLANE
K
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
N
E
G
J
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
K
L
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
M
M
T B
0.25 (0.010)
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.01
_
M
M
0.25 (0.010)
T A
SO–20
DW SUFFIX
20 PIN PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
20
11
E
10
1
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
B
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
T
0.25
A
B
e
1.27 BSC
A
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
q
_
_
18X e
A1
C
T
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9
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
ąă4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
ąă5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
ąă6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
ąă7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
---
6.60 0.252
4.50 0.169
N
C
1.20
---
D
0.05
0.50
0.15 0.002
0.75 0.020
F
F
G
H
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
J1
K
C
K1
L
6.40 BSC
0.252 BSC
0
G
D
M
0
8
8
_
_
_
_
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
EIAJ–20
M SUFFIX
20 PIN PLASTIC EIAJ PACKAGE
CASE 967–01
ISSUE O
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
20
11
Q
1
ąă4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ąă5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
---
e
A
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.504
0.215
c
A
---
0.05
0.35
0.18
12.35
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
1
b
c
D
E
e
12.80 0.486
5.45 0.201
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
0
10
0.90 0.028
10
_
0.035
0.032
0
_
_
_
Q
0.70
---
1
Z
0.81
---
http://onsemi.com
10
MC74AC377, MC74ACT377
Notes
http://onsemi.com
11
MC74AC377, MC74ACT377
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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MC74AC377/D
相关型号：
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AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20, LEAD FREE, PLASTIC, DIP-20
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MC74AC378DR2
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