MC74ACT374DWR2 [ONSEMI]
Octal D−Type Flip−Flop with 3−State Outputs; 八路D型触发器具有三态输出型号: | MC74ACT374DWR2 |
厂家: | ONSEMI |
描述: | Octal D−Type Flip−Flop with 3−State Outputs |
文件: | 总10页 (文件大小:116K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74AC374, MC74ACT374
Octal D−Type Flip−Flop with
3−State Outputs
The MC74AC374/74ACT374 is a high−speed, low−power octal
D−type flip−flop featuring separate D−type inputs for each flip−flop
and 3−state outputs for bus−oriented applications. A buffered Clock
(CP) and Output Enable (OE) are common to all flip−flops.
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Features
• Buffered Positive Edge−Triggered Clock
• 3−State Outputs for Bus−Oriented Applications
• Outputs Source/Sink 24 mA
PDIP−20
N SUFFIX
CASE 738
1
• See MC74AC273 for Reset Version
• See MC74AC377 for Clock Enable Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC574 for Broadside Pinout Version
• See MC74AC564 for Broadside Pinout Version with Inverted
Outputs
SOIC−20W
DW SUFFIX
CASE 751D
1
• ′ACT374 Has TTL Compatible Inputs
• Pb−Free Packages are Available
TSSOP−20
DT SUFFIX
CASE 948E
V
O
D
D
O
O
D
D
O
4
CP
11
CC
7
7
6
6
5
5
4
1
20
19
18
17
16
15
14
12
13
SOEIAJ−20
M SUFFIX
CASE 967
1
1
2
3
4
5
6
7
9
8
10
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
OE
O
D
D
O
O
D
D
O
3
GND
0
0
1
1
2
2
3
Figure 1. Pinout: 20 Lead Packages Conductors
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
PIN ASSIGNMENT
PIN
FUNCTION
D −D
Data Inputs
0
7
D
D
D
D
D
D
D
D
6 7
0
1
2
3
4
5
CP
Clock Pulse Input
3−State Output Enable Input
3−State Outputs
CP
OE
OE
O
O
O
O O O O O
2 3 4 5 6 7
0
1
O −O
0
7
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
MC74AC374/D
November, 2006 − Rev. 8
MC74AC374, MC74ACT374
FUNCTIONAL DESCRIPTION
TRUTH TABLE
The MC74AC374/74ACT374 consists of eight edge−
triggered flip−flops with individual D−type inputs and
3−state true outputs. The buffered clock and buffered Output
Enable are common to all flip−flops. The eight flip−flops
will store the state of their individual D inputs that meet the
setup and hold time requirements on the LOW−to−HIGH
Clock (CP) transition. With the Output Enable (OE) LOW,
the contents of the eight flip−flops are available at the
outputs. When the OE is HIGH, the outputs go to the high
impedance state. Operation of the OE input does not affect
the state of the flip−flops.
Inputs
Outputs
D
CP
OE
O
n
n
H
L
X
L
L
H
H
L
Z
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
CP
CP
Q
D
Q
CP
Q
D
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
Q
OE
O
O
O
O
O
O
O
O
7
0
1
2
3
4
5
6
NOTE: That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to +7.0
V
CC
V
−0.5 to V +0.5
V
IN
CC
V
−0.5 to V +0.5
V
OUT
CC
I
20
50
mA
mA
mA
°C
IN
I
DC Output Sink/Source Current, per Pin
OUT
I
DC V or GND Current per Output Pin
50
CC
CC
T
stg
Storage Temperature
−65 to +150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC74AC374, MC74ACT374
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
V
′AC
2.0
5.0
6.0
V
Supply Voltage
CC
′ACT
4.5
0
5.0
5.5
V
, V
IN
DC Input Voltage, Output Voltage (Ref. to GND)
V
V
OUT
CC
V
V
V
V
V
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
−
150
40
25
10
8.0
−
−
CC
CC
CC
CC
CC
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
−
−
−
−
−
ns/V
t , t
r
f
−
−
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
t , t
r
ns/V
f
−
T
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
−
140
85
°C
°C
J
T
A
−40
−
25
−
I
−24
24
mA
mA
OH
I
Output Current − Low
−
−
OL
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
DC CHARACTERISTICS
74AC
74AC
V
(V)
CC
T
A
= +25°C
T
A
= −40°C to +85°C
Symbol
Parameter
Unit
Conditions
Typ
Guaranteed Limits
V
Minimum High Level
3.0
4.5
5.5
1.5
2.1
2.1
V
= 0.1 V
OUT
IH
Input Voltage
2.25
2.75
3.15
3.85
3.15
3.85
V
V
V
or V − 0.1 V
CC
V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
0.9
0.9
V
= 0.1 V
OUT
IL
2.25
2.75
1.35
1.65
1.35
1.65
or V − 0.1 V
CC
V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= −50 mA
OUT
OH
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
−12 mA
−24 mA
−24 mA
V
V
V
I
I
OH
V
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
= 50 mA
OUT
OL
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
24 mA
24 mA
I
OL
I
Maximum Input
Leakage Current
IN
5.5
5.5
−
−
0.1
0.5
1.0
5.0
mA
mA
V = V , GND
I CC
I
Maximum
3-State
V (OE) = V , V
I IL IH
OZ
V = V , GND
I
CC
Current
V
V
V
V
= V , GND
CC
O
I
†Minimum Dynamic
Output Current
5.5
5.5
5.5
−
−
−
−
−
75
−75
80
mA
mA
mA
= 1.65 V Max
= 3.85 V Min
OLD
OLD
I
OHD
OHD
I
Maximum Quiescent Supply Current
8.0
= V or GND
IN CC
CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
I
and I @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
IN
CC
CC
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3
MC74AC374, MC74ACT374
AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
74AC
74AC
T
= −40°C
A
Fig.
No.
T
C
= +25°C
= 50 pF
V
(V)
*
A
CC
to +85°C
C
Symbol
Parameter
Unit
L
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Clock
Frequency
3.3
5.0
60
100
110
155
−
−
60
100
−
−
f
MHz
ns
3−3
3−6
3−6
3−7
3−8
3−7
3−8
max
PLH
PHL
PZH
Propagation Delay
3.3
5.0
3.0
2.5
11
8.0
13.5
9.5
1.5
1.5
15.5
10.5
t
t
t
CP to O
n
Propagation Delay
CP to O
3.3
5.0
2.5
2.0
10
7.0
12.5
9.0
2.0
1.5
14
10
ns
n
3.3
5.0
3.0
2.0
9.5
7.0
11.5
8.5
1.5
1.0
13
9.5
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
ns
3.3
5.0
2.5
2.0
9.0
6.5
11.5
8.5
1.5
1.0
13
9.5
t
ns
PZL
PHZ
3.3
5.0
3.0
2.0
10.5
8.0
12.5
11
2.0
2.0
14.5
12.5
t
ns
3.3
5.0
2.0
1.5
8.0
6.5
11.5
8.5
1.0
1.0
12.5
10
t
ns
PLZ
*Voltage Range 3.3 V is 3.3 V 0.3 V.
Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74AC
74AC
T
= −40°C
A
Fig.
No.
T
C
= +25°C
= 50 pF
V
(V)
*
A
CC
to +85°C
C
Symbol
Parameter
Unit
L
= 50 pF
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
D to CP
n
3.3
5.0
2.0
1.0
5.5
4.0
6.0
4.5
t
t
ns
ns
ns
3−9
3−9
3−6
s
Hold Time, HIGH or LOW
D to CP
n
3.3
5.0
−1.0
0
1.0
1.5
1.0
1.5
h
CP Pulse Width
HIGH or LOW
3.3
5.0
4.0
2.5
5.5
4.0
6.0
4.5
t
w
*Voltage Range 3.3 V is 3.3 V 0.3 V.
Voltage Range 5.0 V is 5.0 V 0.5 V.
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4
MC74AC374, MC74ACT374
DC CHARACTERISTICS
74ACT
74ACT
T
=
V
(V)
A
CC
T
A
= +25°C
Symbol
Parameter
Unit
Conditions
−40°C to +85°C
Typ
Guaranteed Limits
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
OUT
Minimum High Level
Input Voltage
IH
V
V
V
or V − 0.1 V
CC
V
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
= 0.1 V
OUT
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
V
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= −50 mA
OUT
Minimum High Level
Output Voltage
OH
*V = V or V
IN
IL
IH
4.5
5.5
−
−
3.86
4.86
3.76
4.76
V
V
V
−24 mA
−24 mA
I
OH
V
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
I
= 50 mA
OUT
Maximum Low Level
Output Voltage
OL
*V = V or V
IN
IL
IH
4.5
5.5
−
−
0.36
0.36
0.44
0.44
24 mA
24 mA
I
OL
I
Maximum Input
Leakage Current
IN
5.5
5.5
−
0.1
−
1.0
1.5
mA
V = V , GND
I CC
DI
Additional Max. I /Input
0.6
mA
V = V − 2.1 V
I CC
CCT
CC
I
V (OE) = V , V
I IL IH
Maximum
3-State
OZ
5.5
−
0.5
5.0
mA
V = V , GND
I
CC
V
V
V
= V , GND
Current
O
CC
I
5.5
5.5
−
−
−
−
75
mA
mA
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
OLD
OHD
I
−75
= 3.85 V Min
OHD
I
Maximum Quiescent
Supply Current
CC
5.5
−
8.0
80
mA
V
= V or GND
IN
CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
74ACT
74ACT
= −40°C
T
A
Fig.
T
C
= +25°C
= 50 pF
V
(V)
*
A
CC
to +85°C
= 50 pF
Symbol
Parameter
Unit
L
No.
C
L
Min
Typ
Max
Min
Max
Maximum Clock
f
5.0
5.0
5.0
100
160
−
90
−
MHz
ns
3−3
3−6
3−6
max
Frequency
Propagation Delay
t
2.0
2.0
8.5
8.0
10
2.0
1.5
11.5
11
PLH
CP to O
n
Propagation Delay
CP to O
t
t
9.5
ns
PHL
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
1.5
1.5
1.5
8.0
8.0
8.5
7.0
9.5
9.0
1.5
1.5
1.0
1.0
10.5
10.5
12.5
10
ns
ns
ns
ns
3−7
3−8
3−7
3−8
PZH
t
PZL
PHZ
t
11.5
8.5
t
PLZ
*Voltage Range 5.0 V is 5.0 V 0.5 V.
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5
MC74AC374, MC74ACT374
AC OPERATING REQUIREMENTS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
74ACT
74ACT
T
= −40°C
A
Fig.
No.
T
C
= +25°C
= 50 pF
V
(V)
*
A
CC
to +85°C
C
Symbol
Parameter
Unit
L
= 50 pF
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
t
t
5.0
5.0
5.0
1.0
5.0
1.5
5.0
5.5
1.5
5.0
ns
ns
ns
3−9
3−9
3−6
s
D to CP
n
Hold Time, HIGH or LOW
0
h
D to CP
n
CP Pulse Width
HIGH or LOW
t
2.5
w
*Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Value
Typ
Symbol
Parameter
Unit
Test Conditions
C
Input Capacitance
4.5
80
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
CC
C
PD
Power Dissipation Capacitance
MARKING DIAGRAMS
PDIP−20
SOIC−20W
TSSOP−20
SOEIAJ−20
20
20
20
20
1
AC
374
AC374
AWLYYWWG
MC74AC374N
AWLYYWWG
74AC374
AWLYWWG
ALYWG
G
1
20
1
1
1
20
20
20
1
ACT
374
ACT374
AWLYYWWG
74ACT374
AWLYWWG
MC74ACT374N
AWLYYWWG
ALYWG
G
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
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6
MC74AC374, MC74ACT374
ORDERING INFORMATION
Device
†
Package
Shipping
MC74AC374N
PDIP−20
MC74AC374NG
PDIP−20
(Pb−Free)
18 Units / Rail
MC74ACT374N
PDIP−20
MC74ACT374NG
PDIP−20
(Pb−Free)
MC74AC374DW
SOIC−20
38 Units / Rail
1000 / Tape & Reel
38 Units / Rail
MC74AC374DWG
SOIC−20
(Pb−Free)
MC74AC374DWR2
MC74AC374DWR2G
SOIC−20
SOIC−20
(Pb−Free)
MC74ACT374DW
MC74ACT374DWG
SOIC−20
SOIC−20
(Pb−Free)
MC74ACT374DWR2
MC74ACT374DWR2G
SOIC−20
1000 / Tape & Reel
SOIC−20
(Pb−Free)
MC74AC374DTR2
MC74AC374DTR2G
MC74ACT374DTR2
MC74ACT374DTR2G
MC74AC374MEL
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
SOEIAJ−20
2500 / Tape & Reel
2500 / Tape & Reel
2000 / Tape & Reel
2000 / Tape & Reel
MC74AC374MELG
SOEIAJ−20
(Pb−Free)
MC74ACT374MEL
MC74ACT374MELG
SOEIAJ−20
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*These packages are inherently Pb−Free.
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7
MC74AC374, MC74ACT374
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
MILLIMETERS
L
C
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
1.070
0.260
0.180
0.022
0.050 BSC
1.27 BSC
−T−
SEATING
PLANE
K
0.050
0.070
1.27
1.77
G
J
0.100 BSC
2.54 BSC
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
J 20 PL
_
_
_
D 20 PL
M
M
B
0.25 (0.010)
T
M
M
A
0.25 (0.010)
T
SOIC−20W
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
MILLIMETERS
1
10
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
0.25
T A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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8
MC74AC374, MC74ACT374
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
20X K REF
K
M
S
S
V
0.10 (0.004)
T
U
S
U
K1
0.15 (0.006) T
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T
U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
MC74AC374, MC74ACT374
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
20
11
E
Q
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
1
H
E
E
_
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.25
12.80
5.45
A
−−−
0.05
A
1
A
b
1
0.002
0.008
0.020
0.010
0.504
0.215
b
c
0.35
0.15
0.014
0.006
0.486
0.201
M
0.10 (0.004)
0.13 (0.005)
D
E
e
12.35
5.10
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
10
0.035
0
0.028
_
_
_
_
0.70
−−−
0.90
0.81
1
Z
−−− 0.032
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