MC74HC160ADTR2G [ONSEMI]
具有异步重置模式的 BCD 计数器;
| 型号： | MC74HC160ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 具有异步重置模式的 BCD 计数器 CD 光电二极管 逻辑集成电路 触发器 计数器 |
| 文件： | 总13页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC160A
Presettable Counters
High−Performance Silicon−Gate CMOS
The MC74HC160A is identical in pinout to the LS160. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC160A is a programmable BCD counters with asynchronous
Reset input.
http://onsemi.com
MARKING
DIAGRAMS
16
Features
SOIC−16
D SUFFIX
CASE 751B
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
HC160AG
AWLYWW
16
1
1
16
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
• These are Pb−Free Devices
TSSOP−16
DT SUFFIX
CASE 948F
HC
160A
ALYWG
G
16
1
1
A
= Assembly Location
= Wafer Lot
= Year
WL, L
YY, Y
WW, W = Work Week
3
4
5
6
14
13
12
11
Q0
Q1
Q2
Q3
P0
P1
P2
P3
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
PRESENT
DATA
INPUTS
BCD
OUTPUTS
PIN ASSIGNMENT
RESET
CLOCK
1
2
16
15
V
CC
RIPPLE
CARRY OUT
RIPPLE
CARRY
OUT
2
15
CLOCK
3
4
14 Q0
P0
P1
P2
P3
13 Q1
5
6
7
8
12 Q2
RESET
LOAD
11 Q3
10 ENABLE T
ENABLE P
GND
9
LOAD
ENABLE P
ENABLE T
COUNT
PIN 16 = V
CC
PIN 8 = GND
ENABLES
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Figure 1. Logic Diagram
Device
Count Mode
Reset Mode
Asynchronous
HC160
BCD
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
May, 2013 − Rev. 2
MC74HC160A/D
MC74HC160A
FUNCTION TABLE
Clock
Inputs
Outputs
Q
Reset*
Load
Enable P
Enable T
L
X
L
X
X
H
L
X
X
H
X
L
Reset
H
H
H
H
Load Preset Data
Count
H
H
H
No Count
No Count
X
*HC160 is an Asynchronous Reset Device.
H = High Level
L = Low Level
X = Don’t Care
MAXIMUM RATINGS
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
CC
−0.5 to +7.0
V
in
−0.5 to V + 0.5
V
CC
V
out
−0.5 to V + 0.5
V
CC
I
in
20
25
50
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating
− SOIC Package: − 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
−55
+125
°C
ns
t , t
Input Rise and Fall Time
(Figure 3)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
http://onsemi.com
2
MC74HC160A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
− 55 to
V
V
CC
25°C
v 85°C
v 125°C
Symbol
Parameter
Test Conditions
= 0.1 V or V − 0.1 V
|I | v 20 mA
Unit
V
IH
Minimum High−Level Input
V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
Voltage
out
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V − 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IH
|I | v 20 mA
out
V
= V or V
|I | v 2.4 m
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
V
OL
Maximum Low−Level Output
V
in
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IH
IL
Voltage
|I | v 20 mA
out
V
= V or V
|I | v 2.4 m
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
0.1
4
1.0
40
1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
160
CC
in
CC
I
= 0 mA
out
http://onsemi.com
3
MC74HC160A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
− 55 to
V
V
CC
25°C
v 85°C
v 125°C
Symbol
Parameter
Unit
f
Maximum Clock Frequency (50% Duty Cycle)*
(Figures 3 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
max
PLH
PHL
PHL
PLH
PHL
PLH
PHL
PHL
t
t
t
t
t
t
t
t
Maximum Propagation Delay, Clock to Q
(Figures 3 and 8)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
Maximum Propagation Delay, Reset to Q (HC160A Only)
(Figures 4 and 8)
2.0
4.5
6.0
210
42
36
265
53
45
315
63
54
ns
ns
Maximum Propagation Delay, Enable T to Ripple Carry Out
(Figures 5 and 8)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
Maximum Propagation Delay, Clock to Ripple Carry Out
(Figures 3 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC160A Only)
(Figures 4 and 8)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
ns
pF
t
,
Maximum Output Transition Time, Any Output
(Figures 3 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
TLH
t
THL
C
Maximum Input Capacitance
−
10
10
10
in
*Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine f . However,
max
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the f
See Applications Information in this data sheet.
in the table above is applicable.
max
Typical @ 25°C, V = 5.0 V
CC
60
C
Power Dissipation Capacitance (Per Package)*
pF
PD
2
*Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
http://onsemi.com
4
MC74HC160A
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
− 55 to
V
V
CC
25°C
v 85°C
190
38
v 125°C
Symbol
Parameter
Unit
t
t
t
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 6)
2.0
4.5
6.0
150
30
225
45
38
ns
su
su
su
26
33
Minimum Setup Time, Load to Clock
(Figure 6)
2.0
4.5
6.0
135
27
23
170
34
29
205
41
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Minimum Setup Time, Enable T or Enable P to Clock
(Figure 7)
2.0
4.5
6.0
200
40
34
250
50
43
300
60
51
t
Minimum Hold Time, Clock to Preset Data Inputs
(Figure 6)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
h
h
h
t
Minimum Hold Time, Clock to Load
(Figure 6)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
t
Minimum Hold Time, Clock to Enable T or Enable P
(Figure 7)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
t
t
Minimum Recovery Time, Reset Inactive to Clock
(Figure 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
rec
Minimum Recovery Time, Load Inactive to Clock
(Figure 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
rec
t
t
Minimum Pulse Width, Clock
(Figure 3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
w
Minimum Pulse Width, Reset
(Figure 4)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
w
t , t
r
Maximum Input Rise and Fall Times
(Figure 3)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
f
http://onsemi.com
5
MC74HC160A
FUNCTION DESCRIPTION
Loading
The HC160A is a programmable 4−bit synchronous
counters that feature parallel Load, synchronous or
asynchronous Reset, a Carry Output for cascading, and
count−enable controls. The HC160A is a BCD counter with
asynchronous Reset.
With the rising edge of the Clock, a low level on Load (pin
9) loads the data from the Preset Data Input pins (P0, P1, P2,
P3) into the internal flip−flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load
is low.
INPUTS
Although the HC160A is a BCD counters, they may be
programmed to any state. If they are loaded with a state
disallowed in BCD code, they will return to their normal
count sequence within two clock pulses (see the Output State
Diagram).
Clock (Pin 2)
The internal flip−flops toggle and the output count
advances with the rising edge of the Clock input. In addition,
control functions, such as loading occur with the rising edge
of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the
internal flip−flops and appear at the counter outputs. P0 (pin
3) is the least−significant bit and P3 (pin 6) is the
most−significant bit.
Count Enable/Disable
These devices have two count−enable control pins:
Enable P (pin 7) and Enable T (pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:
Count Enable = Enable P ꢀ Enable T ꢀ Load
The count is either enabled or disabled by the control
inputs according to Table 1. In general, Enable P is a
count−enable control; Enable T is both a count−enable and
a Ripple−Carry Output control.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
These are the counter outputs (BCD or binary). Q0 (pin
14) is the least−significant bit and Q3 (pin 11) is the
most−significant bit.
Table 1. COUNT ENABLE/DISABLE
Control Inputs
Result at Outputs
Ripple Carry Out (Pin 15)
When the counter is in its maximum state (1001 for the
BCD counters or 1111 for the binary counters), this output
goes high, providing an external look−ahead carry pulse that
may be used to enable successive cascaded counters. Ripple
Carry Out remains high only during the maximum count
state. The logic equation for this output is:
Load Enable P Enable T Q0 − Q3 Ripple Carry Out
H
L
H
H
L
H
H
H
Count
High when
Q0−Q3 are max-
imum*
No Count
X
No Count High when
Q0−Q3 are max-
imum*
Ripple Carry Out =
Enable T ꢀ Q0 ꢀ Q1 ꢀ Q2 ꢀ Q3
X
X
L
No Count
L
for BCD counters
*Q0 through Q3 are maximum for the HC160A when Q3 Q2 Q1 Q0
= 1001.
CONTROL FUNCTIONS
Resetting
A low level on the Reset pin (pin 1) resets the internal
flip−flops and sets the outputs (Q0 through Q3) to a low
level. The HC160A resets asynchronously.
0
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
Figure 2. Output State Diagrams HC160A BCD Counters
http://onsemi.com
6
MC74HC160A
SWITCHING WAVEFORMS
t
w
t
r
t
f
V
V
CC
CC
90%
50%
10%
CLOCK
50%
RESET
GND
GND
t
PHL
t
w
1/fmax
50%
ANY
t
t
PHL
PLH
OUTPUT
90%
50%
10%
t
ANY
rec
OUTPUT
V
CC
50%
CLOCK
t
t
THL
TLH
GND
Figure 3.
Figure 4.
t
r
t
f
VALID
V
CC
90%
50%
10%
ENABLE T
INPUTS
P0, P1,
P2, P3
V
CC
GND
50%
t
t
GND
PLH
PHL
90%
50%
10%
RIPPLE
CARRY
OUT
t
t
t
su
h
V
CC
t
t
THL
TLH
50%
LOAD
GND
Figure 5.
t
t
su
rec
h
V
CC
CLOCK
50%
GND
Figure 6.
TEST CIRCUIT
VALID
TEST POINT
ENABLE T
OR
V
CC
50%
OUTPUT
ENABLE P
GND
DEVICE
UNDER
TEST
t
su
t
h
C *
L
V
CC
50%
CLOCK
GND
Figure 7.
*Includes all probe and jig capacitance
Figure 8.
http://onsemi.com
7
MC74HC160A
http://onsemi.com
8
MC74HC160A
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine, zero, one, two, and three.
4. Inhibit.
RESET (HC160A)
(ASYNCHRONOUS)
LOAD
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK
(HC160A)
CLOCK
(HC162A)
ENABLE P
ENABLE T
Q0
COUNT
ENABLES
Q1
OUTPUTS
Q2
Q3
RIPPLE
CARRY
OUT
7
8
9
0
1
2
3
COUNT
INHIBIT
RESET
LOAD
Figure 9. MC74HC160A Timing Diagram
http://onsemi.com
9
MC74HC160A
TYPICAL APPLICATIONS CASCADING
LOAD
INPUTS
INPUTS
INPUTS
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
H = COUNT
L = DISABLE
ENABLE P
RIPPLE
ENABLE P
RIPPLE
ENABLE P
RIPPLE
H = COUNT
L = DISABLE
TO
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
MORE
SIGNIFICANT
STAGES
CLOCK
CLOCK
CLOCK
R
Q0 Q1 Q2 Q3
R
Q0 Q1 Q2 Q3
R
Q0 Q1 Q2 Q3
RESET
CLOCK
OUTPUTS
OUTPUTS
OUTPUTS
NOTE: When used in these cascaded configurations the clock f
guaranteed limits may not apply. Actual performance will depend
max
on number of stages. This limitation is due to set up times between Enable (Port) and Clock.
Figure 10. N−Bit Synchronous Counters
INPUTS
INPUTS
INPUTS
LOAD
ENABLE P
ENABLE T
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
ENABLE P
RIPPLE
ENABLE P
RIPPLE
ENABLE P
RIPPLE
TO
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
MORE
SIGNIFICANT
STAGES
CLOCK
RESET
CLOCK
CLOCK
CLOCK
R
Q0 Q1 Q2 Q3
R
Q0 Q1 Q2 Q3
R
Q0 Q1 Q2 Q3
OUTPUTS
OUTPUTS
OUTPUTS
Figure 11. Nibble Ripple Counter
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC160ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC160ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74HC160ADTG
TSSOP−16*
TSSOP−16*
96 Units / Rail
MC74HC160ADTR2G
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
B
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
0.65
PITCH
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70247A
TSSOP−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
MC74HC161ADR2
Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, SOIC-16
ROCHESTER
©2020 ICPDF网 联系我们和版权申明