MC74HC259ADTG [ONSEMI]
8 位可寻址锁存 1/8 解码器;
| 型号： | MC74HC259ADTG |
| 厂家： | 
ONSEMI |
| 描述： | 8 位可寻址锁存 1/8 解码器 光电二极管 逻辑集成电路 触发器 解码器 |
| 文件： | 总9页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC259A
8-Bit Addressable Latch
1-of-8 Decoder
High−Performance Silicon−Gate CMOS
The MC74HC259A is identical in pinout to the LS259. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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MARKING
The HC259A has four modes of operation as shown in the mode
selection table. In the addressable latch mode, the data on Data In is
written into the addressed latch. The addressed latch follows the data
input with all non−addressed latches remaining in their previous
states. In the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs. In the one−of−eight
decoding or demultiplexing mode, the addressed output follows the
state of Data In with all other outputs in the LOW state. In the Reset
mode all outputs are LOW and unaffected by the address and data
inputs. When operating the HC259A as an addressable latch, changing
more than one bit of the address could impose a transient wrong
address. Therefore, this should only be done while in the memory
mode.
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
HC259AG
AWLYWW
16
1
1
16
TSSOP−16
DT SUFFIX
CASE 948F
HC
259A
ALYWG
G
16
1
1
A
= Assembly Location
= Wafer Lot
WL, L
YY, Y
= Year
Features
WW, W = Work Week
G or G
= Pb−Free Package
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
(Note: Microdot may be in either location)
PIN ASSIGNMENT
A0
A1
A2
Q0
Q1
Q2
1
2
3
4
5
6
7
8
16
V
CC
• High Noise Immunity Characteristic of CMOS Devices
15 RESET
14 ENABLE
13 DATA IN
12 Q7
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
11 Q6
10 Q5
Q3
GND
9
Q4
MODE SELECTION TABLE
Enable Reset
Mode
L
H
L
H
H
L
Addressable Latch
Memory
8−Line Demultiplexer
Reset
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
June, 2012 − Rev. 3
MC74HC259A/D
MC74HC259A
1
2
3
4
5
6
7
9
LATCH SELECTION TABLE
A0
A1
A2
Q0
Q1
Q2
Q3
Q4
ADDRESS
INPUTS
Address Inputs
A
A
A
0
Latch Addressed
2
1
NONINVERTING
OUTPUTS
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
L
13
10
11
DATA IN
Q5
Q6
L
12
H
H
H
H
Q7
15
14
RESET
PIN 16 = V
CC
PIN 8 = GND
ENABLE
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to +7.0
V
V
CC
V
−0.5 to V + 0.5
in
CC
V
out
−0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
SOIC Package
TSSOP Package
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
−65 to + 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
−55
+125
°C
ns
t , t
Input Rise and Fall Time
(Figure 2)
V
CC
V
CC
V
CC
V
CC
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
r
f
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2
MC74HC259A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
− 55 to
V
V
CC
25°C
v 85°C
v 125°C
Symbol
Parameter
Test Conditions
= 0.1 V or V − 0.1 V
|I | v 20 mA
Unit
V
IH
Minimum High−Level Input
V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
Voltage
out
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V − 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
V
V
IL
out
CC
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IH
|I | v 20 mA
out
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
V
OL
Maximum Low−Level Output
V
in
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IH
IL
Voltage
|I | v 20 mA
out
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
0.1
4
1.0
40
1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
160
CC
in
CC
I
= 0 mA
out
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3
MC74HC259A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
− 55 to
V
V
CC
25°C
v 85°C
v 125°C
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, Data to Output
(Figures 2 and 7)
2.0
3.0
4.5
6.0
125
45
32
160
60
32
175
70
42
ns
PLH
t
PHL
25
28
33
,
Maximum Propagation Delay, Address Select to Output
(Figures 3 and 7)
2.0
3.0
4.5
6.0
150
60
32
175
70
40
200
80
45
ns
ns
ns
ns
pF
pF
PLH
t
PHL
28
30
35
,
Maximum Propagation Delay, Enable to Output
(Figures 4 and 7)
2.0
3.0
4.5
6.0
150
60
32
175
70
40
200
80
45
PLH
t
PHL
28
30
35
t
Maximum Propagation Delay, Reset to Output
(Figures 5 and 7)
2.0
3.0
4.5
6.0
110
36
22
125
45
26
160
60
32
PHL
19
23
28
t
t
,
Maximum Output Transition Time, Any Output
(Figures 2 and 7)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
TLH
THL
19
C
Maximum Input Capacitance
−
10
10
10
in
Typical @ 25°C, V = 5.0 V
CC
30
C
Power Dissipation Capacitance (Per Package)
PD
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
− 55 to
25°C
V
V
CC
v 85°C
95
40
19
16
v 125°C
110
55
Symbol
Parameter
Unit
t
su
Minimum Setup Time, Address or Data to Enable
(Figure 6)
2.0
3.0
4.5
6.0
75
30
15
13
ns
22
19
t
Minimum Hold Time, Enable to Address or Data
(Figure 6)
2.0
3.0
4.5
6.0
1
1
1
1
1
1
1
1
1
1
1
1
ns
ns
ns
h
t
w
Minimum Pulse Width, Reset or Enable
(Figure 4 or 5)
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
t , t
r
Maximum Input Rise and Fall Times
(Figure 2)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
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4
MC74HC259A
SWITCHING WAVEFORMS
V
CC
DATA IN
GND
V
CC
50%
50%
t
r
t
f
GND
ADDRESS
V
CC
DATA IN
90%
50%
10%
SELECT
V
CC
GND
GND
t
t
PHL
PLH
90%
50%
10%
t
t
PLH
PHL
OUTPUT Q
50%
OUTPUT Q
t
t
THL
TLH
Figure 2.
Figure 3.
V
CC
V
CC
DATA IN
ENABLE
DATA IN
RESET
GND
GND
t
t
w
w
t
w
V
CC
V
CC
50%
50%
50%
50%
GND
GND
t
t
PLH
PHL
t
PHL
50%
OUTPUT Q
OUTPUT Q
Figure 4.
Figure 5.
TEST POINT
OUTPUT
DATA IN
OR
V
CC
DEVICE
UNDER
TEST
50%
ADDRESS
SELECT
GND
C *
L
t
t
h(H)
h(L)
t
su
t
su
V
CC
ENABLE
50%
GND
*Includes all probe and jig capacitance
Figure 6.
Figure 7. Test Circuit
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5
MC74HC259A
13
4
5
6
DATA INPUT
D
D
D
Q0
Q1
Q2
7
9
D
D
D
D
D
Q3
Q4
Q5
Q6
Q7
A0
ADDRESS
INPUTS
3 TO 8
A1
A2
DECODER
10
11
12
14
ENABLE
15
RESET
Figure 8. Expanded Logic Diagram
ORDERING INFORMATION
†
Device
Package
Shipping
MC74HC259ADG
SOIC−16
(Pb−Free)
48 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
96 Units / Rail
MC74HC259ADR2G
SOIC−16
(Pb−Free)
MC74HC259ADTR2G
MC74HC259ADTG
NLVHC259ADR2G*
TSSOP−16
(Pb−Free)
TSSOP−16
(Pb−Free)
SOIC−16
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
B
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
0.65
PITCH
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70247A
TSSOP−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
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