MC74HC373ADW [ONSEMI]
Octal 3-State Non-Inverting Transparent Latch; 八路三态非反相透明锁存器
| 型号： | MC74HC373ADW |
| 厂家： | 
ONSEMI |
| 描述： | Octal 3-State Non-Inverting Transparent Latch |
| 文件： | 总8页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High–Performance Silicon–Gate CMOS
The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high–impedance state. Thus, data may be latched even when the
outputs are not enabled.
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
MARKING
DIAGRAMS
20
PDIP–20
N SUFFIX
CASE 738
MC74HC373AN
AWLYYWW
20
1
1
20
SOIC WIDE–20
DW SUFFIX
CASE 751D
HC373A
AWLYYWW
20
1
The HC373A is the non–inverting version of the HC533A.
1
20
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
HC
373A
ALYW
TSSOP–20
DT SUFFIX
CASE 948G
20
1
1
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates
ORDERING INFORMATION
Device
Package
PDIP–20
Shipping
1440 / Box
38 / Rail
MC74HC373AN
MC74HC373ADW
MC74HC373ADWR2
MC74HC373ADT
MC74HC373ADTR2
SOIC–WIDE
SOIC–WIDE 1000 / Reel
TSSOP–20 75 / Rail
TSSOP–20 2500 / Reel
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 8
MC74HC373A/D
MC74HC373A
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
1
2
3
4
5
6
7
8
9
20
V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
LOGIC DIAGRAM
D0
D1
Q1
Q2
D2
D3
Q3
3
2
5
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
4
6
7
8
9
DATA
INPUTS
NONINVERTING
OUTPUTS
13
12
15
16
19
14
17
18
LATCH
ENABLE
D5
D6
D7
GND 10
11
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable
11
1
PIN 20 = V
CC
PIN 10 = GND
D
Q
LATCH ENABLE
L
L
L
H
H
L
H
L
X
X
H
OUTPUT ENABLE
L
No Change
Z
H
X
X = Don’t Care
Z = High Impedance
Design Criteria
Internal Gate Count*
Value
46.5
1.5
Units
ea
Internal Gate Propagation Delay
Internal Gate Power Dissipation
ns
5.0
µW
pJ
Speed Power Product
0.0075
*Equivalent to a two–input NAND gate.
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2
MC74HC373A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
= V – 0.1 V
85 C
125 C
Unit
V
IH
Minimum High–Level Input
Voltage
V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
20 µA
|I
|
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
IH
20 µA
|I
|
out
V
in
= V
|I
|I
|I
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
IH
out
out
out
V
OL
Maximum Low–Level Output
Voltage
V
= V
|
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IL
20 µA
|I
out
V
in
= V
|I
|I
|I
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
IL
out
out
out
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3
MC74HC373A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
= V or GND
CC
85 C
125 C
Unit
I
in
Maximum Input Leakage
Current
V
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
in
I
Maximum Three–State
Leakage Current
Output in High–Impedance State
± 0.5
± 5.0
± 10
µA
µA
OZ
V
V
= V or V
in
IL
= V
IH
or GND
out
CC
or GND
I
Maximum Quiescent Supply
Current (per Package)
V
= V
CC
= 0 µA
6.0
4.0
40
160
CC
in
I
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
3.0
4.5
6.0
125
80
25
155
110
31
190
130
38
ns
PLH
PHL
21
26
32
t
t
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
3.0
4.5
6.0
140
90
28
175
120
35
210
140
42
ns
ns
ns
ns
PLH
PHL
24
30
36
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PLZ
t
PHZ
26
33
38
t
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PZL
PZH
26
33
38
t
t
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
TLH
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
36
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
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4
MC74HC373A
TIMING REQUIREMENTS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
85 C
– 55 to 25 C
125 C
Max
V
Volts
CC
Symbol
Parameter
Fig.
Unit
Min
Max
Min
Max
Min
t
Minimum Setup Time, Input D to Latch Enable
Minimum Hold Time, Latch Enable to Input D
Minimum Pulse Width, Latch Enable
4
2.0
3.0
4.5
6.0
25
20
5.0
5.0
30
25
6.0
6.0
40
30
8.0
7.0
ns
su
t
4
2
1
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5 0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
h
t
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
w
t , t
r
Maximum Input Rise and Fall Times
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
SWITCHING WAVEFORMS
t
r
t
f
t
w
V
V
CC
CC
90%
50%
10%
LATCH ENABLE
50%
INPUT D
Q
GND
GND
t
t
PHL
PLH
t
t
PHL
PLH
90%
50%
10%
Q
50%
t
t
THL
TLH
Figure 1.
Figure 2.
V
CC
OUTPUT
ENABLE
50%
GND
VALID
t
t
PLZ
PZL
V
CC
HIGH
IMPEDANCE
INPUT D
50%
50%
GND
Q
Q
t
t
h
10%
90%
su
V
OL
t
t
V
CC
PZH PHZ
LATCH ENABLE
V
OH
50%
GND
1.3 V
HIGH
IMPEDANCE
Figure 3.
Figure 4.
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5
MC74HC373A
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kΩ
CONNECT TO V WHEN
CC
OUTPUT
TESTING t
AND t .
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
C *
L
PHZ PZH
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
EXPANDED LOGIC DIAGRAM
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
11
1
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
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6
MC74HC373A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66 27.17
MILLIMETERS
MIN MAX
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
1.27 BSC
1.27
6.60
4.57
0.55
–T–
SEATING
PLANE
K
M
0.070
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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7
MC74HC373A
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
CASE 948E–02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
M
S
S
0.10 (0.004)
T U
V
S
Y14.5M, 1982.
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
C
6.40
4.30
–––
6.60 0.252
4.50 0.169
1.20
N
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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MC74HC373A/D
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