MC74HC390ADG [ONSEMI]
Dual 4−Stage Binary Ripple Counter with /2and /5 Sections High−Performance Silicon−Gate CMOS; 双4级二进制纹波计数器带/ 2AND / 5节高性能硅栅CMOS
| 型号： | MC74HC390ADG |
| 厂家： | 
ONSEMI |
| 描述： | Dual 4−Stage Binary Ripple Counter with /2and /5 Sections High−Performance Silicon−Gate CMOS |
| 文件： | 总10页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC390A
Dual 4−Stage Binary Ripple
Counter with ÷ 2 and ÷ 5
Sections
High−Performance Silicon−Gate CMOS
http://onsemi.com
MARKING
The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
DIAGRAMS
This device consists of two independent 4−bit counters, each
composed of a divide−by−two and a divide−by−five section. The
divide−by−two and divide−by−five counters have separate clock
inputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.
16
PDIP−16
N SUFFIX
CASE 648
MC74HC390AN
AWLYYWWG
16
1
1
Flip−flops internal to the counters are triggered by high−to−low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4−bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
16
SOIC−16
D SUFFIX
CASE 751B
HC390AG
AWLYWW
16
1
1
16
Features
TSSOP−16
DT SUFFIX
CASE 948F
HC
390A
ALYWG
G
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 mA
16
1
1
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
• Pb−Free Packages are Available*
16
1
SOEIAJ−16
F SUFFIX
CASE 966
16
74HC390A
ALYWG
1
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
W, WW = Work Week
G
= Pb−Free Package
= Pb−Free Package
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
June, 2005 − Rev. 3
MC74HC390A/D
MC74HC390A
÷ 2
COUNTER
3, 13
5, 11
1, 15
CLOCK A
1
2
3
4
5
6
7
8
16
15
V
CC
Q
Q
a
A
B
CLOCK A
CLOCK A
RESET a
b
b
Q
14 RESET b
13
12 CLOCK B
Aa
CLOCK B
Q
Ab
a
Ba
Ca
Da
÷ 5
COUNTER
6, 10
7, 9
Q
Q
4, 12
2, 14
Q
CLOCK B
RESET
C
Q
11
10
9
Q
Q
Q
D
Bb
Cb
Db
Q
PIN 16 = V
CC
PIN 8 = GND
GND
Figure 1. Pin Assignment
Figure 2. Logic Diagram
FUNCTION TABLE
Clock
A
B
Reset
Action
X
X
H
Reset
÷ 2 and ÷ 5
X
L
L
Increment
÷ 2
Increment
X
÷ 5
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC390AN
PDIP−16
500 Units / Rail
500 Units / Rail
MC74HC390ANG
PDIP−16
(Pb−Free)
MC74HC390AD
SOIC−16
48 Units / Rail
48 Units / Rail
MC74HC390ADG
SOIC−16
(Pb−Free)
MC74HC390ADR2
MC74HC390ADR2G
SOIC−16
2500 Units / Reel
2500 Units / Reel
SOIC−16
(Pb−Free)
MC74HC390ADTR2
MC74HC390ADTR2G
MC74HC390AF
TSSOP−16*
TSSOP−16*
SOEIAJ−16
2500 Units / Reel
2500 Units / Reel
50 Units / Rail
MC74HC390AFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74HC390AFEL
MC74HC390AFELG
SOEIAJ−16
2000 Units / Reel
2000 Units / Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
2
MC74HC390A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
out
CC
V
– 0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
I
I
DC Output Current, per Pin
out
cuit. For proper operation, V and
in
DC Supply Current, V and GND Pins
V
out
should be constrained to the
CC
CC
range GND v (V or V ) v V
.
CC
in
out
P
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
D
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V ).
CC
T
stg
Storage Temperature
– 65 to + 150
_C
_C
Unused outputs must be left open.
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
CC
V , V
in out
V
V
CC
T
A
– 55
+ 125
_C
ns
t , t
r
Input Rise and Fall Time
(Figure 1)
V
V
V
V
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
f
CC
CC
CC
CC
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
1.5
2.1
3.15
4.2
V
v 85_C v 125_C
Symbol
Parameter
Test Conditions
= 0.1 V or V – 0.1 V
|I | v 20 mA
Unit
V
Minimum High−Level Input
Voltage
V
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
V
IH
out
CC
out
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V – 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I | v 20 mA
out
V
Minimum High−Level Output
Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
OH
IH
|I | v 20 mA
out
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
V
Maximum Low−Level Output
Voltage
V
in
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
IH
IL
|I | v 20 mA
out
V
in
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
http://onsemi.com
3
MC74HC390A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
0.1
v 85_C v 125_C
V
Symbol
Parameter
Test Conditions
= V or GND
Unit
I
Maximum Input Leakage
Current
V
V
6.0
1.0
1.0
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
6.0
4
40
160
mA
CC
in
CC
I
= 0 mA
out
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
f
f
Guaranteed Limit
– 55 to
V
CC
25_C
10
15
30
50
v 85_C v 125_C
V
Symbol
Parameter
Unit
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
9
8
MHz
max
14
28
45
12
25
40
t
t
t
t
t
,
Maximum Propagation Delay, Clock A to QA
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
24
20
80
45
30
26
90
50
36
31
ns
ns
ns
ns
ns
ns
ns
pF
PLH
t
PHL
,
Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
200
160
58
250
185
65
300
210
70
PLH
t
PHL
49
62
68
,
Maximum Propagation Delay, Clock B to QB
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
PLH
t
PHL
,
Maximum Propagation Delay, Clock B to QC
(Figures 1 and 3)
2.0
3.0
4.5
6.0
90
56
37
31
105
70
46
180
100
56
PLH
t
PHL
39
48
,
Maximum Propagation Delay, Clock B to QD
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
PLH
t
PHL
t
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
3.0
4.5
6.0
80
48
30
26
95
65
38
33
110
75
44
PHL
39
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
TLH
THL
19
C
in
Maximum Input Capacitance
−
10
10
10
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
35
f + I V . For load considerations, see Chapter 2 of the
CC CC
C
Power Dissipation Capacitance (Per Counter)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
D
PD CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
4
MC74HC390A
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
25_C
25
15
10
9
V
v 85_C v 125_C
Symbol
Parameter
Unit
t
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 2)
2.0
3.0
4.5
6.0
30
20
13
11
40
30
15
13
ns
rec
t
t
Minimum Pulse Width, Clock A, Clock B
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
ns
ns
ns
w
w
19
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
20
18
95
32
24
22
110
36
30
28
t , t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
PIN DESCRIPTIONS
INPUTS
OUTPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
QA (Pins 3, 13)
Clock A is the clock input to the ÷ 2 counter; Clock B is
the clock input to the ÷ 5 counter. The internal flip−flops are
toggled by high−to−low transitions of the clock input.
Output of the ÷ 2 counter.
QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)
Outputs of the ÷ 5 counter. Q is the most significant bit.
D
CONTROL INPUTS
Reset (Pins 2, 14)
Q is the least significant bit when the counter is connected
A
for BCD output as in Figure 4. Q is the least significant bit
B
Asynchronous reset. A high at the Reset input prevents
when the counter is operating in the bi−quinary mode as in
Figure 5.
counting, resets the internal flip−flops, and forces Q
A
through Q low.
D
SWITCHING WAVEFORMS
t
f
t
r
t
w
V
90%
50%
10%
CC
V
CC
CLOCK
10%
50%
RESET
GND
GND
t
w
t
PHL
1/f
max
50%
Q
t
t
PHL
PLH
90%
50%
10%
t
rec
Q
V
CC
50%
CLOCK
t
t
THL
TLH
GND
Figure 3.
Figure 4.
http://onsemi.com
5
MC74HC390A
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 5.
EXPANDED LOGIC DIAGRAM
1, 15
Q
C
CLOCK A
CLOCK B
3, 13
D
D
Q
Q
Q
A
R
R
4, 12
Q
Q
C
5, 11
B
Q
Q
C
6, 10
Q
D
C
R
C
7, 9
Q
D
D
Q
R
2, 14
RESET
TIMING DIAGRAM
(QA Connected to Clock B)
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
CLOCK A
RESET
Q
Q
A
B
Q
C
Q
D
http://onsemi.com
6
MC74HC390A
APPLICATIONS INFORMATION
Each half of the MC54/74HC390A has independent ÷ 2
To obtain a bi−quinary count sequence, the input signals
and ÷ 5 sections (except for the Reset function). The ÷ 2 and
÷ 5 counters can be connected to give BCD or bi−quinary
connected to the Clock B input, and output Q is connected
D
to the Clock A input (Figure 5). Q provides a 50% duty
A
(2−5) count sequences. If Output Q is connected to the
cycle output. The bi−quinary count sequence function table
is given in Table 2.
A
Clock B input (Figure 4), a decade divider with BCD output
is obtained. The function table for the BCD count sequence
is given in Table 1.
Table 1. BCD Count Sequence*
Output
Table 2. Bi−Quinary Count Sequence**
Output
Q
Q
Q
Q
Q
Q
Q
Q
B
Count
Count
D
C
B
A
A
D
C
0
1
2
3
4
5
6
7
8
9
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
8
9
10
11
12
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
H
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
H
H
L
L
L
L
H
L
L
L
L
H
L
H
H
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
L
L
*Q connected to Clock B input.
A
**Q connected to Clock A input.
D
CONNECTION DIAGRAMS
1, 15
3, 13
1, 15
3, 13
Q
Q
Q
÷ 2
COUNTER
A
A
÷ 2
COUNTER
CLOCK A
CLOCK A
5, 11
6, 10
7, 9
5, 11
6, 10
7, 9
Q
B
4, 12
2, 14
B
4, 12
÷ 5
COUNTER
CLOCK B
CLOCK B
RESET
÷ 5
COUNTER
Q
Q
C
C
Q
Q
D
D
2, 14
RESET
Figure 6. BCD Count
Figure 7. Bi-Quinary Count
http://onsemi.com
7
MC74HC390A
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
M
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T B
A
http://onsemi.com
8
MC74HC390A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16X KREF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
1.20
−−− 0.047
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
D
G
http://onsemi.com
9
MC74HC390A
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
CASE 966−01
ISSUE O
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
16
9
E
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
Q
1
H
E
E
M
_
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.27
10.50
5.45
A
−−−
0.05
0.35
0.18
9.90
5.10
A
A
1
0.002
0.008
0.020
0.011
0.413
0.215
1
b
0.13 (0.005)
b
c
0.014
0.007
0.390
0.201
0.10 (0.004)
M
D
E
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
0
10
10
0.035
M
Q
0
0.028
_
_
_
_
0.70
−−−
0.90
0.78
1
Z
−−− 0.031
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC74HC390A/D
相关型号：
MC74HC390ADR2G
Dual 4−Stage Binary Ripple Counter with /2and /5 Sections High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC390ADTR2G
Dual 4−Stage Binary Ripple Counter with /2and /5 Sections High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC390AF
Dual 4−Stage Binary Ripple Counter with /2and /5 Sections High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC390AFEL
Dual 4−Stage Binary Ripple Counter with /2and /5 Sections High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC390AFELG
Dual 4−Stage Binary Ripple Counter with /2and /5 Sections High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC390AFG
Dual 4−Stage Binary Ripple Counter with /2and /5 Sections High−Performance Silicon−Gate CMOS
ONSEMI
©2020 ICPDF网 联系我们和版权申明