MC74HC4052AN [ONSEMI]
Analog Multiplexers/Demultiplexers; 模拟多路复用器/多路解复用器
| 型号： | MC74HC4052AN |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexers/Demultiplexers |
| 文件： | 总16页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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High–Performance Silicon–Gate CMOS
MARKING
DIAGRAMS
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize
silicon–gate CMOS technology to achieve fast propagation delays,
low ON resistances, and low OFF leakage currents. These analog
multiplexers/demultiplexers control analog voltages that may vary
16
PDIP–16
N SUFFIX
CASE 648
HC405xAN
AWLYYWW
16
across the complete power supply range (from V
to V ).
CC
EE
1
The HC4051A, HC4052A and HC4053A are identical in pinout to
the metal–gate MC14051AB, MC14052AB and MC14053AB. The
Channel–Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.
1
16
SO–16
D SUFFIX
CASE 751B
HC405xAD
AWLYYWW
16
16
1
1
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
16
SO–16 WIDE
DW SUFFIX
CASE 751G
HC405xA
AWLYWW
These devices have been designed so that the ON resistance (R ) is
on
more linear over input voltage than R of metal–gate CMOS analog
on
1
1
1
switches.
16
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
HC40
5xA
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
16
1
16
1
• Analog Power Supply Range (V
– V ) = 2.0 to 12.0 V
CC
EE
SOEIAJ–16
F SUFFIX
CASE 966
74HC405xA
ALYW
• Digital (Control) Power Supply Range (V
CC
– GND) = 2.0 to 6.0 V
16
• Improved Linearity and Lower ON Resistance Than Metal–Gate
1
Counterparts
• Low Noise
A
= Assembly Location
WL = Wafer Lot
YY = Year
• In Compliance With the Requirements of JEDEC Standard No. 7A
• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates
HC4052A — 168 FETs or 42 Equivalent Gates
WW = Work Week
HC4053A — 156 FETs or 39 Equivalent Gates
ORDERING INFORMATION
Seedetailedorderingandshippinginformationinthepackage
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 1
MC74HC4051A/D
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE – MC74HC4051A
LOGIC DIAGRAM
MC74HC4051A
Single–Pole, 8–Position Plus Common Off
Control Inputs
Select
Enable
C
B
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
NONE
13
X0
14
X1
3
COMMON
OUTPUT/
INPUT
15
12
1
L
X
X2
X3
X4
X5
X6
X7
A
ANALOG
INPUTS/
H
H
H
H
X
MULTIPLEXER/
DEMULTIPLEXER
L
OUTPUTS
H
H
X
5
2
4
X = Don’t Care
11
10
9
CHANNEL
SELECT
INPUTS
Pinout: MC74HC4051A (Top View)
B
V
X2
X1
X0
X3
A
B
C
9
C
CC
6
16
15
14
13
12
11
10
ENABLE
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
1
2
3
4
5
6
7
8
X4
X6
X
X7
X5 Enable
V
EE
GND
FUNCTION TABLE – MC74HC4052A
LOGIC DIAGRAM
MC74HC4052A
Double–Pole, 4–Position Plus Common Off
Control Inputs
Select
Enable
B
A
ON Channels
12
X0
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
Y0
Y1
Y2
Y3
X0
X1
X2
X3
14
X1
X2
X3
13
X SWITCH
Y SWITCH
X
Y
15
11
COMMON
OUTPUTS/INPUTS
ANALOG
NONE
INPUTS/OUTPUTS
1
5
Y0
Y1
Y2
Y3
A
X = Don’t Care
3
2
4
Pinout: MC74HC4052A (Top View)
10
9
V
X2
15
X1
14
X
X0
12
X3
11
A
B
9
CHANNEL-SELECT
INPUTS
CC
PIN 16 = V
CC
B
16
13
10
PIN 7 = V
EE
PIN 8 = GND
6
ENABLE
1
2
3
4
5
6
7
8
Y0
Y2
Y
Y3
Y1 Enable
V
EE
GND
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2
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE – MC74HC4053A
Control Inputs
LOGIC DIAGRAM
MC74HC4053A
Triple Single–Pole, Double–Position Plus Common Off
Select
Enable
C
B
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
Z0
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
12
Z0
Z0
Z0
Z1
Z1
Z1
Z1
X1
X0
X1
X0
X1
X0
X1
X0
X1
14
X
13
X SWITCH
L
H
H
H
H
X
2
1
L
Y0
Y1
15
4
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
Y
Z
H
H
X
Y SWITCH
Z SWITCH
5
3
Z0
Z1
X = Don’t Care
11
10
9
A
B
C
PIN 16 = V
CC
CHANNEL-SELECT
INPUTS
PIN 7 = V
EE
Pinout: MC74HC4053A (Top View)
PIN 8 = GND
6
V
Y
X
X1
13
X0
12
A
B
C
9
CC
ENABLE
16
15
14
11
10
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch
1
2
3
4
5
6
7
8
Y1
Y0
Z1
Z
Z0 Enable
V
EE
GND
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
Positive DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to + 14.0
V
CC
(Referenced to V
)
EE
V
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
– 7.0 to + 5.0
V
V
EE
V
V
V
– 0.5 to
IS
EE
+ 0.5
CC
cuit. For proper operation, V and
in
V
should be constrained to the
V
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
– 0.5 to V
+ 0.5
V
out
in
CC
range GND (V or V
)
V
CC
.
in out
I
± 25
mA
mW
Unused inputs must always be
tied to an appropriate logic voltage
P
Power Dissipation in Still Air,
Plastic DIP†
EIAJ/SOIC Package†
TSSOP Package†
750
500
450
D
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature Range
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
EIAJ/SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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3
MC74HC4051A, MC74HC4052A, MC74HC4053A
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Positive DC Supply Voltage
Min
Max
Unit
V
CC
(Referenced to GND)
(Referenced to V
2.0
2.0
6.0
12.0
V
)
EE
V
EE
Negative DC Supply Voltage, Output (Referenced to
GND)
– 6.0 GND
V
V
Analog Input Voltage
V
V
V
V
V
IS
EE
CC
V
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
GND
in
CC
V
IO
*
1.2
– 55 + 125
V
T
C
ns
A
t , t
r f
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
V
CC
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
CC
V
V
CC
CC
*For voltage drops across switch greater than 1.2V (switch on), excessive V
current may be
CC
drawn; i.e., the current out of the switch may contain both V
and switch input components.
CC
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) V
= GND, Except Where Noted
EE
Guaranteed Limit
–55 to 25°C ≤85°C ≤125°C
V
CC
V
Symbol
Parameter
Condition
= Per Spec
Unit
V
IH
Minimum High–Level Input
Voltage, Channel–Select or
Enable Inputs
R
R
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
on
on
V
IL
Maximum Low–Level Input
Voltage, Channel–Select or
Enable Inputs
= Per Spec
2.0
3.0
4.5
6.0
0.5
0.9
0.5
0.9
0.5
0.9
V
1.35
1.8
1.35
1.8
1.35
1.8
I
Maximum Input Leakage Current,
Channel–Select or Enable Inputs
V
V
= V
or GND,
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
in
CC
= – 6.0 V
EE
I
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
CC
V
V
= V
CC
= 0 V
or GND;
V
V
= GND
= – 6.0
6.0
6.0
1
4
10
40
20
80
IS
IO
EE
EE
NOTE: InformationontypicalparametricvaluescanbefoundinChapter2oftheONSemiconductorHigh–SpeedCMOSDataBook(DL129/D).
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4
MC74HC4051A, MC74HC4052A, MC74HC4053A
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
Symbol
Parameter
Condition
V
CC
V
EE
Unit
–55 to 25°C ≤85°C ≤125°C
R
Maximum “ON” Resistance
V
V
= V or V ; V = V
to
or
4.5
4.5
6.0
0.0
– 4.5
– 6.0
190
120
100
240
150
125
280
170
140
Ω
on
in
IL IH IS
CC
; I ≤ 2.0 mA
EE
S
(Figures 1, 2)
V
V
= V or V ; V = V
IL IH IS
4.5
4.5
6.0
0.0
– 4.5
– 6.0
150
100
80
190
125
100
230
140
115
in
EE
CC
(Endpoints); I ≤ 2.0 mA
S
(Figures 1, 2)
∆R
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
= V or V
IL
;
4.5
4.5
6.0
0.0
– 4.5
– 6.0
30
12
10
35
15
12
40
18
14
Ω
on
in
IS
IH
= 1/2 (V
– V );
EE
CC
I
S
≤ 2.0 mA
I
off
Maximum Off–Channel Leakage
Current, Any One Channel
V
V
= V or V
IL
;
µA
in
IH
= V
– V
;
6.0
– 6.0
0.1
0.5
1.0
IO
CC EE
Switch Off (Figure 3)
Maximum Off–ChannelHC4051A
V
V
= V or V
IL
;
6.0
6.0
6.0
– 6.0
– 6.0
– 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
in
IH
– V
Leakage Current,
Common Channel
HC4052A
HC4053A Switch Off (Figure 4)
= V
;
IO
CC
EE
I
on
Maximum On–ChannelHC4051A
Leakage Current, HC4052A Switch–to–Switch =
Channel–to–Channel HC4053A – V ; (Figure 5)
V
= V or V
;
6.0
6.0
6.0
– 6.0
– 6.0
– 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
µA
in
IL
IH
V
CC
EE
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
V
CC
V
Symbol
Parameter
Unit
–55 to 25°C
≤85°C
≤125°C
t
t
t
,
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
3.0
4.5
6.0
270
90
59
320
110
79
350
125
85
ns
PLH
t
PHL
45
65
75
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
3.0
4.5
6.0
40
25
12
10
60
30
15
13
70
32
18
15
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
6.0
160
70
48
200
95
63
220
110
76
PLZ
t
PHZ
39
55
63
t
t
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
6.0
245
115
49
315
145
69
345
155
83
PZL
PZH
39
58
67
C
Maximum Input Capacitance, Channel–Select or Enable Inputs
10
35
10
35
10
35
pF
pF
in
C
Maximum Capacitance
(All Switches Off)
Analog I/O
I/O
Common O/I: HC4051A
HC4052A
130
80
130
80
130
80
HC4053A
50
50
50
Feedthrough
1.0
1.0
1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D)
Typical @ 25°C, V
= 5.0 V, V
= 0 V
EE
CC
C
Power Dissipation Capacitance (Figure 13)*
HC4051A
HC4052A
HC4053A
pF
45
80
45
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
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5
MC74HC4051A, MC74HC4052A, MC74HC4053A
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Limit*
25°C
‘52
V
V
CC
V
EE
V
Symbol
Parameter
Condition
= 1MHz Sine Wave; Adjust f Voltage to
Unit
BW
Maximum On–Channel Bandwidth
or Minimum Frequency Response
(Figure 6)
f
‘51
‘53
MHz
in
in
Obtain 0dBm at V ; Increase f
OS
Frequency Until dB Meter Reads –3dB;
= 50Ω, C = 10pF
in
2.25
4.50
6.00
80
80
80
95
95
95
120
120
120
–2.25
–4.50
–6.00
R
L
L
—
—
Off–Channel Feedthrough Isolation
(Figure 7)
f
= Sine Wave; Adjust f Voltage to
in
2.25 –2.25
4.50 –4.50
–50
–50
–50
dB
in
Obtain 0dBm at V
IS
f
in
= 10kHz, R = 600Ω, C = 50pF 6.00 –6.00
L L
2.25 –2.25
4.50 –4.50
–40
–40
–40
f
in
= 1.0MHz, R = 50Ω, C = 10pF 6.00 –6.00
L L
Feedthrough Noise.
Channel–Select Input to Common
I/O (Figure 8)
V
≤ 1MHz Square Wave (t = t = 6ns);
2.25 –2.25
4.50 –4.50
25
105
135
mV
PP
in
r
f
Adjust R at Setup so that I = 0A;
Enable = GND
L
S
R
= 600Ω, C = 50pF 6.00 –6.00
L
L
2.25 –2.25
4.50 –4.50
= 10kΩ, C = 10pF 6.00 –6.00
35
145
190
R
L
L
—
Crosstalk Between Any Two
Switches (Figure 12)
(Test does not apply to HC4051A)
f
= Sine Wave; Adjust f Voltage to
in
2.25 –2.25
4.50 –4.50
–50
–50
–50
dB
in
Obtain 0dBm at V
IS
f
in
= 10kHz, R = 600Ω, C = 50pF 6.00 –6.00
L L
2.25 –2.25
4.50 –4.50
= 1.0MHz, R = 50Ω, C = 10pF 6.00 –6.00
–60
–60
–60
f
in
L
L
THD
Total Harmonic Distortion
(Figure 14)
f
= 1kHz, R = 10kΩ, C = 50pF
%
in
THD = THD
L
L
– THD
= 4.0V
= 8.0V
measured
source
V
sine wave
sine wave
sine wave
2.25 –2.25
4.50 –4.50
6.00 –6.00
0.10
0.08
0.05
IS
V
PP
PP
PP
IS
V
IS
= 11.0V
*Limits not tested. Determined by design and verified by qualification.
180
160
140
300
250
200
120
100
80
125°C
125°C
150
25°C
25°C
–55°C
100
60
–55°C
40
50
0
20
0
0
0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25
0
0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS EE
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS EE
Figure 1a. Typical On Resistance, V
CC
– V
EE
= 2.0 V
Figure 1b. Typical On Resistance, V
CC
– V = 3.0 V
EE
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MC74HC4051A, MC74HC4052A, MC74HC4053A
105
90
120
100
80
75
125°C
125°C
60
25°C
60
45
30
15
0
25°C
–55°C
40
20
0
–55°C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS EE
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS EE
Figure 1c. Typical On Resistance, V
– V
EE
= 4.5 V
Figure 1d. Typical On Resistance, V – V
CC EE
= 6.0 V
CC
80
70
60
50
40
30
20
60
50
40
30
20
125°C
25°C
125°C
–55°C
25°C
–55°C
10
0
10
0
–4.5 –3.5 –2.5 –1.5 –0.5
0.5
1.5
2.5
3.5
4.5
–6.0 –5.0 –4.0 –3.0 –2.0 –1.0
0
1.0 2.0 3.0 4.0 5.0 6.0
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
EE
IS
EE
Figure 1e. Typical On Resistance, V
– V
EE
= 9.0 V
Figure 1f. Typical On Resistance, V
– V = 12.0 V
EE
CC
CC
PLOTTER
PROGRAMMABLE
POWER
MINI COMPUTER
DC ANALYZER
SUPPLY
–
+
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
V
EE
GND
Figure 2. On Resistance Test Set–Up
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MC74HC4051A, MC74HC4052A, MC74HC4053A
V
CC
V
CC
V
V
CC
CC
16
16
V
V
EE
EE
ANALOG I/O
OFF
OFF
OFF
OFF
A
V
V
CC
V
CC
COMMON O/I
NC
COMMON O/I
V
6
7
8
6
7
8
IH
IH
V
EE
V
EE
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set–Up
V
CC
16
V
OS
V
V
CC
V
CC
16
0.1µF
A
dB
METER
f
in
ON
ON
N/C
R
L
C *
L
EE
COMMON O/I
OFF
V
CC
ANALOG I/O
V
IL
6
7
8
6
7
8
V
EE
V
EE
*Includes all probe and jig capacitance
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set–Up
Figure 6. Maximum On Channel Bandwidth,
Test Set–Up
V
CC
16
V
CC
16
V
IS
V
OS
0.1µF
dB
METER
R
L
f
in
OFF
ON/OFF
OFF/ON
COMMON O/I
TEST
ANALOG I/O
R
L
R
L
C *
L
POINT
R
L
C *
L
R
L
6
7
8
6
7
8
V
CC
V ≤ 1 MHz
in
11
t = t = 6 ns
r
f
V
EE
V
EE
V
CC
GND
CHANNEL SELECT
*Includes all probe and jig capacitance
CHANNEL SELECT
*Includes all probe and jig capacitance
V
IL
or V
IH
Figure 7. Off Channel Feedthrough Isolation,
Test Set–Up
Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set–Up
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8
MC74HC4051A, MC74HC4052A, MC74HC4053A
V
CC
16
V
CC
V
CC
ON/OFF
OFF/ON
COMMON O/I
C *
CHANNEL
SELECT
TEST
POINT
50%
ANALOG I/O
GND
L
t
t
PHL
PLH
6
7
8
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set–Up Channel
Select to Analog Out
V
CC
16
COMMON O/I
C *
ANALOG I/O
TEST
POINT
V
CC
ON
ANALOG
IN
50%
L
GND
t
t
PHL
PLH
6
7
8
ANALOG
OUT
50%
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In
to Analog Out
Figure 10b. Propagation Delay, Test Set–Up
Analog In to Analog Out
t
t
POSITION 1 WHEN TESTING t
POSITION 2 WHEN TESTING t
AND t
AND t
f
r
PHZ
PLZ
PZH
PZL
1
2
V
CC
90%
50%
10%
ENABLE
V
CC
16
GND
1kΩ
V
CC
t
t
PZL PLZ
HIGH
IMPEDANCE
1
2
ANALOG I/O
ENABLE
TEST
POINT
ON/OFF
ANALOG
OUT
50%
C *
L
10%
V
OL
t
t
PZH PHZ
6
7
8
V
OH
90%
ANALOG
OUT
50%
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set–Up
Enable to Analog Out
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9
MC74HC4051A, MC74HC4052A, MC74HC4053A
V
CC
V
IS
A
V
CC
16
16
R
L
V
OS
ON/OFF
OFF/ON
COMMON O/I
f
in
ON
NC
ANALOG I/O
0.1µF
OFF
V
EE
R
L
R
L
C *
L
C *
L
V
CC
R
L
6
7
8
6
7
8
11
V
EE
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 12. Crosstalk Between Any Two
Switches, Test Set–Up
Figure 13. Power Dissipation Capacitance,
Test Set–Up
0
–10
–20
–30
–40
V
IS
FUNDAMENTAL FREQUENCY
V
CC
16
V
OS
0.1µF
TO
f
in
DISTORTION
METER
ON
R
L
C *
L
–50
–60
–70
–80
–90
–100
DEVICE
SOURCE
6
7
8
V
EE
*Includes all probe and jig capacitance
1.0
2.0
3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set–Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at outputs to V
or GND through a low value resistor helps
CC
or GND logic levels. V being recognized as a logic
V
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
CC
CC
high and GND being recognized as a logic low. In this
example:
V
= +5V = logic high
CC
GND = 0V = logic low
V
– GND = 2 to 6 volts
– GND = 0 to –6 volts
CC
The maximum analog voltage swings are determined by
V
V
EE
CC
thesupplyvoltagesV andV . Thepositivepeakanalog
CC EE
– V = 2 to 12 volts
EE
voltageshouldnotexceedV .Similarly,thenegativepeak
CC
and V ≤ GND
EE
analog voltage should not go below V . In this example,
EE
thedifferencebetweenV andV istenvolts.Therefore,
CC EE
WhenvoltagetransientsaboveV and/orbelowV are
CC EE
anticipated on the analog channels, external Germanium or
Schottky diodes (D ) are recommended as shown in Figure
16. These diodes should be able to absorb the maximum
anticipated current surges during clipping.
using the configuration of Figure 15, a maximum analog
signal of ten volts peak–to–peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
x
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10
MC74HC4051A, MC74HC4052A, MC74HC4053A
V
V
CC
CC
+5V
V
CC
16
ON/OFF
D
D
x
16
x
+5V
–5V
+5V
–5V
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
D
D
x
x
V
EE
V
EE
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
6
7
8
11
10
9
7
8
–5V
V
EE
Figure 15. Application Example
Figure 16. External Germanium or
Schottky Clipping Diodes
+5V
16
+5V
16
+5V
+5V
+5V
+5V
ANALOG
SIGNAL
ANALOG
ANALOG
SIGNAL
ANALOG
ON/OFF
ON/OFF
SIGNAL
SIGNAL
V
EE
V
EE
V
EE
V
EE
+5V
*
R
R
R
+5V
6
7
8
11
10
9
6
7
8
11
10
9
LSTTL/NMOS
CIRCUITRY
LSTTL/NMOS
CIRCUITRY
V
EE
V
EE
* 2K ≤ R ≤ 10K
HCT
BUFFER
a. Using Pull–Up Resistors
b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
11
10
9
13
X0
LEVEL
SHIFTER
A
14
X1
15
X2
LEVEL
SHIFTER
B
C
12
X3
1
LEVEL
SHIFTER
X4
5
X5
6
2
LEVEL
SHIFTER
ENABLE
X6
4
X7
3
X
Figure 18. Function Diagram, HC4051A
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11
MC74HC4051A, MC74HC4052A, MC74HC4053A
10
12
14
15
LEVEL
SHIFTER
A
B
X0
X1
X2
9
LEVEL
SHIFTER
11
13
1
X3
X
6
LEVEL
SHIFTER
ENABLE
Y0
5
2
4
3
Y1
Y2
Y3
Y
Figure 19. Function Diagram, HC4052A
11
10
9
13
LEVEL
SHIFTER
A
X1
12
14
1
X0
X
LEVEL
SHIFTER
B
C
Y1
2
15
3
Y0
Y
LEVEL
SHIFTER
Z1
5
4
Z0
Z
6
LEVEL
SHIFTER
ENABLE
Figure 20. Function Diagram, HC4053A
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12
MC74HC4051A, MC74HC4052A, MC74HC4053A
ORDERING & SHIPPING INFORMATION
Device
MC74HC4051AN
Package
PDIP–16
Shipping
500 Units / Unit Pak
48 Units / Rail
MC74HC4051AD
SOIC–16
MC74HC4051ADR2
MC74HC4051ADT
MC74HC4051ADTR2
MC74HC4051ADW
MC74HC4051ADWR2
MC74HC4051AF
SOIC–16
2500 Units / Tape & Reel
96 Units / Rail
TSSOP–16
TSSOP–16
SOIC WIDE
SOIC WIDE
SOEIAJ–16
SOEIAJ–16
PDIP–16
2500 Units / Tape & Reel
48 Units / Rail
1000 Units / Tape & Reel
See Note 1.
MC74HC4051AFEL
MC74HC4052AN
See Note 1.
500 Units / Unit Pak
48 Units / Rail
MC74HC4052AD
SOIC–16
MC74HC4052ADR2
MC74HC4052ADT
MC74HC4052ADTR2
MC74HC4052ADW
MC74HC4052ADWR2
MC74HC4052AF
SOIC–16
2500 Units / Tape & Reel
96 Units / Rail
TSSOP–16
TSSOP–16
SOIC WIDE
SOIC WIDE
SOEIAJ–16
SOEIAJ–16
PDIP–16
2500 Units / Tape & Reel
48 Units / Rail
1000 Units / Tape & Reel
See Note 1.
MC74HC4052AFEL
MC74HC4053AN
See Note 1.
500 Units / Unit Pak
48 Units / Rail
MC74HC4053AD
SOIC–16
MC74HC4053ADR2
MC74HC4053ADT
MC74HC4053ADTR2
MC74HC4053ADW
MC74HC4053ADWR2
MC74HC4053AF
SOIC–16
2500 Units / Tape & Reel
96 Units / Rail
TSSOP–16
TSSOP–16
SOIC WIDE
SOIC WIDE
SOEIAJ–16
SOEIAJ–16
2500 Units / Tape & Reel
48 Units / Rail
1000 Units / Tape & Reel
See Note 1.
MC74HC4053AFEL
See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
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13
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
C
L
0.250 0.270
0.145 0.175
0.015 0.021
0.040 0.070
0.100 BSC
6.35
3.69
0.39
1.02
6.85
4.44
0.53
S
1.77
SEATING
PLANE
–T
–
G
H
J
K
L
M
S
2.54 BSC
1.27 BSC
0.38
3.30
7.74
0.050 BSC
M
K
0.008 0.015
0.110 0.130
0.295 0.305
0.21
2.80
7.50
0°
H
J
G
D 16 PL
0°
10°
10°
M
M
0.25 (0.010)
T
A
0.020 0.040
0.51
1.01
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN MAX
DIM MIN
MAX
A
B
C
D
F
G
J
K
M
P
9.80 10.00
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
1.27 BSC
–T
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEAT–ING
M
PLANE
D 16 PL
0°
7°
5.80
0.25
6.20
0.50
0.229 0.244
0.010 0.019
M
S
S
0.25 (0.010)
T
B
A
R
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14
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
SOIC–16 WIDE
DW SUFFIX
CASE 751G–03
ISSUE B
A
D
16
9
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
8
MILLIMETERS
B
16X B
DIM MIN
MAX
2.65
0.25
0.49
0.32
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
M
S
S
0.25
T A
B
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
0.25
0.50
0
0.75
0.90
7
SEATING
PLANE
L
14X
e
C
T
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
NOTES:
S
0.15 (0.006) T U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
B
–U–
SECTION N–N
L
0.25 (0.010) PER SIDE.
J
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
–V–
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
C
4.90
4.30
–––
5.10 0.193
4.50 0.169
1.20
F
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
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15
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
ISSUE O
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
A
–––
0.05
0.35
0.18
9.90
5.10
2.05
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
1
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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PUBLICATION ORDERING INFORMATION
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EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
For additional information, please contact your local
Sales Representative.
*Available from Germany, France, Italy, England, Ireland
MC74HC4051A/D
相关型号：
MC74HC4052DTR2
Differential Multiplexer, 1 Func, 4 Channel, CMOS, PDSO16, PLASTIC, TSSOP-16
MOTOROLA
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