MC74HC4094ADG [ONSEMI]
8-Bit Shift and Store Register;
| 型号： | MC74HC4094ADG |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Shift and Store Register |
| 文件： | 总12页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC4094A
8-Bit Shift and Store
Register
High−Performance Silicon−Gate CMOS
The MC74HC4094A is a high speed CMOS 8−bit serial shift and
storage register. This device consists of an 8−bit shift register and latch
with 3−state output buffers. Data is shifted on positive clock (CP)
transitions. The data in the shift register is transferred to the storage
register when the Strobe (STR) input is high. The output buffers are
enabled when the Output Enable (OE) input is set high. Two serial
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
outputs (QS , QS ) are available for cascading multiple devices.
1
2
HC4094AG
AWLYWW
16
Features
1
1
• Wide Operating Voltage Range: 2.0 to 6.0 V
• Low Power Dissipation: I = < 10 mA
CC
16
• In Compliance with the Requirements Defined by JEDEC
HC
4094A
ALYWG
G
Standard No. 7A
TSSOP−16
DT SUFFIX
CASE 948F
16
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
1
1
• These are Pb−Free Devices
A
= Assembly Location
= Wafer Lot
= Year
Typical Applications
WL, L
YY, Y
• Serial−to−Parallel Conversion
• Remote Control Storage Register
WW, W = Work Week
G, G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
February, 2015 − Rev. 2
MC74HC4094A/D
MC74HC4094A
1
3
1
C2
15
EN3
CP
STR
SRG8
C1/
3
2
QS1
QS2
QP0
QP1
QP2
QP3
QP4
QP5
QP6
QP7
9
STR
D
1
2
3
4
5
6
7
8
16
V
CC
10
15 OE
14 QP
13 QP
12 QP
11 QP
10 QS
4
4
1 D
2 D
3
CP
4
5
6
7
2
1
5
6
5
QP
QP
QP
QP
0
1
2
3
6
2
D
7
7
14
13
14
13
GND
9
QS
12
11
12
11
Figure 1. Pin Assignment
OE
15
9
10
Figure 2. Logic Symbol
Figure 3. IEC Logic Symbol
2
3
D
QS2
QS1
10
8 – Stage Shift Register
8 – Bit Storage Register
3 – Stage Outputs
CP
9
1
STR
15
OE
QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7
14 13 12 11
4
5
6
7
Figure 4. Functional Diagram
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2
MC74HC4094A
STAGE 0
STAGES 1 TO 6
STAGE 7
Q
Q
D
D
Q
D
D
QS1
QS2
CP
CP
Q
D
FF7
FF0
CP
CP
CP
latch
D
Q
D
Q
CP
CP
latch
latch
STR
OE
QP0 QP1 QP2 QP3 QP4 QP5 QP6
QP7
Figure 5. Logic Diagram
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3
MC74HC4094A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
20
35
75
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating − SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
6.0
V , V
in out
DC Input Voltage, Output Voltage
(Referenced to GND)
V
CC
V
T
A
Operating Temperature, All Package Types
–55
+125
°C
t , t
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
r
f
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4
MC74HC4094A
FUNCTIONAL TABLE
INPUTS
PARALLEL OUTPUTS
SERIAL OUTPUTS
CP
↑
OE
STR
X
D
X
X
X
L
QP0
Z
QPn
Z
QS1
Q’6
NC
Q’6
Q’6
Q’6
NC
QS2
NC
L
L
↓
X
Z
Z
QP7
NC
↑
H
H
H
H
L
NC
L
NC
↑
H
QPn−1
QPn−1
NC
NC
↑
H
H
H
H
NC
↓
H
NC
QP7
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF−state
NC = no change
↑ = LOW−to−HIGH CP transition
↓ = HIGH−to−LOW CP transition
Q’6 = the information in the seventh register stage is transferred to the 8th register stage and QSn output at the positive clock edge
CLOCK INPUT
CP
DATA INPUT
D
STROBE INPUT
STR
OUTPUT ENABLE INPUT OE
INTERNAL Q’0
OUTPUT
FF0
QP0
Z−state
Z−state
INTERNAL Q’6
OUTPUT
FF6
QP6
SERIAL OUTPUT
SERIAL OUTPUT
QS1
QS2
Figure 6. Timing Diagram
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5
MC74HC4094A
DC CHARACTERISTICS
Guaranteed Limits
−555C to 255C
≤ 855C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
2.9
4.4
5.9
2.7
4.2
5.7
0.1
0.1
0.1
0.1
0.3
0.3
0.3
1
≤ 1255C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
2.9
4.4
5.9
2.6
4.1
5.6
0.1
0.1
0.1
0.1
0.4
0.4
0.4
1
Symbol
Parameter
Test Conditions
V
CC
(V)
Unit
V
IH
Minimum High−Level Input
Voltage
V
⎟I
= 0.1 V or V – 0.1 V
2.0
1.5
V
OUT
OUT
CC
⎟ ≤ 20 mA
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
3.0
4.5
6.0
6.0
2.1
3.15
4.2
V
IL
Maximum Low−Level Input
Voltage
V
⎟I
= 0.1 V or V – 0.1 V
0.5
V
V
OUT
OUT
CC
⎟ ≤ 20 mA
0.9
1.35
1.8
V
OH
Minimum High−Level Output
Voltage
V
IN
= V or V
IL
1.9
IH
⎟I
OUT
⎟ ≤ 20 mA
2.9
4.4
5.9
V
IN
V
IN
V
IN
V
IN
= V or V , ⎟I
⎟ = 2.4 mA
⎟ = 4 mA
IL OUT
2.75
4.25
5.75
0.1
IH
IL OUT
= V or V , ⎟I
IH
= V or V , ⎟I
⎟ = 5.2 mA
⎟ ≤ 20 mA
IH
IL OUT
V
OL
Maximum Low−Level Output
Voltage
= V or V , ⎟I
V
IH
IL OUT
0.1
0.1
0.1
V
IN
V
IN
V
IN
V
IN
= V or V , ⎟I
⎟ = 2.4 mA
⎟ = 4 mA
IL OUT
0.25
0.25
0.25
0.1
IH
IL OUT
= V or V , ⎟I
IH
= V or V , ⎟I
⎟ = 5.2 mA
IH
IL OUT
I
IN
Maximum Input Leakage
Current
= V or GND
mA
mA
mA
CC
I
Maximum Tri−State Output
Leakage Current
V
V
= V or GND
6.0
6.0
0.5
4.0
5
10
80
OZ
IN
OUT
CC
= V or GND
CC
I
Maximum Quiescent Supply
Current
V
IN
= V or GND
40
CC
CC
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MC74HC4094A
AC CHARACTERISTICS (t = t = 6 ns, C = 50 pF)
f
r
L
Guaranteed Limits
−555C to 255C
≤ 855C
150
100
38
≤ 1255C
170
110
45
Symbol
, t
Parameter
Test Conditions
V
CC
(V)
Unit
t
t
t
t
Maximum Propagation Delay
Figure 7
2.0
120
90
30
26
120
90
27
23
120
90
39
33
120
90
36
31
120
80
35
30
100
70
25
21
70
40
18
16
80
50
16
14
80
50
16
14
50
30
10
9
ns
PHL PLH
CP to QS
1
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
33
38
, t
Maximum Propagation Delay
CP to QS
Figure 7
Figure 7
Figure 8
Figure 9
Figure 9
Figure 7
Figure 7
Figure 8
Figure 10
150
100
34
170
110
41
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHL PLH
2
29
35
, t
Maximum Propagation Delay
CP to QP
150
100
49
170
110
59
PHL PLH
n
42
50
, t
Maximum Propagation Delay
STR to QP
150
100
45
170
110
54
PHL PLH
n
38
46
t
t
, t
Maximum 3−State Output Enable Time
OE to QP
140
100
44
160
120
53
PZH PZL
n
37
45
, t
Maximum 3−State Output Enable Time
OE to QP
120
90
140
110
38
PHZ PLZ
n
31
26
32
t
, t
Maximum Output Transition Time
90
110
80
THL TLH
60
22
25
19
22
t
t
Minimum Clock Pulse Width
High or Low
100
60
120
80
W
20
24
17
20
Minimum Strobe Pulse Width
High
100
60
120
80
W
20
24
17
20
t
Minimum Set−up Time
D to CP
65
75
SU
35
45
13
15
11
13
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7
MC74HC4094A
AC CHARACTERISTICS (t = t = 6 ns, C = 50 pF)
f
r
L
Guaranteed Limits
−555C to 255C
≤ 855C
125
75
25
21
3
≤ 1255C
Symbol
Parameter
Minimum Set−up Time
Test Conditions
V
(V)
Unit
CC
t
Figure 8
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
−
100
60
20
17
3
150
90
30
26
3
ns
SU
CP to STR
t
h
t
h
Minimum Hold Time
D to CP
Figure 10
Figure 8
Figure 7
ns
ns
3
3
3
3
3
3
3
3
3
Minimum Hold Time
CP to STR
0
0
0
0
0
0
0
0
0
0
0
0
f
Minimum Clock Pulse Frequency
6
5
4
MHz
MAX
18
30
35
10
15
140
14
24
28
10
15
140
12
20
24
10
15
140
C
Maximum Input Capacitance
Maximum Output Capacitance
pF
pF
pF
in
C
−
out
PD
C
Power Dissipation Capacitance (Note 2)
−
2. C is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from:
PD
I
(operating) ≈ C x V x f x N
where N
= total number of outputs switching and f = switching frequency.
CC
PD
CC
IN
SW
SW
IN
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8
MC74HC4094A
AC WAVEFORMS
1/f
MAX
CP Input
50%
CP Input
50%
t
w
t
su
t
h
t
PHL
t
PLH
QPn, QS1
Output
STR Input
50%
50%
t
W
t
THL
t
TLH
t
t
PHL
PLH
t
t
PHL
PLH
QS2 Output
QPn Output
50%
50%
t
t
THL
TLH
Figure 7. Waveforms showing the clock
(CP) to output (QPn, QS1, QS2) propagation
delays, the clock pulse width and the
maximum clock frequency.
Figure 8. Waveforms showing the strobe
(STR) to output (QPn) propagation delays,
the strobe pulse width, the clock set−up
and hold times for the strobe input.
t
f
t
r
90%
50%
10%
OE Input
50%
CP Input
D Input
t
su
t
su
t
t
PZL
PLZ
t
h
t
h
QPn Output:
Low − to − Off
Off − to − Low
50%
50%
10%
90%
t
t
PZH
PHZ
QPn Output:
High − to − Off
Off − to − High
QPn, QS1, QS2
Output
50%
50%
Outputs
Enabled
Outputs
Disabled
Outputs
Enabled
The shaded areas indicate when
the input is permitted to change for
predictable output performance.
Figure 9. Waveforms showing the 3−state
enable and disable times for input OE.
Figure 10. Waveforms showing the data
set−up and hold times for the data input.
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9
MC74HC4094A
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kW
CONNECT TO V WHEN
.
CC
TESTING t AND t
OUTPUT
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 11. AC Characteristics Load Circuits
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC4094ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC4094ADR2G
MC74HC4094ADTG
MC74HC4094ADTR2G
NLVHC4094BDTR2G*
SOIC−16
(Pb−Free)
2500 / Tape & Reel
96 Units / Rail
TSSOP−16
(Pb−Free)
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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10
MC74HC4094A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16X KREF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
U
0.15 (0.006) T
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T
U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
M
−V−
A
B
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
D
G
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
MC74HC4094A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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