MC74HC4538AN [ONSEMI]
Dual Precision Monostable Multivibrator(Retriggerable, Resettable); 双精密单稳多谐振荡器（可重触发，复位）
| 型号： | MC74HC4538AN |
| 厂家： | 
ONSEMI |
| 描述： | Dual Precision Monostable Multivibrator(Retriggerable, Resettable) |
| 文件： | 总16页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC4538A
Dual Precision Monostable
Multivibrator (Retriggerable,
Resettable)
The MC74HC4538A is identical in pinout to the MC14538B. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs.
This dual monostable multivibrator may be triggered by either the
positive or the negative edge of an input pulse, and produces a
precision output pulse over a wide range of pulse widths. Because the
device has conditioned trigger inputs, there are no trigger–input rise
and fall time restrictions. The output pulse width is determined by the
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MARKING
DIAGRAMS
16
16
MC74HC4538AN
AWLYYWW
1
external timing components, R and C . The device has a reset
x
x
PDIP–16
N SUFFIX
CASE 648
function which forces the Q output low and the Q output high,
regardless of the state of the output pulse circuitry.
1
• Unlimited Rise and Fall Times Allowed on the Trigger Inputs
• Output Pulse is Independent of the Trigger Pulse Width
• ± 10% Guaranteed Pulse Width Variation from Part to Part (Using
the Same Test Jig)
16
16
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 3.0 to 6.0 V
HC4538A
AWLYWW
1
SO–16
D SUFFIX
CASE 751B
1
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
16
16
• Chip Complexity: 145 FETs or 36 Equivalent Gates
HC
1
4538A
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
GND
C 1/R 1
1
2
3
4
5
6
7
8
16
15 GND
14 C 2/R 2
V
CC
1
X
X
RESET 1
A1
X
X
13 RESET 2
12 A2
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
B1
Q1
11 B2
W, WW = Work Week
Q1
10 Q2
GND
9
Q2
ORDERING INFORMATION
Figure 1. Pin Assignment
Device
Package
PDIP–16
SOIC–16
SOIC–16
TSSOP–16
Shipping
MC74HC4538AN
MC74HC4538AD
2000/Box
48/Rail
MC74HC4538ADR2
MC74HC4538ADT
MC74HC4538ADTR2
2500/Reel
96/Rail
TSSOP–16 2500/Reel
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
April, 2001 – Rev. 8
MC74HC4538A/D
MC74HC4538A
C 1
X
R 1
X
V
CC
1
2
6
7
4
5
Q1
Q1
A1
B1
TRIGGER
INPUTS
3
RESET 1
C 2
X
R 2
X
V
CC
15 14
10
12
Q2
Q2
A2
B2
TRIGGER
INPUTS
11
9
13
PIN 16 = V
RESET 2
CC
PIN 8 = GND
R
AND C ARE EXTERNAL COMPONENTS
X
X
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
Figure 2. Logic Diagram
FUNCTION TABLE
Inputs
A
Outputs
Reset
B
Q
Q
H
H
H
L
H
H
X
H
L
X
Not Triggered
Not Triggered
H
H
L,H,
L
H
L,H,
Not Triggered
Not Triggered
L
X
X
X
X
L
H
Not Triggered
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2
MC74HC4538A
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
*0.5 to )7.0
V
V
*0.5 v V v V )0.5
V
I
I
CC
DC Output Voltage
DC Input Diode Current
(Note 2)
*0.5 v V v V )0.5
V
O
O
CC
I
IK
A, B, Reset
$20
$30
mA
C , R
X
X
I
I
I
I
DC Output Diode Current
$25
$25
mA
mA
mA
mA
_C
OK
DC Output Sink Current
O
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
$100
$100
CC
GND
T
T
T
q
*65 to )150
260
STG
Lead temperature, 1 mm from Case for 10 Seconds
Junction temperature under Bias
Thermal resistance
_C
L
J
)150
_C
_C/W
PDIP
SOIC
TSSOP
78
112
148
JA
P
D
Power Dissipation in Still Air at 85_C
PDIP
SOIC
TSSOP
750
500
450
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% – 35%
UL–94–VO (0.125 in)
V
ESD
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
>2000
>100
>500
V
I
Latch–Up Performance
Above V and Below GND at 85_C (Note 6)
$300
mA
Latch–Up
CC
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated
conditions is not implied.
2. I absolute maximum rating must be observed.
O
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
7. For high frequency or heavy load considerations, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
3.0*
0
Max
Unit
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
CC
V , V
in out
V
CC
V
T
A
–55
+125
_C
ns
t , t
r
Input Rise and Fall Time
(Figure 7)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
–
1000
500
400
f
A or B (Figure 5)
No Limit
R
C
External Timing Resistor
V
< 4.5 V
≥ 4.5 V
1.0
2.0
†
†
kW
mF
x
x
CC
V
CC
External Timing Capacitor
0
†
*The HC4538A will function at 2.0 V but for optimum pulse–width stability, V should be above 3.0 V.
CC
†The maximum allowable values of R and C are a function of the leakage of capacitor C , the leakage of the HC4538A, and leakage due to board layout
x
x
x
and surface resistance. For most applications, C /R should be limited to a maximum value of 10 mF/1.0 MW. Values of C > 1.0 mF may cause a
x
x
x
problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for R > 1.0 MW.
x
8. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
9. Information on typical parametric values can be found in the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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3
MC74HC4538A
DC CHARACTERISTICS
Guaranteed Limits
–55 to 25_C
v 85_C
v 125_C
V
Volts
CC
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
= 0.1 V or V – 0.1 V
Unit
V
V
V
Minimum High–Level
Input Voltage
V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
IH
out
CC
|I | v 20 µA
out
Maximum Low–Level
Input Voltage
V
out
= 0.1 V or V – 0.1 V
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
IL
CC
|I | v 20 µA
out
Minimum High–Level
Output Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
OH
IH
|I | v 20 µA
out
V
in
= V or V
IH IL
|I | v –4.0 mA
|I | v –5.2 mA
out
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
out
V
OL
Maximum Low–Level
Output Voltage
V
= V or V
IL
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
|I | v 20 µA
out
V
in
= V or V
IH IL
|I | v 4.0 mA
|I | v 5.2 mA
out
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
out
I
I
I
Maximum Input
Leakage Current
(A, B, Reset)
V
V
V
= V or GND
6.0
6.0
6.0
± 0.1
± 50
130
± 1.0
± 500
220
± 1.0
± 500
350
µA
nA
µA
in
in
in
in
CC
Maximum Input
Leakage Current
= V or GND
CC
in
(R , C )
x
x
Maximum Quiescent
Supply Current
(per package)
= V or GND
CC
CC
Q1 and Q2 = Low
I
= 0 µA
out
Standby State
I
Maximum Supply
Current
(per package)
Active State
V
= V or GND
CC
in
CC
25_C
–45_C to 85_C
–55_C to 125_C
Q1 and Q2 = High
I = 0 µA
out
Pins 2 and 14 = 0.5 V
400
600
800
CC
6.0
µA
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MC74HC4538A
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limits
–55 to 25_C
v 85_C
v 125_C
V
Volts
CC
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Unit
t
t
t
t
Maximum Propagation Delay
Input A or B to Q
(Figures 6 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
PLH
PHL
PHL
PLH
Maximum Propagation Delay
Input A or B to NQ
(Figures 6 and 8)
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
ns
ns
ns
ns
pF
Maximum Propagation Delay
Reset to Q
(Figures 7 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
Maximum Propagation Delay
Reset to NQ
(Figures 7 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
t
t
Maximum Output Transition Time, Any Output
(Figures 7 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
TLH,
THL
C
Maximum Input Capacitance
(A. B, Reset)
(C , R )
—
10
25
10
25
10
25
in
x
x
10.For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
150
C
Power Dissipation Capacitance (per Multivibrator)*
pF
PD
2
*Used to determine the no–load dynamic power consumption: P = C
V
f + I V . For load considerations, see the ON Semiconductor
CC CC
D
PD CC
High–Speed CMOS Data Book (DL129/D).
TIMING CHARACTERISTICS (Input t = t = 6.0 ns)
r
f
Guaranteed Limits
–55 to 25_C
v 85_C
v 125_C
V
Volts
CC
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Unit
t
t
t
Minimum Recovery Time, Inactive to A or B
(Figure 7)
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
rec
Minimum Pulse Width, Input A or B
(Figure 6)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
ns
ns
w
Minimum Pulse Width, Reset
(Figure 7)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
w
t , t
r
Maximum Input Rise and Fall Times, Reset
(Figure 7)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
f
A or B
(Figure 7)
2.0
4.5
6.0
No Limit
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MC74HC4538A
OUTPUT PULSE WIDTH CHARACTERISTICS (C = 50 pF)t
L
Conditions
Guaranteed Limits
–55 to 25_C
v 85_C
v 125_C
V
Volts
CC
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Timing Components
Unit
τ
Output Pulse Width*
(Figures 6 and 8)
R = 10 kΩ, C = 0.1 µF
5.0
0.63
0.77
0.6
0.8
0.59
0.81
ms
x
x
—
—
Pulse Width Match
Between Circuits in the
same Package
—
—
—
—
± 5.0
%
%
Pulse Width Match
± 10
Variation (Part to Part)
*For output pulse widths greater than 100 µs, typically τ = kR C , where the value of k may be found in Figure 3.
x
x
0.8
0.7
0.6
0.5
0.4
0.3
10 s
1 s
T = 25°C
A
V
= 5 V, T = 25°C
A
CC
100 ms
10 ms
1 ms
1 MΩ
100 µs
10 µs
100 kΩ
10 kΩ
1 kΩ
1 µs
100 ns
1
2
3
4
5
6
7
0.00001 0.0001 0.001 0.01
0.1
1
10
100
V
CC
, POWER SUPPLY VOLTAGE (VOLTS)
CAPACITANCE (µF)
Figure 3. Typical Output Pulse Width Constant,
k, versus Supply Voltage
Figure 4. Output Pulse Width versus Timing Capacitance
(For output pulse widths > 100 µs: τ = kRxCx)
1.1
R = 100 kΩ
x
T = 25°C
A
C = 1000 pF
x
1
0.9
0.8
0.7
R = 1 MΩ
C = 0.1 µF
x
x
0.6
0.5
1
2
3
4
5
6
7
V
CC
, POWER SUPPLY VOLTAGE (VOLTS)
Figure 5. Normalized Output Pulse Width versus Power Supply Voltage
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6
MC74HC4538A
1.1
1.05
1
V
CC
= 6 V
R = 10 kΩ
C = 0.1 µF
x
x
0.95
0.9
0.85
0.8
V
CC
= 3 V
–75 –50 –25
0
25
50
75 100 125 150
T , AMBIENT TEMPERATURE (°C)
A
Figure 6. Normalized Output Pulse Width versus Power Supply Voltage
1.03
R = 10 kΩ
C = 0.1 µF
x
1.02
1.01
1
x
V
CC
= 5.5 V
0.99
V
= 5 V
CC
0.98
0.97
V
= 4.5 V
CC
–75 –50 –25
0
25
50
75 100 125 150
T , AMBIENT TEMPERATURE (°C)
A
Figure 7. Normalized Output Pulse Width versus Power Supply Voltage
t
w(H)
V
CC
50%
A
B
GND
t
w(L)
V
CC
50%
GND
t
t
PLH
τ
τ
PLH
50%
Q
Q
t
t
τ
τ
PHL
PHL
50%
Figure 8. Switching Waveform
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7
MC74HC4538A
t
r
t
f
V
CC
90%
10%
GND
A
t
rr
V
CC
50%
GND
B
t
f
t
f
V
CC
90%
10%
50%
RESET
GND
t
t
w(L)
rec
t
τ + t
TLH
rr
t
PHL
90%
10%
(RETRIGGERED PULSE)
50%
50%
Q
Q
t
t
PLH
THL
90%
10%
50%
Figure 9. Switching Waveform
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 10. Test Circuit
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MC74HC4538A
PIN DESCRIPTIONS
INPUTS
capacitors (see the Block Diagram). Polystyrene capacitors
are recommended for optimum pulse width control.
Electrolytic capacitors are not recommended due to high
leakages associated with these type capacitors.
A1, A2 (Pins 4, 12)
Positive–edge trigger inputs. A rising–edge signal on
either of these pins triggers the corresponding multivibrator
when there is a high level on the B1 or B2 input.
GND (Pins 1 and 15)
External ground. The external timing capacitors discharge
to ground through these pins.
B1, B2 (Pins 5, 11)
Negative–edge trigger inputs. A falling–edge signal on
either of these pins triggers the corresponding multivibrator
when there is a low level on the A1 or A2 input.
OUTPUTS
Q1, Q2 (Pins 6, 10)
Reset 1, Reset 2 (Pins 3, 13)
Noninverted monostable outputs. These pins (normally
low) pulse high when the multivibrator is triggered at either
the A or the B input. The width of the pulse is determined by
Reset inputs (active low). When a low level is applied to
one of these pins, the Q output of the corresponding
multivibrator is reset to a low level and the Q output is set to
a high level.
the external timing components, R and C .
X
X
Q1, Q2 (Pins 7, 9)
CX1/RX1 and CX2/RX2 (Pins 2 and 14)
Inverted monostable outputs. These pins (normally high)
pulse low when the multivibrator is triggered at either the A
or the B input. These outputs are the inverse of Q1 and Q2.
External timing components. These pins are tied to the
common points of the external timing resistors and
RxCx
UPPER
REFERENCE
CIRCUIT
OUTPUT
LATCH
–
+
V
CC
V ,
re
UPPER
LOWER
REFERENCE
CIRCUIT
M1
V
CC
2 kΩ
–
+
M2
Q
Q
V ,
re
LOWER
M3
TRIGGER
CONTROL CIRCUIT
A
B
C
Q
TRIGGER CONTROL
RESET CIRCUIT
CB
R
RESET
POWER
ON
RESET
RESET LATCH
Figure 11. Logic Detail (1/2 the Device)
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9
MC74HC4538A
CIRCUIT OPERATION
TRIGGER OPERATION
Figure 12 shows the HC4538A configured in the
retriggerable mode. Briefly, the device operates as follows
(refer to Figure 10): In the quiescent state, the external
The HC4538A is triggered by either a rising–edge signal
at input A (#7) or a falling–edge signal at input B (#8), with
the unused trigger input and the Reset input held at the
voltage levels shown in the Function Table. Either trigger
signal will cause the output of the trigger–control circuit to
go high (#9).
The trigger–control circuit going high simultaneously
initiates two events. First, the output latch goes low, thus
taking the Q output of the HC4538A to a high state (#10).
Second, transistor M3 is turned on, which allows the
timing capacitor, C , is charged to V . When a trigger
x
CC
occurs, the Q output goes high and C discharges quickly to
x
the lower reference voltage (V Lower [ 1/3 V ). C
ref
CC
x
then charges, through R , back up to the upper reference
x
voltage (V Upper [ 2/3 V ), at which point the
ref
CC
one–shot has timed out and the Q output goes low.
The following, more detailed description of the circuit
operation refers to both the logic detail (Figure 9) and the
timing diagram (Figure 10).
external timing capacitor, C , to rapidly discharge toward
x
ground (#11). (Note that the voltage across C appears at the
input of both the upper and lower reference circuit
comparator).
x
QUIESCENT STATE
In the quiescent state, before an input trigger appears, the
output latch is high and the reset latch is high (#1 in
Figure 10). Thus the Q output (pin 6 or 10) of the monostable
multivibrator is low (#2, Figure 10).
The output of the trigger–control circuit is low (#3), and
transistors M1, M2, and M3 are turned off. The external
When C discharges to the reference voltage of the lower
x
reference circuit (#12), the outputs of both reference circuits
will be high (#13). The trigger–control reset circuit goes high,
resetting the trigger–control circuit flip–flop to a low state
(#14). This turns transistor M3 off again, allowing C to begin
x
timing capacitor, C , is charged to V (#4), and both the
to charge back up toward V , with a time constant t = R C
x
CC
CC x x
upper and lower reference circuit has a low output (#5).
In addition, the output of the trigger–control reset circuit
is low.
(#15). Once the voltage across C charges to above the lower
reference voltage, the lower reference circuit will go low
allowing the monostable multivibrator to be retriggered.
x
QUIESCENT
STATE
TRIGGER CYCLE
(A INPUT)
TRIGGER CYCLE
(B INPUT)
RESET
RETRIGGER
t
rr
7
TRIGGER INPUT A
(PIN 4 OR 12)
TRIGGER INPUT B
(PIN 5 OR 11)
8
24
9
TRIGGER-CONTROL
CIRCUIT OUTPUT
3
14
11
4
21
23
15
17
18
R /C INPUT
X
X
12
(PIN 2 OR 14)
V
ref
UPPER
25
13
V
ref
LOWER
5
UPPER REFERENCE
CIRCUIT
13
6
16
LOWER REFERENCE
CIRCUIT
RESET INPUT
(PIN 3 OR 13)
20
1
RESET LATCH
22
10
2
19
Q OUTPUT
(PIN 6 OR 10)
τ
τ
τ + t
rr
Figure 12. Timing Diagram
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10
MC74HC4538A
When C charges up to the reference voltage of the upper
reference circuit (#17), the output of the upper reference
occurs, the output of the reset latch goes low (#22), turning
on transistor M1. Thus C is allowed to quickly charge up to
x
x
circuit goes low (#18). This causes the output latch to toggle,
taking the Q output of the HC4538A to a low state (#19), and
completing the time–out cycle.
V
(#23) to await the next trigger signal.
On power up of the HC4538A the power–on reset circuit
CC
will be high causing a reset condition. This will prevent the
trigger–control circuit from accepting a trigger input during
this state. The HC4538A’s Q outputs are low and the Q not
outputs are high.
POWER–DOWN CONSIDERATIONS
Large values of C may cause problems when powering
x
down the HC4538A because of the amount of energy stored
in the capacitor. When a system containing this device is
RETRIGGER OPERATION
powered down, the capacitor may discharge from V
through the input protection diodes at pin 2 or pin 14.
Current through the protection diodes must be limited to 30
When used in the retriggerable mode (Figure 12), the
HC4538A may be retriggered during timing out of the
output pulse at any time after the trigger–control circuit
CC
mA; therefore, the turn–off time of the V power supply
flip–flop has been reset (#24), and the voltage across C is
CC
x
must not be faster than t = V ꢀ C /(30 mA). For example,
above the lower reference voltage. As long as the C voltage
CC
x
x
if V = 5.0 V and C = 15 µF, the V supply must turn off
is below the lower reference voltage, the reset of the
flip–flop is high, disabling any trigger pulse. This prevents
M3 from turning on during this period resulting in an output
pulse width that is predictable.
CC
x
CC
no faster than t = (5.0 V)ꢀ (15 µF)/30 mA = 2.5 ms. This is
usually not a problem because power supplies are heavily
filtered and cannot discharge at this rate.
When a more rapid decrease of V to zero volts occurs,
The amount of undershoot voltage on R C during the
CC
x x
the HC4538A may sustain damage. To avoid this possibility,
trigger mode is a function of loop delay, M3 conductivity,
and V . Minimum retrigger time, trr (Figure 7), is a
use an external damping diode, D , connected as shown in
x
DD
Figure 11. Best results can be achieved if diode D is chosen
function of 1) time to discharge R C from V
to lower
x
x
x
DD
to be a germanium or Schottky type diode able to withstand
large current surges.
reference voltage (T
); 2) loop delay (T
); 3)
delay
discharge
time to charge R C from the undershoot voltage back to the
x
x
lower reference voltage (T ).
charge
RESET AND POWER ON RESET OPERATION
Figure 13 shows the device configured in the
non–retriggerable mode.
For additional information, please see Application Note
(AN1558/D) titled Characterization of Retrigger Time in
the HC4538A Dual Precision Monostable Multivibrator.
A low voltage applied to the Reset pin always forces the
Q output of the HC4538A to a low state.
The timing diagram illustrates the case in which reset
occurs (#20) while C is charging up toward the reference
x
voltage of the upper reference circuit (#21). When a reset
D
R
X
X
C
V
CC
X
Q
Q
A
B
RESET
Figure 13. Discharge Protection During Power Down
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11
MC74HC4538A
TYPICAL APPLICATIONS
C
R
X
X
C
R
X
X
RISING–EDGE
TRIGGER
RISING–EDGE
TRIGGER
V
CC
V
CC
Q
Q
Q
A
A
B
Q
B
B = V
CC
RESET = V
CC
RESET = V
CC
C
R
C
R
X
X
X
X
FALLING–EDGE
TRIGGER
V
V
CC
CC
A = GND
B
Q
Q
Q
A
B
Q
FALLING–EDGE
TRIGGER
RESET = V
RESET = V
CC
CC
Figure 14. Retriggerable Monostable Circuitry
Figure 15. Non–retriggerable Monostable Circuitry
GND
N/C
A = GND
R C
X
X
Q
N/C
N/C
V
CC
B
Q
RESET
Figure 16. Connection of Unused Section
ONE–SHOT SELECTION GUIDE
100 ns 1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1 s 10 s
MC14528B
MC14536B
MC14538B
MC14541B
HC4538A*
23 HR
5 MIN
*Limited operating voltage (2–6 V)
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
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12
MC74HC4538A
PACKAGE DIMENSIONS
PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
SEATING
PLANE
–T–
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
K
L
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
_
_
_
_
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
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13
MC74HC4538A
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45
K
_
C
G
J
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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14
MC74HC4538A
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T
U
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
S
U
0.15 (0.006) T
K
K1
16
9
2X L/2
J1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
B
–U–
SECTION N–N
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T
U
A
M
MILLIMETERS
INCHES
MIN
–V–
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
C
D
F
4.90
4.30
---
0.193
0.169
---
F
DETAIL E
0.05
0.50
0.002
0.020
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15
MC74HC4538A
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MC74HC4538A/D
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