MC74HC540ADTR2 [ONSEMI]
Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS; 八路三态缓冲器/线路驱动器/线接收器高性能硅栅CMOS
| 型号： | MC74HC540ADTR2 |
| 厂家： | 
ONSEMI |
| 描述： | Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS |
| 文件： | 总8页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC540A
Octal 3−State Inverting
Buffer/Line Driver/Line
Receiver
High−Performance Silicon−Gate CMOS
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MARKING
The MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pull−up
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3−state memory address drivers, clock
drivers, and other bus−oriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
active−low output enables.
DIAGRAMS
20
20
PDIP−20
N SUFFIX
CASE 738
MC74HC540AN
AWLYYWWG
1
1
The HC540A is similar in function to the HC541A, which has
noninverting outputs.
20
Features
SOIC−20
DW SUFFIX
CASE 751D
20
74HC540A
AWLYYWWG
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
1
1
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 124 FETs or 31 Equivalent Gates
• Pb−Free Packages are Available*
20
HC
540A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
20
SOEIAJ−20
F SUFFIX
CASE 967
20
74HC540A
AWLYWWG
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G
G
= Pb−Free Package
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
July, 2005 − Rev. 9
MC74HC540A/D
MC74HC540A
V
OE2 Y1
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
CC
FUNCTION TABLE
Inputs
20
19
18
Output Y
OE1 OE2
A
L
L
L
L
L
H
X
X
H
L
H
X
X
H
Z
Z
1
2
3
4
5
6
7
9
8
10
Z = High Impedance
X = Don’t Care
OE1 A1
A2
A3
A4
A5
A6
A7
A8 GND
Figure 1. Pinout: 20−Lead Packages (Top View)
2
18
17
16
15
14
13
12
11
A1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
3
A2
4
A3
5
A4
Data
Inputs
Inverting
Outputs
6
A5
7
A6
8
A7
9
A8
1
Output
Enables
OE1
OE2
PIN 20 = V
CC
19
PIN 10 = GND
Figure 2. Logic Diagram
ORDERING INFORMATION
†
Device
MC74HC540AN
Package
Shipping
PDIP−20
18 Units / Rail
18 Units / Rail
MC74HC540ANG
PDIP−20
(Pb−Free)
MC74HC540ADW
MC74HC540ADWG
SOIC−20 WIDE
38 Units / Rail
38 Units / Rail
SOIC−20 WIDE
(Pb−Free)
MC74HC540ADWR2
MC74HC540ADWR2G
SOIC−20 WIDE
1000 Tape & Reel
1000 Tape & Reel
SOIC−20 WIDE
(Pb−Free)
MC74HC540ADTR2
MC74HC540ADTR2G
MC74HC540AF
TSSOP−20*
TSSOP−20*
SOEIAJ−20
2500 Tape & Reel
2500 Tape & Reel
40 Units / Rail
MC74HC540AFG
SOEIAJ−20
(Pb−Free)
40 Units / Rail
MC74HC540AFEL
MC74HC540AFELG
SOEIAJ−20
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HC540A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
*0.5 to )7.0
V
DC Input Voltage
*0.5 to V )0.5
V
I
O
CC
V
DC Output Voltage (Note 1)
DC Input Diode Current
*0.5 v V v V )0.5
V
O
CC
I
IK
$20
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
I
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
$35
$35
$75
$75
OK
I
O
I
CC
I
GND
T
*65 to )150
260
STG
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
T
J
)150
q
PDIP
SOIC
67
96
JA
TSSOP
128
P
D
Power Dissipation in Still Air at 85_C
PDIP
SOIC
TSSOP
750
500
450
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% − 35%
UL 94 V0 @ 0.125 in
V
ESD
Human Body Model (Note 2)
Machine Model (Note 3)
u2000
u200
V
Charged Device Model (Note 4)
u1000
I
Latchup Performance
Above V and Below GND at 85_C (Note 5)
$300
mA
LATCHUP
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. I absolute maximum rating must be observed.
O
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
6.0
V , V
in out
DC Input Voltage, Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 3)
V
CC
V
T
A
*55
)125
_C
ns
t , t
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
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3
MC74HC540A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Condition
−55 to
25°C
≤85°C
≤125°C
Unit
V
V
CC
V
IH
Minimum High−Level Input Voltage
V
= 0.1 V
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
out
|I | ≤ 20 mA
out
V
Maximum Low−Level Input Voltage
V
= V − 0.1 V
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
IL
out
CC
|I | ≤ 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
|I | ≤ 20 mA
out
V
in
= V
|I | ≤ 3.6 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IL
out
|I | ≤ 6.0 mA
out
|I | ≤ 7.8 mA
out
V
OL
Maximum Low−Level Output
Voltage
V
= V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
|I | ≤ 20 mA
out
V
= V
|I | ≤ 3.6 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
in
IH
out
|I | ≤ 6.0 mA
out
|I | ≤ 7.8 mA
out
I
Maximum Input Leakage Current
V
= V or GND
6.0
6.0
0.1
0.5
1.0
5.0
1.0
mA
mA
in
CC
I
Maximum Three−State Leakage
Current
Output in High Impedance State
= V or V
10.0
OZ
V
in
IL
IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V or GND
= 0 mA
6.0
4
40
160
mA
CC
in
CC
I
out
7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
Symbol
Parameter
−55 to
25°C
≤85°C
≤125°C
Unit
V
V
CC
t
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 5)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
120
55
28
ns
PLH
t
PHL
20
25
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
3.0
4.5
6.0
110
45
25
140
60
31
165
75
38
ns
ns
ns
PLZ
t
PHZ
21
26
31
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
3.0
4.5
6.0
110
45
25
140
60
31
165
75
38
PZL
t
PZH
21
26
31
t
,
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
TLH
t
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum 3−State Output Capacitance (Output in High Impedance State)
out
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V, V = 0 V
CC
EE
35
C
Power Dissipation Capacitance (Per Buffer) (Note 9)
pF
PD
2
9. Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
. For load considerations, see the ON
D
PD CC
CC CC
Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
MC74HC540A
V
CC
OE1 or OE2
t
f
t
r
50%
50%
V
GND
CC
90%
50%
10%
t
t
PLZ
PZL
INPUT A
HIGH
IMPEDANCE
OUTPUT Y
GND
50%
50%
t
t
PLH
PHL
10%
90%
V
OL
90%
50%
10%
t
t
PHZ
PZH
OUTPUT Y
V
OH
OUTPUT Y
HIGH
t
t
TLH
THL
IMPEDANCE
Figure 3. Switching Waveform
Figure 4. Switching Waveform
TEST POINT
OUTPUT
TEST POINT
CONNECT TO V WHEN
CC
1kW
OUTPUT
TESTING t
AND t
.
PLZ
PZL
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t and t
DEVICE
UNDER
TEST
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
To 7 Other Inverters
V
CC
One of Eight
Inverters
INPUT A
OUTPUT Y
OE1
OE2
Figure 7. Logic Detail
PIN DESCRIPTIONS
INPUTS
device functions as an inverter. When a high voltage is
applied to either input, the outputs assume the high
impedance state.
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
Data input pins. Data on these pins appear in inverted form
on the corresponding Y outputs, when the outputs are
enabled.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
CONTROLS
Device outputs. Depending upon the state of the output
enable pins, these outputs are either inverting outputs or
high−impedance outputs.
OE1, OE2 (PINS 1, 19)
Output enables (active−low). When a low voltage is
applied to both of these pins, the outputs are enabled and the
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5
MC74HC540A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
L
C
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
0.050 BSC
1.27 BSC
−T−
SEATING
PLANE
K
0.050
0.100 BSC
0.070
1.27
2.54 BSC
1.77
F
G
J
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.01
J 20 PL
_
D 20 PL
M
M
T B
0.25 (0.010)
M
M
T A
0.25 (0.010)
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
B
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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6
MC74HC540A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING
20X K REF
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
0.25 (0.010)
N
S
0.15 (0.006) T U
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
A
−V−
N
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
−−−
6.60 0.252
4.50 0.169
DETAIL E
C
1.20
−−−
D
0.05
0.50
0.15 0.002
0.75 0.020
−W−
F
C
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
G
D
J1
K
H
DETAIL E
0.100 (0.004)
−T− SEATING
K1
L
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
PLANE
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7
MC74HC540A
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
E
20
11
Q
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
1
H
E
_
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
2.05
0.20
0.50
0.27
12.80
5.45
MAX
0.081
0.008
0.020
0.011
0.504
0.215
A
A
1
−−−
0.05
0.35
0.18
12.35
5.10
−−−
0.002
0.014
0.007
0.486
0.201
A
b
1
b
c
M
0.10 (0.004)
0.13 (0.005)
D
E
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0
10
_
0.035
0.032
_
_
_
0.70
−−−
0.90
0.81
0.028
−−−
1
Z
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2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC74HC540A/D
相关型号：
MC74HC540ADTR2G
Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC540ADWG
Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC540ADWR2G
Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC540AF
Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC540AFEL
Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC540AFELG
Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC540AFG
Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS
ONSEMI
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