MC74HC595AFELG [ONSEMI]
8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High−Performance Silicon−Gate CMOS; 8位串行输入/串行或并行输出移位锁存具有三态输出的高性能硅栅CMOS注册
| 型号： | MC74HC595AFELG |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High−Performance Silicon−Gate CMOS |
| 文件： | 总12页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC595A
8−Bit Serial−Input/Serial or
Parallel−Output Shift
Register with Latched
3−State Outputs
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MARKING
High−Performance Silicon−Gate CMOS
The MC74HC595A consists of an 8−bit shift register and an 8−bit
D−type latch with three−state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8−bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
MC74HC595AN
AWLYYWW
16
1
1
The HC595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
16
Features
SOIC−16
D SUFFIX
CASE 751B
HC595A
AWLYWW
16
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
1
1
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
16
TSSOP−16
DT SUFFIX
CASE 948F
HC
595A
ALYW
16
1
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
1
−
−
−
Improved Propagation Delays
50% Lower Quiescent Power
Improved Input Noise and Latchup Immunity
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
• Pb−Free Packages are Available*
W, WW = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
April, 2005 − Rev. 9
MC74HC595A/D
MC74HC595A
LOGIC DIAGRAM
SERIAL
14
15
1
DATA
INPUT
A
Q
Q
A
B
PIN ASSIGNMENT
2
3
4
5
6
7
Q
Q
Q
Q
Q
Q
C
D
E
Q
Q
1
2
3
4
5
6
7
8
16
15
14
V
CC
B
PARALLEL
DATA
OUTPUTS
Q
A
C
D
A
SHIFT
REGISTER
LATCH
Q
F
Q
13 OUTPUT ENABLE
12 LATCH CLOCK
11 SHIFT CLOCK
10 RESET
E
G
H
Q
Q
F
SHIFT
11
10
12
13
G
CLOCK
Q
H
SERIAL
DATA
OUTPUT
9
RESET
SQ
H
GND
9
SQ
H
LATCH
CLOCK
V
= PIN 16
CC
GND = PIN 8
OUTPUT
ENABLE
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC595AN
PDIP−16
500 Units / Rail
500 Units / Rail
MC74HC595ANG
PDIP−16
(Pb−Free)
MC74HC595AD
SOIC−16
48 Units / Rail
48 Units / Rail
MC74HC595ADG
SOIC−16
(Pb−Free)
MC74HC595ADR2
MC74HC595ADR2G
SOIC−16
2500 Tape & Reel
2500 Tape & Reel
SOIC−16
(Pb−Free)
MC74HC595ADT
MC74HC595ADTR2
MC74HC595AFEL
MC74HC595AFELG
TSSOP−16*
TSSOP−16*
SOEIAJ−16
96 Units / Rail
2500 Tape & Reel
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HC595A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
± 20
± 35
± 75
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
DC Supply Current, V and GND Pins
range GND v (V or V ) v V
.
CC
CC
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
L
260
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V , V
in out
DC Input Voltage, Output Voltage
(Referenced to GND)
0
V
CC
V
T
Operating Temperature, All Package Types
– 55
+ 125
_C
ns
A
t , t
r
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
– 55 to 25_C
v 85_C v 125_C
Symbol
Parameter
Test Conditions
= 0.1 V or V – 0.1 V
|I | v 20 mA
Unit
V
IH
Minimum High−Level Input
Voltage
V
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
1.5
2.1
V
out
CC
out
3.15
4.2
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V – 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage, Q − Q
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IH
|I | v 20 mA
out
A
H
V
in
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
IH
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
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3
MC74HC595A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
– 55 to 25_C
v 85_C
0.1
0.1
0.1
v 125_C
V
Symbol
Parameter
Test Conditions
= V or V
|I | v 20 mA
out
Unit
V
OL
Maximum Low−Level Output
Voltage, Q − Q
V
in
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
V
IH
IL
A
H
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
IH
IL
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
V
Minimum High−Level Output
V
in
= V or V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
OH
IH
Voltage, SQ
II I v 20 mA
out
H
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
2.98
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
in
IH
IL
out
II
out
I
4.0 mA
v
II Iv 5.2 mA
out
V
Maximum Low−Level Output
V
in
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
IH
IL
Voltage, SQ
II I v 20 mA
out
H
V
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
IH
IL
out
II
out
I
4.0 mA
v
II Iv 5.2 mA
out
I
Maximum Input Leakage
Current
= V or GND
6.0
± 0.1
± 1.0
± 1.0
mA
mA
in
in
CC
I
Maximum Three−State
Leakage
Output in High−Impedance State
= V or V
6.0
± 0.5
± 5.0
± 10
OZ
V
in
IL
IH
Current, Q − Q
V
= V or GND
A
H
out CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V or GND
= 0 mA
6.0
4.0
40
160
mA
CC
in
CC
l
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
V
CC
V
– 55 to 25_C
v 85_C v 125_C
Symbol
Parameter
Unit
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
MHz
max
24
t
t
,
Maximum Propagation Delay, Shift Clock to SQ
(Figures 1 and 7)
2.0
3.0
4.5
6.0
140
100
28
175
125
35
210
150
42
ns
ns
ns
ns
ns
PLH
H
PHL
24
30
36
t
Maximum Propagation Delay, Reset to SQ
(Figures 2 and 7)
2.0
3.0
4.5
6.0
145
100
29
180
125
36
220
150
44
PHL
H
25
31
38
t
t
t
,
Maximum Propagation Delay, Latch Clock to Q − Q
2.0
3.0
4.5
6.0
140
100
28
175
125
35
210
150
42
PLH
t
A
H
(Figures 3 and 7)
PHL
24
30
36
,
Maximum Propagation Delay, Output Enable to Q − Q
(Figures 4 and 8)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PLZ
A
H
t
PHZ
26
33
38
,
Maximum Propagation Delay, Output Enable to Q − Q
(Figures 4 and 8)
2.0
3.0
4.5
6.0
135
90
27
170
110
34
205
130
41
PZL
A
H
t
PZH
23
29
35
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4
MC74HC595A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
V
CC
– 55 to 25_C
v 85_C
v 125_C
V
Symbol
Parameter
Unit
t
,
Maximum Output Transition Time, Q − Q
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
31
18
15
ns
TLH
A
H
t
(Figures 3 and 7)
THL
t
t
,
Maximum Output Transition Time, SQ
(Figures 1 and 7)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
ns
TLH
H
THL
19
C
Maximum Input Capacitance
—
—
10
15
10
15
10
15
pF
pF
in
C
Maximum Three−State Output Capacitance (Output in
High−Impedance State), Q − Q
out
A
H
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
300
C
Power Dissipation Capacitance (Per Package)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I V . For load considerations, see Chapter 2 of the
CC CC
D
PD CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input t = t = 6.0 ns)
r
f
Guaranteed Limit
V
CC
25_C to –55_C v 85_C v 125_C
V
Symbol
Parameter
Unit
t
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
su
su
t
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
75
60
15
13
95
70
19
16
110
80
22
ns
ns
ns
ns
ns
ns
ns
19
t
h
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
t
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
rec
t
w
t
w
t
w
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
60
45
12
10
75
60
15
13
90
70
18
15
Minimum Pulse Width, Shift Clock
(Figure 1)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
t , t
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
r
f
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5
MC74HC595A
FUNCTION TABLE
Inputs
Resulting Function
Serial
Input
A
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
Parallel
Outputs
Shift
Clock
Latch
Clock
Output
Enable
SQ
Q
− Q
Reset
Operation
H
A
H
Reset shift register
L
X
D
X
L, H, ↓
L, H, ↓
L
L
L
U
U
L
U
Shift data into shift
register
H
↑
D → SR ;
SR → SR
SR → SR
U
A
G
H
N
N+1
Shift register remains
unchanged
H
H
X
X
L, H, ↓
L, H, ↓
L, H, ↓
L
L
U
U
U
U
U
U
Transfer shift register
contents to latch
register
↑
SR → LR
SR
N
N
N
Latch register remains
unchanged
X
X
X
L, H, ↓
L
*
U
*
U
Enable parallel outputs
X
X
X
X
X
X
X
X
L
*
*
**
**
*
*
Enabled
Z
Force outputs into high
impedance state
H
SR = shift register contents
LR = latch register contents
D = data (L, H) logic level
U = remains unchanged
↑ = Low−to−High
↓ = High−to−Low
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
Output Enable (Pin 13)
A (Pin 14)
Active−low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
Serial Data Input. The data on this pin is shifted into the
8−bit serial shift register.
on this input forces the outputs (Q −Q ) into the
A
H
high−impedance state. The serial output is not affected by
this control unit.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low− to−high transition on
this input causes the data at the Serial Input pin to be shifted
into the 8−bit shift register.
OUTPUTS
QA − QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3−state, latch outputs.
Reset (Pin 10)
SQH (Pin 9)
Active−low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8−bit latch is not affected.
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8−bit shift register. This output does not
have three−state capability.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low−to−high transition on
this input latches the shift register data.
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6
MC74HC595A
SWITCHING WAVEFORMS
t
w
t
r
t
f
V
CC
V
CC
SHIFT
90%
50%
10%
50%
RESET
CLOCK
GND
GND
t
t
PHL
w
1/f
max
50%
OUTPUT
t
t
PHL
PLH
SQ
H
t
rec
90%
50%
10%
OUTPUT
V
CC
SHIFT
SQ
H
50%
CLOCK
GND
t
t
TLH
THL
Figure 1.
Figure 2.
V
CC
OUTPUT
ENABLE
V
50%
CC
LATCH
CLOCK
50%
GND
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
50%
t
t
PHL
PLH
OUTPUT Q
OUTPUT Q
10%
90%
V
V
OL
t
t
PHZ
90%
50%
10%
PZH
Q −Q
A
H
OUTPUTS
OH
50%
HIGH
t
t
THL
TLH
IMPEDANCE
Figure 3.
Figure 4.
V
CC
SHIFT
50%
VALID
CLOCK
V
CC
GND
SERIAL
50%
t
su
INPUT A
GND
V
CC
LATCH
CLOCK
t
su
t
h
50%
V
CC
SWITCH
CLOCK
GND
50%
t
w
GND
Figure 5.
Figure 6.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
CONNECT TO V WHEN
CC
1 kW
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7.
Figure 8.
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7
MC74HC595A
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE
13
12
14
LATCH
CLOCK
SERIAL
DATA
INPUT A
15
D
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
A
SR
SR
SR
SR
SR
LR
LR
A
B
C
D
E
A
B
C
D
R
D
1
B
R
D
2
C
D
E
F
LR
LR
R
D
3
PARALLEL
DATA
OUTPUTS
R
D
4
LR
LR
E
R
D
5
SR
F
F
R
D
6
G
SR
G
LR
G
R
D
7
H
SHIFT
11
10
SR
H
LR
H
CLOCK
R
SERIAL
DATA
OUTPUT SQ
9
RESET
H
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8
MC74HC595A
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
Q
A
B
C
D
Q
Q
Q
Q
E
Q
F
Q
G
Q
H
SERIAL DATA
OUTPUT SQ
H
NOTE:
implies that the output is in a high−impedance
state.
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9
MC74HC595A
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T
A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
−A
−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
−B
−
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
B
0.25 (0.010)
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
MIN MAX
9.80 10.00
INCHES
MIN MAX
DIM
A
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
B
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
D
C
F
1.27 BSC
G
J
−T
0.19
0.10
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEATING
PLANE
−
M
K
Dꢀ16ꢀPL
M
P
0°
0°
0.229 0.244
7°
5.80
0.25
6.20
0.50
M
S
S
A
0.25 (0.010)
T
B
R
0.010 0.019
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10
MC74HC595A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16X KREF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
D
F
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
−T−
D
PLANE
G
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11
MC74HC595A
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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