MC74HCT244A_06 [ONSEMI]
Octal 3−State Noninverting Buffer/Line Driver/Line Receiver with LSTTL−Compatible Inputs; 八路三态同相缓冲器/线路驱动器/线接收器与LSTTL兼容输入
| 型号： | MC74HCT244A_06 |
| 厂家： | 
ONSEMI |
| 描述： | Octal 3−State Noninverting Buffer/Line Driver/Line Receiver with LSTTL−Compatible Inputs |
| 文件： | 总8页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT244A
Octal 3−State Noninverting
Buffer/Line Driver/
Line Receiver with
LSTTL−Compatible Inputs
http://onsemi.com
High−Performance Silicon−Gate CMOS
The MC74HCT244A is identical in pinout to the LS244. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High−Speed CMOS inputs. The HCT244A is an octal
noninverting buffer line driver line receiver designed to be used with
3−state memory address drivers, clock drivers, and other bus−oriented
systems. The device has non−inverted outputs and two active−low
output enables.
PDIP−20
N SUFFIX
CASE 738
1
SOIC−20W
DW SUFFIX
CASE 751D
The HCT244A is the non−inverting version of the HCT240. See
also HCT241.
1
Features
TSSOP−20
DT SUFFIX
CASE 948E
• Output Drive Capability: 15 LSTTL Loads
• TTL NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1 mA
1
SOEIAJ−20
M SUFFIX
CASE 967
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
1
• Chip Complexity: 112 FETs or 28 Equivalent Gates
• Pb−Free Packages are Available
PIN ASSIGNMENT
ENABLE A
1
20
V
CC
A1
YB4
A2
2
3
4
19
18
17
ENABLE B
YA1
2
4
6
18
16
14
A1
A2
A3
YA1
YA2
YA3
B4
YB3
A3
5
6
7
8
9
16
15
14
13
12
YA2
B3
YB2
A4
YA3
B2
8
12
9
A4
B1
YA4
YB1
NONINVERTING
OUTPUTS
DATA INPUTS
YB1
YA4
11
GND 10
11 B1
13
15
17
7
5
3
B2
B3
B4
YB2
YB3
YB4
FUNCTION TABLE
Inputs
Enable A,
Enable B A, B
Outputs
YA, YB
L
L
H
L
H
X
L
H
Z
1
PIN 20 = V
CC
PIN 10 = GND
ENABLE A
ENABLE B
OUTPUT
ENABLES
19
Z = high impedance, X = don’t care
ORDERING AND MARKING INFORMATION
See detailed ordering, shipping, and marking information in
the package dimensions section on page 5 of this data sheet.
Figure 1. Logic Diagram
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 11
MC74HCT244A/D
MC74HCT244A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7
V
CC
V
– 0.5 to V + 0.5
V
in
CC
V
– 0.5 to V + 0.5
V
out
CC
I
20
35
75
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
DC Supply Current, V and GND Pins
range GND v (V or V ) v V
.
CC
CC
CC
in
out
Unused inputs must always be
tied to an appropriate logic voltage
P
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
750
500
450
D
level (e.g., either GND or V ).
CC
TSSOP Package†
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
L
260
†Derating − Plastic DIP: – 10 mW/_C from 65_ to 125_C
−
−
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
5.5
CC
V , V
in out
V
V
CC
T
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
– 55
0
+ 125
500
_C
ns
A
t , t
r
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
2
2
V
v 85_C v 125_C
Symbol
Parameter
Test Conditions
= 0.1 V or V – 0.1 V
|I | v 20 mA
Unit
V
Minimum High−Level Input Voltage
V
out
4.5
5.5
2
2
2
2
V
IH
out
CC
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V – 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
CC
|I | v 20 mA
out
V
Minimum High−Level Output
Voltage
V
in
= V or V
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
OH
IH
IL
|I | v 20 mA
out
V
= V or V
in
IH
IL
|I | v 6 mA
out
4.5
3.98
3.84
3.7
V
Maximum Low−Level Output
Voltage
V
= V or V
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
in
IH
IL
|I | v 20 mA
out
V
= V or V
in
IH IL
|I | v 6 mA
4.5
5.5
5.5
0.26
0.1
0.33
1.0
0.4
out
I
Maximum Input Leakage Current
V
in
= V or GND
1.0
mA
mA
in
CC
I
Maximum Three−State Leakage
Current
Output in High−Impedance State
0.5
5.0
10
OZ
V
in
= V or V
V
= V or GND
IL
IH; out CC
I
Maximum Quiescent Supply
Current (per Package)
V
in
= V or GND I = 0 mA
5.5
4
40
160
mA
CC
CC
out
DI
Additional Quiescent Supply
Current
V
V
l
= 2.4 V, Any One Input
≥ −55_C
2.9
25_C to 125_C
CC
in
in
= V or GND, Other Inputs
CC
= 0 mA
2.4
out
5.5
mA
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Total Supply Current = I + ΣDI
.
CC
CC
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2
MC74HCT244A
AC ELECTRICAL CHARACTERISTICS (V = 5.0 V 10%, C = 50 pF, Input t = t = 6 ns)
CC
L
r
f
Guaranteed Limit
– 55 to 25_C
v 85_C
v 125_C
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)
20
25
30
ns
PLH
t
PHL
,
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
26
22
12
33
28
15
39
33
18
ns
ns
ns
PLZ
t
PHZ
,
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
PZL
t
PZH
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
TLH
t
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
out
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
55
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
pF
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I V . For load considerations, see Chapter 2 of the
CC CC
D
PD CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
t
r
t
f
3 V
INPUT
A OR B
2.7 V
1.3 V
0.3 V
GND
t
t
PHL
PLH
90%
1.3 V
10%
OUTPUT
YA OR YB
t
t
THL
TLH
Figure 2.
3 V
ENABLE
1.3 V
GND
A OR B
t
t
PLZ
PZL
HIGH
IMPEDANCE
1.3 V
OUTPUT Y
OUTPUT Y
10%
90%
V
V
OL
t
t
PHZ
PZH
OH
1.3 V
HIGH
IMPEDANCE
Figure 3.
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3
MC74HCT244A
TEST CIRCUITS
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 4.
TEST POINT
CONNECT TO V WHEN
CC
1 kW
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
*Includes all probe and jig capacitance
Figure 5.
LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS
ONE OF 8
BUFFERS
V
CC
DATA INPUT
A OR B
YA
OR
YB
ENABLE A OR ENABLE B
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4
MC74HCT244A
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT244AN
MC74HCT244ANG
PDIP−20
18 Units / Rail
38 Units / Rail
PDIP−20
(Pb−Free)
MC74HCT244ADW
MC74HCT244ADWG
SOIC−20
SOIC−20
(Pb−Free)
MC74HCT244ADWR2
MC74HCT244ADWR2G
SOIC−20
1000 / Tape & Reel
2500 / Tape & Reel
40 Units / Rail
SOIC−20
(Pb−Free)
MC74HCT244ADTR2
MC74HCT244ADTR2G
MC74HCT244AF
TSSOP−20*
TSSOP−20*
SOEIAJ−20
MC74HCT244AFG
SOEIAJ−20
(Pb−Free)
MC74HCT244AFEL
MC74HCT244AFELG
SOEIAJ−20
2000 / Tape & Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*These packages are inherently Pb−Free.
MARKING DIAGRAMS
PDIP−20
SOIC−20W
TSSOP−20
SOEIAJ−20
20
20
1
20
1
20
1
HCT
244A
ALYWG
G
HCT244A
AWLYYWWG
74HCT244A
AWLYWWG
MC74HCT244AN
AWLYYWWG
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
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5
MC74HCT244A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
MILLIMETERS
L
C
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
1.070
0.260
0.180
0.022
0.050 BSC
1.27 BSC
−T−
SEATING
PLANE
K
0.050
0.070
1.27
1.77
G
J
0.100 BSC
2.54 BSC
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
J 20 PL
_
_
_
D 20 PL
M
M
B
0.25 (0.010)
T
M
M
A
0.25 (0.010)
T
SOIC−20W
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
MILLIMETERS
1
10
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
B
20X B
M
S
S
B
0.25
T A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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6
MC74HCT244A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
20X K REF
K
M
S
S
V
0.10 (0.004)
T
U
S
U
K1
0.15 (0.006) T
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T
U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MC74HCT244A
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
20
11
E
Q
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
1
H
E
E
_
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.25
12.80
5.45
A
−−−
0.05
A
1
A
b
1
0.002
0.008
0.020
0.010
0.504
0.215
b
c
0.35
0.15
0.014
0.006
0.486
0.201
M
0.10 (0.004)
0.13 (0.005)
D
E
e
12.35
5.10
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
10
0.035
0
0.028
_
_
_
_
0.70
−−−
0.90
0.81
1
Z
−−− 0.032
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74HCT244A/D
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