MC74HCT273 [ONSEMI]
Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs; 八路D触发器与普通时钟和LSTTL兼容输入复位
| 型号： | MC74HCT273 |
| 厂家： | 
ONSEMI |
| 描述： | Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs |
| 文件： | 总8页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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High–Performance Silicon–Gate CMOS
MARKING
DIAGRAMS
20
The MC74HCT273A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT273A is identical in pinout to the LS273.
This device consists of eight D flip–flops with common Clock and
Reset inputs. Each flip–flop is loaded with a low–to–high transition of
the Clock input. Reset is asynchronous and active low.
PDIP–20
N SUFFIX
CASE 738
MC74HCT273AN
AWLYYWW
20
1
1
20
• Output Drive Capability: 10 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT273A
AWLYYWW
20
1
1
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 284 FETs or 71 Equivalent Gates
PIN ASSIGNMENT
LOGIC DIAGRAM
2
RESET
Q0
1
2
3
4
5
6
7
8
9
20
V
CC
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
5
6
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CLOCK
4
D0
7
D1
8
9
DATA
INPUTS
NONINVERTING
OUTPUTS
13
14
17
18
Q1
12
15
16
19
Q2
D2
D3
Q3
11
CLOCK
GND 10
PIN 20 = V
CC
PIN 10 = GND
1
RESET
FUNCTION TABLE
ORDERING INFORMATION
Inputs
Reset Clock
Output
Device
Package
PDIP–20
Shipping
D
Q
MC74HCT273AN
1440 / Box
38 / Rail
L
X
X
H
L
X
X
L
H
L
MC74HCT273ADW
SOIC–WIDE
H
H
H
H
MC74HCT273ADWR2 SOIC–WIDE 1000 / Reel
L
No Change
No Change
X = Don’t Care
Z = High Impedance
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 8
MC74HCT273A/D
MC74HCT273A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or Plastic DIP)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
500
C
t , t
r f
0
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
IH
out
CC
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
in
IL
IL
IL
IL
|I
|
20 µA
out
V
= V or V
IH
in
|I
|
4.0 mA
4.5
3.98
3.84
3.7
out
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
in
|I
|
20 µA
out
V
= V or V
in
IH
|I
|
4.0 mA
4.5
5.5
0.26
0.33
0.4
out
I
in
Maximum Input Leakage
Current
V
in
= V
or GND
or GND
± 0.1
± 1.0
± 1.0
µA
µA
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V
= 0 µA
5.5
4.0
40
160
CC
in
CC
I
out
∆I
CC
Additional Quiescent Supply
Current
V
V
l
= 2.4 V, Any One Input
≥ –55 C
25 C to 125 C
in
in
out
= V
or GND, Other Inputs
CC
= 0 µA
5.5
2.9
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
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2
MC74HCT273A
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
25 C
30
Symbol
Parameter
Maximum Clock Frequency (50% Duty Cycle)
Maximum Propagation Delay, Clock to Q
Fig.
1, 4
1, 4
Unit
MHz
ns
85 C
24
125 C
20
f
max
t
t
,
25
28
35
PLH
PHL
t
Maximum Propagation Delay, Reset to Q
2, 4
1, 5
25
18
28
20
35
22
ns
ns
PHL
t
,
Maximum Output Transition Time, Any Output
TLH
t
THL
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Gate)*
pF
30
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
TIMING REQUIREMENTS (V
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
CC
L
r
f
Guaranteed Limit
– 55 to 25 C
85 C
Max
125 C
Max
Symbol
Parameter
Fig.
3
Unit
ns
Min
10
Max
Min
12
Min
15
t
su
Minimum Setup Time, Data to Clock
Minimum Hold Time, Clock to Data
t
h
3
3.0
5.0
12
3.0
5.0
15
3.0
5.0
18
ns
t
Minimum Recovery Time, Set or Reset Inactive to Clock
Minimum Pulse Width, Clock
2
ns
rec
t
1
ns
w
w
t
Minimum Pulse Width, Set or Reset
Maximum Input Rise and Fall Times
2
12
15
18
ns
t , t
r f
1
500
500
500
ns
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3
MC74HCT273A
SWITCHING WAVEFORMS
t
w
t
t
r
f
3.0 V
GND
3.0 V
2.7 V
1.3 V
1.3 V
RESET
Q
CLOCK
GND
0.3 V
t
PHL
t
w
1/f
max
1.3 V
t
t
PHL
PLH
t
90%
1.3 V
10%
rec
Q
3.0 V
GND
CLOCK
1.3 V
t
t
THL
TLH
Figure 1.
Figure 2.
TEST POINT
OUTPUT
VALID
3.0 V
GND
3.0 V
GND
DEVICE
UNDER
TEST
DATA
1.3 V
C *
L
t
su
t
h
1.3 V
CLOCK
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
C
2
Q
Q
Q
Q
Q
Q
Q
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
D0
D1
D2
D3
D4
D5
D6
D
R
C
5
4
D
R
C
6
7
D
R
C
9
8
D
R
NONINVERTING
OUTPUTS
DATA
INPUTS
C
12
15
16
19
13
14
17
D
R
C
D
R
C
D
R
C
18
11
1
D7
CLOCK
RESET
D
R
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4
MC74HCT273A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66 27.17
MILLIMETERS
MIN MAX
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
1.27 BSC
1.27
6.60
4.57
0.55
–T–
SEATING
PLANE
K
M
0.070
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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5
MC74HCT273A
Notes
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6
MC74HCT273A
Notes
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7
MC74HCT273A
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MC74HCT273A/D
相关型号：
MC74HCT273ADWR2
D Flip-Flop, HCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, PLASTIC, SOIC-20
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