MC74HCT573ADWR2G [ONSEMI]
Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs; 八路三态同相透明锁存器与LSTTL兼容输入
| 型号： | MC74HCT573ADWR2G |
| 厂家： | 
ONSEMI |
| 描述： | Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs |
| 文件： | 总8页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT573A
Octal 3-State Noninverting
Transparent Latch with
LSTTL Compatible Inputs
High−Performance Silicon−Gate CMOS
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MARKING
The MC74HCT573A is identical in pinout to the LS573. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High−Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold times becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
DIAGRAMS
20
20
PDIP−20
N SUFFIX
CASE 738
MC74HCT573AN
AWLYYWWG
1
1
20
The HCT573A is identical in function to the HCT373A but has the
Data Inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
SOIC−20
DW SUFFIX
CASE 751D
20
HCT573A
AWLYYWWG
1
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 10 mA
1
20
HCT
573A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
• In Compliance with the Requirements Defined by JEDEC Standard
1
No. 7 A
1
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
— Improved Propagation Delays
— 50% Lower Quiescent Power
• These Devices are Pb−Free and are RoHS Compliant
20
SOEIAJ−20
F SUFFIX
CASE 967
20
74HCT573A
AWLYWWG
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
†
Device
MC74HCT573ANG
Package
Shipping
PDIP−20
18 / Rail
MC74HCT573ADWR2G SOIC−20 1000 / Reel
MC74HCT573ADTR2G TSSOP−20 2500 / Reel
MC74HCT573AFELG
SOEIAJ−20 2000 / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 12
MC74HCT573A/D
MC74HCT573A
LOGIC DIAGRAM
PIN ASSIGNMENT
OUTPUT
ENABLE
2
3
4
19
1
2
3
4
5
6
7
8
9
20
V
CC
D0
D1
D2
Q0
Q1
Q2
18
17
D0
D1
D2
D3
D4
D5
D6
D7
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
5
6
16
15
NONINVERTING
DATA
D3
D4
Q3
Q4
OUTPUTS
INPUTS
7
8
9
14
13
12
D5
D6
D7
Q5
Q6
Q7
11
1
LATCH ENABLE
PIN 20 = V
CC
PIN 10 = GND
LATCH
ENABLE
GND 10
11
OUTPUT ENABLE
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable
D
Q
L
L
L
H
H
L
H
L
X
X
H
L
No Change
Z
H
X
X = Don’t Care
Z = High Impedance
Design Criteria
Value
Units
ea
Internal Gate Count*
58.5
1.5
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
ns
5.0
μW
0.0075
pJ
*Equivalent to a two−input NAND gate.
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2
MC74HCT573A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, TSSOP or SOIC Package)
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C
SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/°C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
500
_C
ns
t , t
0
r
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
V
v 85_C
v 125_C
Symbol
Parameter
Test Conditions
= 0.1 V or V – 0.1 V
Unit
V
IH
Minimum High−Level Input
V
out
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
out
CC
Voltage
|I | v 20 μA
V
IL
Maximum Low−Level Input
V
out
= 0.1 V or V – 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
CC
Voltage
|I | v 20 μA
out
V
OH
Minimum High−Level Output
V
in
= V or V
IL
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
IH
Voltage
|I | v 20 μA
out
V
in
= V or V
IH IL
|I | v 6.0 mA
4.5
3.98
3.84
3.7
out
V
OL
Maximum Low−Level Output
V
V
in
= V or V
IL
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
IH
Voltage
|I | v 20 μA
out
V
in
= V or V
IH IL
|I | v 6.0 mA
4.5
5.5
5.5
0.26
0.1
0.33
1.0
0.4
1.0
10
out
I
Maximum Input Leakage Current
V
= V or GND
μA
μA
in
in
CC
I
Maximum Three−State
Leakage Current
Output in High−Impedance State
V = V or V
in
0.5
5.0
OZ
IL
CC
IH
V
out
= V or GND
I
Maximum Quiescent Supply
Current (per Package)
V
I
= V or GND
5.5
5.5
4.0
40
160
μA
CC
in
out
CC
v 0 μA
ΔI
Additional Quiescent Supply
Current
V
V
l
= 2.4 V, Any One Input
CC
in
in
≥ – 55_C
25_C to 125_C
= V or GND, Other Inputs
CC
= 0 μA
2.9
2.4
out
mA
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3
MC74HCT573A
AC ELECTRICAL CHARACTERISTICS (V = 5.0 V 10%, C = 50 pF, Input t = t = 6.0 ns)
CC
L
r
f
Guaranteed Limit
– 55 to
25_C
v 85_C
v 125_C
Symbol
Parameter
Unit
t
,
Maximum Propagation Delay, Input D to Output Q
(Figures 1 and 5)
30
30
28
28
12
38
45
45
42
42
18
ns
PLH
t
PHL
t
t
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
38
35
35
15
ns
ns
ns
ns
PLH
PHL
T
PLZ,
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
T
PHZ
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
TZL,
t
TZH
t
,
Maximum Output Transition Time, any Output
(Figures 1 and 5)
TLH
t
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
out
Typical @ 25°C, V = 5.0 V
CC
48
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
TIMING REQUIREMENTS (V = 5.0 V 10%, C = 50 pF, Input t = t = 6.0 ns)
CC
L
r
f
Guaranteed Limit
– 55 to 25_C
v 85_C
v 125_C
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Fig.
4
Unit
ns
t
su
Minimum Setup Time, Input D to Latch Enable
Minimum Hold Time, Latch Enable to Input D
Minimum Pulse Width, Latch Enable
10
13
5.0
19
15
5.0
22
t
h
4
5.0
15
ns
t
w
2
ns
t , t
Maximum Input Rise and Fall Times
1
500
500
500
ns
r
f
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4
MC74HCT573A
SWITCHING WAVEFORMS
3.0 V
GND
LATCH
t
r
t
f
1.3 V
ENABLE
3.0 V
2.7 V
1.3 V
0.3 V
INPUT D
t
w
GND
t
t
PHL
PLH
90%
1.3 V
10%
t
t
PHL
PLH
Q
1.3 V
t
t
THL
TLH
Q
Figure 1.
Figure 2.
OUTPUT
ENABLE
3.0 V
GND
VALID
1.3 V
3.0 V
GND
1.3 V
t
INPUT D
t
t
PLZ
PZL
HIGH
IMPEDANCE
Q
1.3 V
t
h
SU
3.0 V
GND
10%
90%
V
V
OL
t
t
1.3 V
PZH
PHZ
LATCH
OH
ENABLE
Q
1.3 V
HIGH
IMPEDANCE
Figure 3.
Figure 4.
EXPANDED LOGIC DIAGRAM
TEST POINT
OUTPUT
2
D0
D
19
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
DEVICE
UNDER
TEST
3
D1
D
C *
L
18
17
16
15
14
13
12
Q
LE
4
D2
D
Q
LE
*Includes all probe and jig capacitance
5
D3
D
Q
LE
Figure 5. Test Circuit
6
D4
D
Q
LE
7
D5
D
TEST POINT
Q
LE
CONNECT TO V WHEN
CC
8
1 kΩ
OUTPUT
D6
D
TESTING t AND t
PLZ
.
PZL
Q
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
LE
.
PZH
PHZ
9
C *
L
D7
D
Q
LE
11
LATCH ENABLE
*Includes all probe and jig capacitance
1
OUTPUT ENABLE
Figure 6. Test Circuit
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5
MC74HCT573A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
L
C
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
0.050 BSC
1.27 BSC
−T−
SEATING
PLANE
K
0.050
0.100 BSC
0.070
1.27
2.54 BSC
1.77
F
G
J
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.01
J 20 PL
_
D 20 PL
M
M
B
0.25 (0.010)
T
M
M
A
0.25 (0.010)
T
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
B
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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6
MC74HCT573A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
K
K1
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T
U
S
T U
0.15 (0.006)
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006)
T U
N
A
−V−
MILLIMETERS
INCHES
MIN
F
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
−W−
C
F
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
G
D
J
H
J1
K
DETAIL E
0.100 (0.004)
−T− SEATING
K1
L
6.40 BSC
0.252 BSC
0
PLANE
M
0
8
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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7
MC74HCT573A
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
20
11
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
e
A
DIM MIN
MAX
2.05
0.20
0.50
0.25
12.80
5.45
MAX
0.081
0.008
0.020
0.010
0.504
0.215
c
A
---
0.05
0.35
0.15
12.35
5.10
---
0.002
0.014
0.006
0.486
0.201
A
1
b
c
D
E
e
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
10
_
0.035
0.032
0
_
_
_
0.70
---
0.90
0.81
0.028
---
1
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74HCT573A/D
相关型号：
MC74HCT573AFEL
Octal 3-State Inverter Transceiver/Latch; Package: SOEIAJ-20; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2000
ONSEMI
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