MC74LV594ADR2G [ONSEMI]
8-Bit Shift Register with Output Register;
| 型号： | MC74LV594ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Shift Register with Output Register |
| 文件： | 总13页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LV594A
8-Bit Shift Register with
Output Register
The MC74LV594A is an 8−bit shift register designed for
2 V to 6.0 V VCC operation. The device contain an 8−bit serial−in,
parallel−out shift register that feeds an 8−bit D−type storage register.
Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR,
SRCLR) inputs are provided on the shift and storage registers. A serial
output (QH’) is provided for cascading purposes.
The shift−register (SRCLK) and storage−register (RCLK) clocks
are positive−edge triggered. If the clocks are tied together, the shift
register always is one clock pulse ahead of the storage register.
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
LV594AG
AWLYWW
16
1
Features
1
16
• 2.0 V to 6.0 V V Operation
CC
• Low Input Current: 1.0 mA
TSSOP−16
DT SUFFIX
CASE 948F
LV
594A
ALYWG
G
16
• Max t of 6.5 ns at 5 V
pd
• Typical V
(Output Ground Bounce) < 0.8 V
OLP
1
at V = 3.3 V, T = 25°C
CC
A
1
• Typical V
(Output V Undershoot) > 2.3 V
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
OHV
OH
at V = 3.3 V, T = 25°C
CC
A
• Support Mixed−Mode Voltage Operation on All Ports
• 8−Bit Serial−In, Parallel−Out Shift Registers With Storage
• Independent Direct Overriding Clears on Shift and Storage Registers
• Independent Clocks for Shift and Storage Registers
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
V
16
15
CC
Q
1
2
B
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Q
Q
Q
A
C
3
D
SER
14
13
RCLR
Q
4
E
5
Q
Q
12
RCLR
F
6
SRCLR
SRCLR
11
10
9
G
7
8
Q
H
GND
Q
H’
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
May, 2018 − Rev. 2
MC74LV594A/D
MC74LV594A
FUNCTION TABLE
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2
MC74LV594A
Figure 1. Logic Diagram
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3
MC74LV594A
Figure 2. Timing Diagram
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LV594ADR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
MC74LV594ADTR2G
TSSOP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74LV594A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
−0.5 to +7.0
V
I
−0.5 to V + 0.5
V
CC
V
DC Output Voltage Active Mode (Note 1)
High Impedance or Power−Off Mode
DC Input Clamp Current
−0.5 to V + 0.5
V
O
CC
−0.5 to +7.0
I
IK
20
mA
mA
mA
mA
mA
mA
°C
I
DC Output Clamp Current
35
OK
I
IN
DC Input Current
20
35
I
O
DC Output Source / Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
I
75
CC
I
75
GND
T
STG
−65 to +150
260
T
Lead temperature, 1 mm from Case for 10 Seconds
Junction temperature under Bias
°C
L
T
+150
°C
J
q
Thermal Resistance SOIC
TSSOP
112
148
°C
JA
P
D
Power Dissipation in Still Air at SOIC
TSSOP
500
450
mW
MSL
Moisture Sensitivity
Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35%
UL−94−VO (0.125 in)
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
> 3000
>400
N/A
V
Charged Device Model (Note 4)
I
Latchup Performance Above V and Below GND at 85°C (Note 5)
300
mA
Latchup
CC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I absolute maximum rating must be observed.
O
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS (Note 6)
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
0
Max
Unit
V
V
CC
6.0
V
I
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
Operating Free−Air Temperature
V
CC
V
CC
V
V
O
0
V
T
A
−55
+85
°C
nS
t , t
Input Rise or Fall Rate
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. All unused inputs of the device must be held at V or GND to ensure proper device operation.
CC
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5
MC74LV594A
DC ELECTRICAL CHARACTERISTICS
Guaranteed Limits
T
A
= 255C
Typ
T
= −555C to 1255C
A
Min
1.5
Max
Min
1.5
0.7 x V
Max
Symbol
Parameter
Conditions
V
, (V)
Unit
CC
Minimum
High−Level In-
put Voltage
2.0
V
IH
V
2.3 – 6.0
2.0
0.7 x V
CC
CC
Maximum
0.5
0.5
Low−Level In-
put Voltage
V
V
V
IL
2.3 – 6.0
0.3 x V
0.3 x V
CC
CC
V
= V or V
IH IL
IN
V
0.1
–
CC
I
= −50 mA
2.0 – 6.0
V
CC
– 0.1
oH
Minimum
High−Level
Output Voltage
V
OH
I
= −2 mA
= −6 mA
= −12 mA
2.3
3.0
4.5
2
2
oH
I
2.48
3.8
2.48
3.8
oH
I
oH
V
IN
= V or V
IH IL
I
= 50 mA
= 2 mA
= 6 mA
= 12 mA
2.0 – 6.0
2.3
0.1
0.4
0.1
0.4
oH
Maximum
Low−Level
Output Voltage
I
V
OL
V
oH
oH
I
3.0
0.44
0.55
0.44
0.55
I
oH
4.5
Maximum In-
put Leakage
Current
V = V or
I
CC
I
6.0
0.1
3.5
1
mA
IN
GND
Maximum Sup-
ply Current
V = V or
I CC
I
6.0
3.3
8.0
80
mA
CC
GND, I = 0 A
O
Input Capacit-
ance
V = V or
I CC
C
pF
I
GND
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
MC74LV594A
TIMING SPECIFICATIONS (See Figure 3)
T
= 255C
T
= −555C to 1255C
A
A
Min
7
Max
Min
Max
Symbol
Parameter
Pulse Duration
Conditions
V
, (V)
Unit
CC
t
W
RCLK or SRCLK
High or Low
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
7.5
5.5
5
ns
5.5
5
RCLR or SRCLR Low
6
6.5
5
5
5.2
5.5
3.5
3
5.2
5.5
3.5
3
SER before SRCLK↑
8
9
SRCLK↑ before
RCLK↑
8
8.5
5
5
SRCLR Low before
8.5
8
9.5
9
RCLK↑
t
Setup Time
ns
SU
5
5
SRCLR High (Inactive)
before
6
6.8
4.8
3.3
7.6
5.3
3.7
1.5
1.5
2
4.2
2.9
6.7
4.6
3.2
1.5
1.5
2
SRCLK↑
RCLR High (Inactive)
before RCLK↑
t
H
Hold Time
SER after SRCLK↑
ns
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7
MC74LV594A
AC CHARACTERISTICS (See Figure 3)
Guaranteed Limits
T
= −555C to
1255C
A
Load
Condi-
tions
T
A
= 255C
Typ
Min
65
Max
Min
Max
Symbol
Paraeter
Input to Output
V
, (V)
Unit
CC
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
80
45
70
115
40
55
90
1
C = 15 pF
80
120
170
51
L
135
50
f
MHz
MAX
C = 50 pF
70
74
L
115
120
27.5
18
32.5
22.5
15
RCLK to
1
Q −Q
A
H
12
1
C = 15 pF
L
27.5
18
1
32
SRCLK to Q
RCLK to
1
22
H’
H’
H’
H’
H’
H’
Propagation
Delay Low to
High
12.5
25.0
17.5
12.5
25.5
18.0
12.5
23
1
12
t
ns
PLH
22.1
15.6
11.5
21.6
15.2
10.9
1
30.0
21.0
15.5
29.5
21.0
15.0
27.5
19
1
Q −Q
A
H
1
C = 50 pF
L
1
SRCLK to Q
RCLK to
1
1
1
15.5
11
1
Q −Q
A
H
1
14
23.5
16
1
27
SRCLK to Q
RCLR to
1
19
11
1
13.5
25
C = 15 pF
L
20.5
14.5
10
1
1
17.5
12
Q −Q
A
H
1
1
23
SRCLR to Q
RCLK to
13
1
16
Propagation
Delay High to
Low
9
1
11
t
ns
PHL
19.7
14.0
10.1
18.4
13.1
9.0
23.0
16.5
11.5
21.5
15.0
10.5
30.0
20.0
13.5
30.0
20.0
14.0
1
27.0
19.5
13.5
25.0
18.0
12.5
35.0
24.5
17.0
34
1
Q −Q
A
H
1
1
SRCLK to Q
RCLR to
1
1
C = 50 pF
L
25.7
17.6
12.2
25.3
17.3
11.9
1
1
Q −Q
A
H
1
1
SRCLR to Q
1
24.0
16.5
1
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8
MC74LV594A
NOISE CHARACTERISTICS, V = 3.3 V, C = 50 pF, T = 25°C
CC
L
A
Symbol
Parameter
Min
Typ
0.8
Max
0.8
Unit
V
V
V
Quiet Output, Maximum Dynamic V
OL(P)
OL(V)
OH(V)
OL
OL
Quiet Output, Minimum Dynamic V
Quiet Output, Minimum Dynamic V
High−Level Dynamic Input Voltage
Low−Level Dynamic Input Voltage
−0.1
2.8
−0.8
V
V
V
OH
V
IH(D)
2.31
V
V
IL(D)
0.99
V
POWER DISSIPATION CHARACTERISTICS, T = 25°C
A
Symbol
Parameter
Power Dissipation Capacitance
Test Conditions
V
(V)
Typ
Unit
CC
C
f = 10 MHz
3.3
93
pF
PD
5
112
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9
MC74LV594A
Figure 3. Load Circuit and Voltage Waveforms
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
B
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
0.65
PITCH
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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