MC74LVX257 [ONSEMI]
Quad 2-Channel Multiplexer with 3-State Outputs; 四路2通道多路复用器与三态输出
| 型号： | MC74LVX257 |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2-Channel Multiplexer with 3-State Outputs |
| 文件： | 总8页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX257
Quad 2−Channel Multiplexer
with 3−State Outputs
The MC74LVX257 is an advanced high speed CMOS quad
2−channel multiplexer fabricated with silicon gate CMOS technology.
It consists of four 2−input digital multiplexers with common select
(S) and enable (OE) inputs. When (OE) is held High, selection of data
is inhibited and all the outputs go Low.
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MARKING
DIAGRAMS
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The inputs tolerate voltages up to 7.0 V, allowing the interface of
5.0 V systems to 3.0 V systems.
16
SOIC−16
D SUFFIX
CASE 751B
Features
LVX257
AWLYWW
• High Speed: t = 4.5 ns (Typ) at V = 3.3 V
PD
CC
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
1
CC
A
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
16
LVX
257
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
• Low Noise: V
= 0.8 V (Max)
OLP
1
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• Chip Complexity: FETs = 100; Equivalent Gates = 25
• ESD Performance:
16
1
SOEIAJ−16
M SUFFIX
CASE 966
Human Body Model > 2000 V;
Machine Model > 200 V
LVX257
ALYW
• Pb−Free Packages are Available*
A
=
=
=
=
Assembly Location
Wafer Lot
Year
WL or L
Y
WW or W
Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
March, 2005 − Rev. 3
MC74LVX257/D
MC74LVX257
2
4
I0a
Za
Zb
Zc
Zd
3
I1a
V
S
1
2
16
15
CC
5
A0
OE
A3
B3
7
I0b
6
B0
Y0
I1b
3
4
14
13
14
12
9
I0c
13
A1
B1
5
6
12
11
Y3
A2
I1c
11
I0d
7
8
10
9
B2
Y2
Y1
10
I1d
GND
15
OE
Figure 1. Pin Assignment
1
S
Figure 2. Expanded Logic Diagram
15
1
OE
S
EN
G1
2
3
5
6
MUX
A0
B0
A1
B1
1
1
4
7
Y0
Y1
Y2
Y3
FUNCTION TABLE
Inputs
Outputs
OE
S
Y0 − Y3
11
10
14
13
A2
B2
9
H
L
L
X
L
H
Z
A0−A3
B0−B3
A3
B3
12
A0 − A3, B0 − B3 = the levels
of the respective Data−Word
Inputs.
Figure 3. IEC Logic Symbol
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVX257D
SOIC−16
48 Units / Rail
48 Units / Rail
MC74LVX257DG
SOIC−16
(Pb−Free)
MC74LVX257DR2
MC74LVX257DR2G
SOIC−16
2500 Tape & Reel
2500 Tape & Reel
SOIC−16
(Pb−Free)
MC74LVX257DT
MC74LVX257DTR2
MC74LVX257M
TSSOP−16*
TSSOP−16*
SOEIAJ−16
SOEIAJ−16
96 Units / Rail
2500 Tape & Reel
50 Units / Rail
MC74LVX257MEL
MC74LVX257MELG
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVX257
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
Positive DC Supply Voltage
Digital Input Voltage
−0.5 to +7.0
−0.5 to +7.0
V
IN
V
V
OUT
DC Output Voltage
−0.5 to V +0.5
V
CC
I
Input Diode Current
−20
$20
$25
$75
mA
mA
mA
mA
mW
IK
I
Output Diode Current
DC Output Current, per Pin
OK
I
OUT
I
DC Supply Current, V and GND Pins
CC
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
V
Storage Temperature Range
ESD Withstand Voltage
−65 to +150
°C
STG
Human Body Model (Note 1)
Machine Model (Note 2)
>2000
>200
V
ESD
Charged Device Model (Note 3)
>2000
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
$300
mA
LATCHU
P
CC
q
Thermal Resistance, Junction−to−Ambient
SOIC Package
TSSOP
143
164
°C/W
JA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
This device contains protection
circuitry to guard against damage
RECOMMENDED OPERATING CONDITIONS
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
Symbol
Characteristics
DC Supply Voltage
Min
2.0
0
Max
3.6
Unit
V
V
CC
V
IN
DC Input Voltage
5.5
V
V
OUT
DC Output Voltage
0
V
CC
V
cuit. For proper operation, V and
in
V
should be constrained to the
out
T
Operating Temperature Range, all Package
Types
−40
85
°C
A
range GND v (V or V ) v V
.
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
t , t
r
Input Rise or Fall Time
V = 3.3 V + 0.3 V
CC
0
100
ns/V
f
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
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3
MC74LVX257
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
T
A
= 25°C
−40°C ≤ T ≤ 85°C
A
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
3.6
0.75 V
0.7 V
0.7 V
0.75 V
0.7 V
0.7 V
V
CC
CC
CC
CC
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0
3.6
0.25 V
0.3 V
0.3 V
0.25 V
0.3 V
0.3 V
V
V
IL
CC
CC
CC
CC
CC
CC
V
OH
High−Level Output
Voltage
I
= −50 mA
= −50 mA
= −4 mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
I
OH
I
OH
V
OL
Low−Level Output
Voltage
I
= 50 mA
= 50 mA
= 4 mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
V
OL
I
OL
I
OL
I
Maximum 3−State
Leakage Current
V
V
= V or V
IL
3.6
±0.1
±1.0
mA
OZ
IN
IH
= V or GND
OUT
CC
I
Input Leakage Current
V
IN
V
IN
= 5.5 V or GND
0 to 3.6
3.6
±0.1
±1.0
mA
mA
IN
I
Maximum Quiescent
Supply Current
= V or GND
1.0
1.0
2.0
40
CC
CC
(per package)
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
−40°C ≤ T ≤ 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
t
,
Maximum Propagation
Delay, A or B to Y
V
V
V
V
V
= 2.7 V
C = 15pF
C = 50pF
L
6.5
9.5
10.0
14.0
1.0
1.0
15.0
18.5
ns
PLH
t
CC
CC
CC
CC
CC
L
PHL
= 3.3 V ± 0.3 V
= 2.7 V
C = 15pF
4.5
7.5
8.0
12.0
1.0
1.0
10.0
13.5
L
C = 50pF
L
,
Maximum Propagation
Delay, S to Y
C = 15pF
8.0
10.5
12.0
15.5
1.0
1.0
17.0
20.0
ns
ns
ns
PLH
t
L
C = 50pF
L
PHL
= 3.3 V ± 0.3 V
= 2.7 V
C = 15pF
6.0
8.5
10.0
13.5
1.0
1.0
12.0
15.5
L
C = 50pF
L
,
Maximum Output
Enable, Time, OE to Y
C = 15pF
7.5
10.5
11.5
15.0
1.0
1.0
16.5
18.0
PZL
t
L
R = 1 kW
C = 50pF
L
PZH
L
V
CC
= 3.3 V ± 0.3 V
C = 15pF
5.5
8.5
9.5
13.0
1.0
1.0
11.5
15.0
L
R = 1 kW
C = 50pF
L
L
,
Maximum Output
Disable, Time, OE to Y
V
CC
= 2.7
C = 50pF
L
13.0
12
4
17.0
17.0
10
1.0
18.0
18.0
10
PLZ
t
R = 1 kW
L
PHZ
V
CC
= 3.3 V ± 0.3 V
C = 50pF
L
1.0
R = 1 kW
L
C
Maximum Input
Capacitance
pF
pF
IN
Typical @ 25°C, V = 3.3 V
CC
20
C
Power Dissipation Capacitance (Note 5)
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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4
MC74LVX257
NOISE CHARACTERISTICS Input t = t = 3.0 ns, C = 50 pF, V = 3.3 V
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
Symbol
Characteristic
Unit
V
V
V
Quiet Output Maximum Dynamic V
0.5
−0.5
2.0
OLP
OL
Quiet Output Minimum Dynamic V
−0.3
V
OLV
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
0.8
V
V
CC
OE
50%
GND
V
CC
t
t
PLZ
50%
PZL
A, B or S
HIGH
GND
IMPEDANCE
t
50% V
PHL
Y
Y
CC
t
PLH
V
V
+ 0.3V
OL
t
t
PHZ
PZH
50% V
CC
Y
− 0.3V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 4. Switching Waveform
Figure 5. Switching Waveform
TEST POINT
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
1 kW
TESTING t AND t
PLZ
OUTPUT
PZL.
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
DEVICE
UNDER
TEST
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
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5
MC74LVX257
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
G
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
7
0
_
_
_
_
M
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
NOTES:
16X KREF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
1
N
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.25 (0.010)
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
S
0.15 (0.006) T U
A
M
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
−V−
1.20
−−− 0.047
N
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
DETAIL E
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
6.40 BSC
0.252 BSC
−W−
C
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
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6
MC74LVX257
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
L
E
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
Q
1
H
E
M
_
E
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
−−−
0.05
0.35
0.18
9.90
5.10
2.05
A
A
1
0.20 0.002
0.50 0.014
0.27 0.007
1
b
0.13 (0.005)
b
c
0.10 (0.004)
M
D
E
10.50 0.390
5.45 0.201
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
_
0.035
0.031
0
_
_
_
0.70
−−−
1
Z
0.78
−−−
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7
MC74LVX257
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74LVX257/D
相关型号：
MC74LVX257MG
IC LV/LV-A/LVX/H SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, EIAJ, SO-16, Multiplexer/Demultiplexer
ONSEMI
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