MC74LVX32DR2G [ONSEMI]
Quad 2-Input OR Gate;
| 型号： | MC74LVX32DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2-Input OR Gate 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX32
Quad 2-Input OR Gate
With 5 V−Tolerant Inputs
The MC74LVX32 is an advanced high speed CMOS 2−input OR
gate. The inputs tolerate voltages up to 7.0 V, allowing the interface of
5.0 V systems to 3.0 V systems.
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Features
• High Speed: t = 4.4 ns (Typ) at V = 3.3 V
PD
CC
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C
CC
A
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
PIN ASSIGNMENT
• Low Noise: V
= 0.5 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
V
CC
A2 B2 O2 A3 B3 O3
14 13 12 11 10
9
8
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
• These Devices are Pb−Free and are RoHS Compliant
1
2
3
4
5
6
7
1
A0 B0 O0 A1 B1 O1 GND
A0
3
O0
2
14−Lead (Top View)
B0
4
A1
6
MARKING DIAGRAMS
O1
5
B1
13
A2
14
11
O2
12
LVX32G
AWLYWW
B2
10
A3
8
O3
9
1
B3
SOIC−14 NB
Figure 1. Logic Diagram
14
PIN NAMES
LVX
32
Pins
Function
ALYWG
An, Bn
On
Data Inputs
Outputs
G
1
TSSOP−14
FUNCTION TABLE
INPUTS
LVX32 = Specific Device Code
OUTPUTS
On
A
= Assembly Location
WL, L = Wafer Lot
= Year
An
Bn
Y
L
L
H
H
L
H
L
L
H
H
H
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2014 − Rev. 4
MC74LVX32/D
MC74LVX32
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to +7.0
V
in
V
V
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
–0.5 to V + 0.5
V
out
IK
CC
I
−20
mA
mA
mA
mA
mW
_C
I
20
25
OK
I
out
CC
I
DC Supply Current, V and GND Pins
50
CC
P
Power Dissipation
180
D
T
stg
Storage Temperature
–65 to +150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
3.6
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature, All Package Types
Input Rise and Fall Time
−40
0
+85
100
_C
ns/V
A
Dt/DV
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = −40 to 85°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
V
IH
High−Level Input Voltage
2.0
3.0
3.6
1.5
2.0
2.4
1.5
2.0
2.4
V
V
Low−Level Input Voltage
2.0
3.0
3.6
0.5
0.8
0.8
0.5
0.8
0.8
V
V
V
IL
V
OH
High−Level Output Voltage
(V = V or V )
I
I
I
= −50mA
= −50mA
= −4mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
OH
OH
in
IH
IL
V
OL
Low−Level Output Voltage
(V = V or V )
I
OL
I
OL
I
OL
= 50mA
= 50mA
= 4mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
in
IH
IL
I
Input Leakage Current
V
V
= 5.5V or GND
3.6
3.6
0.1
2.0
1.0
mA
mA
in
in
I
Quiescent Supply Current
= V or GND
20.0
CC
in
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
MC74LVX32
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = −40 to 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
,
Propagation Delay, Input to
Output
V
V
= 2.7V
C = 15pF
C = 50pF
L
5.8
8.3
10.7
14.2
1.0
1.0
13.5
17.0
ns
PLH
CC
L
PHL
= 3.3 0.3V
C = 15pF
4.4
6.9
6.6
10.1
1.0
1.0
8.0
11.5
CC
L
C = 50pF
L
t
t
Output−to−Output Skew
(Note 1)
V
CC
V
CC
= 2.7V
= 3.3 0.3V
C = 50pF
C = 50pF
L
1.5
1.5
1.5
1.5
ns
OSHL
OSLH
L
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
guaranteed by design.
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
CAPACITIVE CHARACTERISTICS
T
A
= 25°C
Typ
4
T = −40 to 85°C
A
Min
Max
Min
Max
10
Symbol
Parameter
Unit
pF
Cin
Input Capacitance
Power Dissipation Capacitance (Note 2)
10
C
14
pF
PD
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /4 (per gate). C is used to determine the
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 3.3V, Measured in SOIC Package)
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
Symbol
Characteristic
Unit
V
V
Quiet Output Maximum Dynamic V
0.5
−0.5
2.0
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−0.3
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
0.8
V
TEST POINT
V
CC
A or B
OUTPUT
50%
DEVICE
UNDER
TEST
GND
t
t
PHL
PLH
C *
L
O
50% V
CC
*Includes all probe and jig capacitance
Figure 2. Switching Waveforms
Figure 3. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVX32DR2G
SOIC−14 NB
(Pb−Free)
2500 Tape & Reel
2500 Tape & Reel
MC74LVX32DTR2G
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
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相关型号：
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MOTOROLA
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