MC74LVX4245_17 [ONSEMI]
Dual Supply Octal Translating Transceiver;型号: | MC74LVX4245_17 |
厂家: | ONSEMI |
描述: | Dual Supply Octal Translating Transceiver |
文件: | 总10页 (文件大小:104K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74LVX4245
Dual Supply Octal
Translating Transceiver
with 3−State Outputs
The 74LVX4245 is a 24−pin dual−supply, octal translating
transceiver that is designed to interface between a 5.0 V bus and a 3.0 V
bus in a mixed 3.0 V / 5.0 V supply environment such as laptop
computers using a 3.3 V CPU and 5.0 V LCD display. The A port
interfaces with the 5V bus; the B port interfaces with the 3.0 V bus.
The Transmit/Receive (T/R) input determines the direction of data
flow. Transmit (active−High) enables data from the A port to the B
port. Receive (active−Low) enables data from the B port to the A port.
The Output Enable (OE) input, when High, disables both A and B
ports by placing them in 3−State.
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MARKING
DIAGRAMS
24
24
SOIC−24
DW SUFFIX
CASE 751E
LVX4245
AWLYYWWG
1
1
Features
• Bi−directional Interface Between 5.0 V and 3.0 V Buses
• Control Inputs Compatible with TTL Level
• 5.0 V Data Flow at A Port and 3.0 V Data Flow at B Port
• Outputs Source/Sink 24 mA at 5.0 V Bus and 12 mA at 3.0 V Bus
• Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
24
LVX
4245G
ALYW
24
TSSOP−24
DT SUFFIX
CASE 948H
1
1
• Available in SOIC and TSSOP Packages
LVX4245 = Specific Device Code
A
WL, L
Y
= Assembly Location
= Wafer Lot
= Year
• Functionally Compatible with the 74 Series 245
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
WW, W
G or G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN NAMES
Pins
Function
V
V
OE B0
B1
20
B2
19
B3
18
B4
17
B5
16
B6
15
B7 GND
14
CCB
CCB
OE
T/R
A0−A7
Output Enable Input
Transmit/Receive Input
Side A 3−State Inputs or 3−State
Outputs
24
23
22
21
13
B0−B7
Side B 3−State Inputs or 3−State
Outputs
1
2
3
4
5
6
7
9
11
8
10
12
ORDERING INFORMATION
See detailed ordering and shipping information in the package
V
T/R A0
A1
A2
A3
A4
A5
A6
A7 GND GND
CCA
dimensions section on page 5 of this data sheet.
Figure 1. 24−Lead Pinout
(Top View)
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
July, 2017 − Rev. 6
MC74LVX4245/D
MC74LVX4245
OE 22
T/R 2
3
4
A0
A1
A2
A3
A4
A5
A6
A7
21
20
19
18
17
16
15
14
B0
B1
B2
B3
B4
B5
B6
B7
5
6
7
8
9
10
Figure 2. Logic Diagram
INPUTS
OPERATING MODE
Non−Inverting
OE
T/R
L
L
L
H
X
B Data to A Bus
A Data to B Bus
Z
H
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level
and Transitions are Acceptable; For I reasons, Do Not Float Inputs
CC
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2
MC74LVX4245
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
V
CCA
,
DC Supply Voltage
−0.5 to +7.0
V
V
CCB
V
DC Input Voltage
OE, T/R
An
−0.5 to V
+0.5
V
I
CCA
CCA
CCB
V
I/O
DC Input/Output Voltage
−0.5 to V
−0.5 to V
+0.5
+0.5
V
Bn
V
I
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current
OE, T/R
20
V < GND
mA
mA
mA
mA
IK
I
I
50
50
V < GND; V > V
O O CC
OK
I
O
I
,
Per Output Pin
50
CC
I
Maximum Current at I
Maximum Current at I
200
100
GND
CCA
CCB
T
Storage Temperature Range
−65 to +150
300
°C
STG
Latchup DC Latchup Source/Sink Current
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
V
,
Supply Voltage
V
CCA
V
CCB
4.5
2.7
5.5
3.6
V
CCA
CCB
V
Input Voltage
OE, T/R
0
V
V
V
I
CCA
V
I/O
Input/Output Voltage
An
Bn
0
0
V
CCA
V
CCB
T
Operating Free−Air Temperature
Minimum Input Edge Rate
−40
0
+85
8
°C
A
Dt/DV
ns/V
V
IN
from 30% to 70% of V ; V at 3.0V, 4.5V, 5.5V
CC CC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = −40 to +85°C
A
Symbol
Parameter
Condition
≤ 0.1V
V
V
Typ
Guaranteed Limits
Unit
CCA
CCB
V
IHA
An,OE
T/R
5.5
4.5
3.3
3.3
2.0
2.0
2.0
2.0
V
Minimum HIGH
V
OUT
Level
or
≥ V − 0.1V
Input Voltage
V
IHB
5.0
5.0
3.6
2.7
2.0
2.0
2.0
2.0
V
V
V
V
V
CC
Bn
V
An,OE
T/R
5.5
4.5
3.3
3.3
0.8
0.8
0.8
0.8
Maximum LOW
Level
Input Voltage
ILA
ILB
V
≤ 0.1V
OUT
or
V
5.0
5.0
2.7
3.6
0.8
0.8
0.8
0.8
≥ V − 0.1V
CC
Bn
V
V
I
I
= −100mA
4.5
4.5
3.0
3.0
4.50
4.25
4.40
3.86
4.40
3.76
Minimum HIGH
Level
Output Voltage
OHA
OUT
I
= −24mA
OH
= −100mA
= −12mA
= −8mA
4.5
4.5
4.5
3.0
3.0
2.7
2.99
2.80
2.50
2.9
2.4
2.4
2.9
2.4
2.4
OHB
OUT
I
I
OH
OH
V
V
I
= 100mA
= 24mA
4.5
4.5
3.0
3.0
0.002
0.18
0.10
0.36
0.10
0.44
V
V
Maximum LOW
Level
Output Voltage
OLA
OUT
I
OL
I
= 100mA
= 12mA
= 8mA
4.5
4.5
4.5
3.0
3.0
2.7
0.002
0.1
0.1
0.10
0.31
0.31
0.10
0.40
0.40
OLB
OUT
I
OL
I
OL
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3
MC74LVX4245
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = −40 to +85°C
A
Symbol
Parameter
Max Input Leak-
age
Current
Condition
, GND
V
V
Typ
Guaranteed Limits
Unit
CCA
CCB
I
IN
mA
OE,
T/R
V = V
5.5
5.5
5.5
3.6
3.6
3.6
0.1
1.0
I
CCA
I
I
Max 3−State Out-
put Leakage
V = V , V
mA
mA
OZA
OZB
I
IH
IL
An
Bn
OE = V
= V
0.5
0.5
5.0
5.0
CCA
, GND
CCA
V
V
O
Max 3−State Out-
put Leakage
V = V , V
I
IH
IL
OE = V
= V
CCA
, GND
CCB
O
DI
CC
Maximum I
per Input
An,OE
T/R
mA
CCT
V =V
−2.1V
−0.6V
5.5
5.5
3.6
3.6
1.0
1.35
0.35
1.5
0.5
I
CCA
CCB
Bn
V =V
I
mA
I
Quiescent V
Supply Current
An=V
Bn=V
or GND
or GND
mA
CCA
CCA
CCA
CCB
5.5
5.5
3.6
3.6
8
5
80
50
OE=GND
T/R=GND
I
Quiescent V
An=V
or GND
or GND
mA
CCB
CCB
CCA
Supply Current
Bn=V
CCB
OE=GND
T/R=V
CCA
V
V
Quiet Output Max
5.0
5.0
3.3
3.3
1.5
1.2
V
V
V
OLPA
OLPB
Notes 1, 2
Notes 1, 2
Dynamic V
OL
V
OLVA
V
OLVB
Quiet Output Min
5.0
5.0
3.3
3.3
−1.2
−0.8
Dynamic V
OL
V
V
Min HIGH Level
Dynamic Input
Voltage
IHDA
IHDB
5.0
5.0
3.3
3.3
2.0
2.0
Notes 1, 3
Notes 1, 3
V
V
Max LOW Level
Dynamic Input
Voltage
V
ILDA
ILDB
5.0
5.0
3.3
3.3
0.8
0.8
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Worst case package.
2. Max number of outputs defined as (n). Data inputs are driven 0V to V level; one output at GND.
CC
3. Max number of data inputs (n) switching. (n−1) inputs switching 0V to V level. Input under test switching: V level to threshold (V ),
CC
CC
IHD
0V to threshold (V ), f = 1MHz.
ILD
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
4.5
Unit
C
Input Capacitance
V
V
= 5.0V; V
= 5.0V; V
= 3.3V
= 3.3V
pF
pF
pF
IN
I/O
PD
CCA
CCB
CCB
C
C
Input/Output Capacitance
15
CCA
Power Dissipation Capacitance
(Measured at 10MHz)
B→A
A→B
V
CCA
V
CCB
= 5.0V
= 3.3V
55
40
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4
MC74LVX4245
AC ELECTRICAL CHARACTERISTICS
T
A
= −40 to +85°C
L
T = −40 to +85°C
A
C = 50pF
C = 50pF
L
V
CCA
= 5V 0.5V
V
CCA
= 5V 0.5V
V
CCB
= 3.3V 0.3V
V
CCB
= 2.7V
Typ
Symbol
Parameter
Propagation Delay A to B
Min
(Note 4)
Max
Min
Max
Unit
t
t
1.0
1.0
5.1
5.3
9.0
9.0
1.0
1.0
10.0
10.0
ns
PHL
PLH
t
t
Propagation Delay B to A
1.0
1.0
5.4
5.5
9.0
9.0
1.0
1.0
10.0
10.0
ns
ns
ns
ns
ns
ns
PHL
PLH
t
t
Output Enable Time OE to B
Output Enable Time OE to A
Output Disable Time OE to B
Output Disable Time OE to A
1.0
1.0
6.5
6.7
10.5
10.5
1.0
1.0
11.5
11.5
PZL
PZH
t
t
1.0
1.0
5.2
5.8
9.5
9.5
1.0
1.0
10.0
10.0
PZL
PZH
t
1.0
1.0
6.0
3.3
10.0
7.0
1.0
1.0
10.0
7.5
PHZ
t
PLZ
t
1.0
1.0
3.9
2.9
7.5
7.0
1.0
1.0
7.5
7.5
PHZ
t
PLZ
t
t
OSHL
OSLH
Output to Output Skew, Data to Output (Note 5)
1.0
1.5
1.5
4. Typical values at V
= 5.0V; V
= 3.3V at 25°C.
CCA
CCB
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
guaranteed by design.
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
ORDERING INFORMATION
†
Device
MC74LVX4245DWG
Package
Shipping
30 Units / Rail
1000 / Tape & Reel
62 Units / Rail
SOIC−24
(Pb−Free)
MC74LVX4245DWR2G
MC74LVX4245DTG
TSSOP−24
(Pb−Free)
MC74LVX4245DTR2G
NLVLVX4245DTR2G*
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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5
MC74LVX4245
Dual Supply Octal Translating Transceiver
The 74LVX4245 is a is a dual−supply device well capable
of bidirectional signal voltage translation. This level shifting
ability provides an excellent interface between low voltage
CPU local bus and a standard 5.0 V I/O bus. The device
control inputs can be controlled by either the low voltage
CPU and core logic or a bus arbitrator with 5.0 V I/O levels.
The LVX4245 is ideal for mixed voltage applications such
as notebook computers using a 3.3 V CPU and 5.0 V
peripheral devices.
LOW VOLTAGE CPU LOCAL BUS
V
V
V
CCB
CCB
LVX4245
LVX4245
V
CCA
CCA
Applications:
Mixed Mode Dual Supply Interface Solutions
EISA - ISA - MCA
(5V I/O LEVELS)
The LVX4245 is designed to solve 3.0 V / 5.0 V interfaces
when CMOS devices cannot tolerate I/O levels above their
Figure 3. 3.3V/5V Interface Block Diagram
Powering Up the LVX4245
applied V . If an I/O pin of a 3.0 V device is driven by a 5.0
CC
V device, the P−Channel transistor in the 3.0 V device will
conduct − causing current flow from the I/O bus to the 3.0 V
power supply. The result may be destruction of the 3.0 V
device through latchup effects. A current limiting resistor
may be used to prevent destruction, but it causes speed
degradation and needless power dissipation.
A better solution is provided in the LVX4245. It provides
two different output levels that easily handle the dual voltage
interface. The A port is a dedicated 5.0 V port; the B port is
a dedicated 3.0 V port.
When powering up the LVX4245, please note that if the
pin is powered−up well in advance of the V pin,
V
CCB
CCA
several milliamps of either I
or I
current will result.
CCA
CCB
If the V
pin is powered−up in advance of the V
pin
CCA
CCB
then only nanoamps of Icc current will result. In actuality the
can be powered “slightly” before the V without
V
CCB
CCA
the current penalty, but this “setup time” is dependent on the
power−up ramp rate of the V pins. With a ramp rate of
CC
approximately 50 mV/ns (50V/ms) a 25 ns setup time was
Since the LVX4245 is a ‘245 transceiver, the user may
either use it for bidirectional or unidirectional applications.
The center 20 pins are configured to match a ‘245 pinout.
This enables the user to easily replace this level shifter with
a 3.0 V ‘245 device without additional layout work or re−
manufacture of the circuit board (when both buses are 3.0 V).
observed (V
before V
). With a 7.0 V/ms rate, the
CCB
CCA
setup time was about 140ns. When all is said and done, the
safest powerup strategy is to simply power V before
CCA
V . One more note: if the V
CCB
ramp rate is faster than
CCB
the V
ramp rate then power problems might still occur,
CCA
even if the V
powerup began prior to the V
powerup.
CCA
CCB
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6
MC74LVX4245
MICROCHANNEL/
EISA/ISA/AT
5V BUS
LOCAL
3V BUS
5V
3V
KEYBOARD
CACHE
SRAM
CONTROLLER
SUPER
I/O
5V
3V
V
V
CCB
CCA
CPU
CORE
LOGIC
386/486
LVX4245
A PORT
A0:7
B PORT
B0:7
TRANSCEIVERS
ROM
BIOS
PCMCIA
CONTROLLER
MEMORY
DRIVER
VGA
CONTROLLER
Figure 4. MC74LVX4245 Fits Into a System with 3V Subsystem and 5V Subsystem
V
V
V
MC74LVX4245
CCA
CCB
(T/R) DIR
A0
CCB
OE
B0
B1
B2
B3
B4
B5
B6
B7
GND
A1
A2
STANDARD
74 SERIES
`245
A3
A4
A5
A6
A7
GND
GND
Figure 5. MC74LVX4245 Pin Arrangement Is Compatible to 20−Pin 74 Series ‘245s
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7
MC74LVX4245
V
CC
50% V
50% V
CC
CC
An, Bn
Bn, An
0V
t
t
PHL
PLH
V
OH
OL
50% V
50% V
CC
CC
V
WAVEFORM 1 - PROPAGATION DELAYS
t
R
= t = 2.5ns, 10% to 90%; f = 1MHz; t = 500ns
F W
V
CCA
50% V
50% V
CC
CC
OE, T/R
0V
t
t
PHZ
PZH
V
V
CC
- 0.3V
OH
50% V
An, Bn
CC
≈ 0V
t
t
PLZ
PZL
≈ V
CC
50% V
An, Bn
CC
V + 0.3V
OL
GND
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
t
R
= t = 2.5ns, 10% to 90%; f = 1MHz; t = 500ns
F W
Figure 6. AC Waveforms
V
CC
2 × V
CC
OPEN
R
1
PULSE
GENERATOR
DUT
R
T
C
R
L
L
TEST
SWITCH
t
t
, t
, t
, t
Open
PLH PHL PZH PHZ
, t
2 × V
PZL PLZ
CC
C = 50pF or equivalent (Includes jig and probe capacitance)
L
R = R = 500W or equivalent
L
1
R = Z
of pulse generator (typically 50W)
T
OUT
Figure 7. Test Circuit
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8
MC74LVX4245
PACKAGE DIMENSIONS
SOIC−24
DW SUFFIX
CASE 751E−04
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
H
D
A
B
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b AND c APPLY TO THE FLAT SEC-
TION OF THE LEAD AND ARE MEASURED BE-
TWEEN 0.10 AND 0.25 FROM THE LEAD TIP.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 mm PER SIDE. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
0.25
C
24
1
13
12
E
E1
L
C
DETAIL A
5. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
24X
b
PIN 1
INDICATOR
M
S
S
B
0.25
C A
MILLIMETERS
DIM
A
A1
b
c
D
MIN
2.35
0.13
0.35
0.23
15.25
MAX
2.65
0.29
0.49
0.32
15.54
TOP VIEW
NOTE 3
h
x 45
_
A
M
E
10.30 BSC
E1
e
h
L
M
7.40
1.27 BSC
7.60
c
SEATING
PLANE
e
A1
NOTE 5
DETAIL A
C
NOTE 3
0.25
0.41
0
0.75
0.90
8
END VIEW
SIDE VIEW
_
_
RECOMMENDED
SOLDERING FOOTPRINT*
24X
1.62
24X
0.52
11.00
1
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MC74LVX4245
PACKAGE DIMENSIONS
TSSOP−24
DT SUFFIX
CASE 948H
ISSUE B
NOTE 4
NOTES:
A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
D
NOTE 6
NOTE 6
L2
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
DAMBAR PROTRUSION SHALL BE 0.08 MAX AT MMC. DAMBAR
CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS
OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMEN-
SION D IS DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 PER SIDE. DIMENSION E1 IS DETERMINED AT DA-
TUM PLANE H.
B
24
13
GAUGE
PLANE
L
NOTE 5
E1
C
E
DETAIL A
6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEAT-
ING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
PIN 1
REFERENCE
1
12
S
0.15 C B
e
2X 12 TIPS
24X b
MILLIMETERS
DIM MIN
MAX
1.20
0.15
0.30
0.20
7.90
0.10 M C B
A
S S
A
A1
b
---
0.05
0.19
0.09
7.70
NOTE 3
TOP VIEW
SIDE VIEW
A
c
DETAIL A
H
D
A1
0.05
0.10
C
C
E
6.40 BSC
E1
e
4.30
4.50
0.75
0.65 BSC
L
0.50
c
SEATING
PLANE
L2
M
0.25 BSC
24X
C
M
END VIEW
0
8
_
_
RECOMMENDED
SOLDERING FOOTPRINT
24X
0.42
24X
1.15
6.70
0.65
PITCH
DIMENSIONS: MILLIMETERS
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