MC74LVX595MEL [ONSEMI]
8âBit Shift Register;
| 型号： | MC74LVX595MEL |
| 厂家： | 
ONSEMI |
| 描述： | 8âBit Shift Register 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总14页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX595
Product Preview
8−Bit Shift Register with
Output Storage Register
(3−State)
http://onsemi.com
MARKING DIAGRAMS
The MC74LVX595 is an advanced high speed 8−bit shift register
with an output storage register fabricated with silicon gate CMOS
technology.
The MC74LVX595 contains an 8−bit static shift register which
feeds an 8−bit storage register.
Shift operation is accomplished on the positive going transition of
the Shift Clock input (SCK). The output register is loaded with the
contents of the shift register on the positive going transition of the
Register Clock input (RCK). Since the RCK and SCK signals are
independent, parallel outputs can be held stable during the shift
operation. And, since the parallel outputs are 3−state, the LVX595 can
be directly connected to an 8−bit bus. This register can be used in
serial−to−parallelconversion, data receivers, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
16
9
LVX595
AWLYYWW
SOIC−16
D SUFFIX
CASE 751B
1
8
16
9
LVX
595
TSSOP−16
DT SUFFIX
CASE 948F
AWLYWW
1
8
16
9
LVX595
ALYW
• High Speed: f
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
• High Noise Immunity: V
= 100 MHz (Typ) at V = 3.3 V
CC
max
SOIC EIAJ−16
M SUFFIX
CASE 966
CC
A
1
8
= V = 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 3.6 V Operating Range
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
• Low Noise: V
= 1.0 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
ORDERING INFORMATION
Device
Package
Shipping
MC74LVX595M
SO EIAJ−16 48 Units/Rail
MC74LVX595MEL
SO EIAJ−16 2000 Units/Reel
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 2
MC74LVX595/D
MC74LVX595
FUNCTION TABLE
Inputs
Resulting Function
Serial
Input
(SI)
Shift
Clock
(SCK)
Reg
Clock
(RCK)
Output
Enable
(OE)
Shift
Register
Contents
Storage
Register
Contents
Serial
Output
(SQH)
Parallel
Outputs
(QA − QH)
Reset
(SCLR)
Operation
Clear shift register
L
X
D
X
L, H, ↓
L, H, ↓
L
L
L
U
U
L
U
U
Shift data into shift
register
H
↑
D→SR ;
SR →SR
SR →SR
A
G
H
N
N+1
Registers remains
unchanged
H
H
X
X
L, H, ↓
L, H, ↓
X
L
L
U
U
**
U
*
**
Transfer shift register
contents to storage
register
↑
SR ³STR
SR
N
N
N
Storage register remains
unchanged
X
X
X
L, H, ↓
L
*
U
*
U
Enable parallel outputs
X
X
X
X
X
X
X
X
L
*
*
**
**
*
*
Enabled
Z
Force outputs into high
impedance state
H
SR = shift register contents
STR = storage register contents U = remains unchanged
D = data (L, H) logic level
↓ = High−to−Low
↑ = Low−to−High
* = depends on Reset and Shift Clock inputs
** = depends on Register Clock input
13
OE
QB
QC
1
2
16
V
CC
EN3
C2
12
RSK
15 QA
SRG8
R
QD
QE
QF
3
4
5
14 SI
10
SCLR
11
13 OE
12 RCK
SCK
C/1
14
SI
15
1D
2D
3
QA
QB
QG
QH
6
7
8
11 SCK
1
10 SCLR
2
3
4
QC
GND
9
SQH
QD
QE
Figure 1. Pin Assignment
5
6
7
9
QF
QG
QH
SERIAL
DATA
INPUT
14
15
1
3
2D
QA
QB
SI
SQH
2
3
4
QC
Figure 2. IEC Logic Symbol
PARALLEL
DATA
OUTPUTS
QD
QE
SHIFT
REGISTER
STORAGE
REGISTER
5
6
7
QF
QG
QH
11
10
12
13
SCK
SERIAL
DATA
OUTPUT
9
SQH
SCLR
RCK
OE
Figure 3. Logic Diagram
http://onsemi.com
2
MC74LVX595
13
12
14
OE
RCK
15
1
D
Q
D
D
D
D
D
D
D
D
Q
SI
QA
QB
QC
QD
QE
QF
QG
QH
SRA
STRA
R
D
Q
Q
SRB
STRB
R
D
2
Q
Q
SRC
STRC
R
D
3
Q
Q
SRD
STRD
PARALLEL
DATA
OUTPUTS
R
D
4
Q
Q
SRE
STRE
R
D
5
Q
Q
SRF
STRF
R
D
6
Q
Q
SRG
STRG
R
D
7
Q
Q
11
10
SRH
STRH
SCK
R
9
SCLR
SQH
Figure 4. Expanded Logic Diagram
http://onsemi.com
3
MC74LVX595
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
–0.5 to + 7.0
–0.5 to + 7.0
CC
in
V
V
out
−0.5 to V + 0.5
V
CC
I
I
I
I
−20
±20
±25
±50
mA
mA
mA
mA
mW
IK
cuit. For proper operation, V and
in
Output Diode Current
OK
out
CC
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Output Current, per Pin
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
DC Supply Current, V and GND Pins
CC
level (e.g., either GND or V ).
CC
P
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
200
180
D
Unused outputs must be left open.
T
stg
Storage Temperature
–65 to + 150
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute−maximum−rated
conditions is not implied.
†Derating — SOIC Packages: – 7.0 mW/°C from 65° to 125°C
— TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0.0
0.0
−55
0
Max
3.6
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
5.5
V
V
V
OUT
CC
T
A
Operating Temperature Range
Input Rise and Fall Time
+85
100
°C
ns/V
t , t
V
= 3.3 V ± 0.3 V
CC
r
f
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
V
CC
Min
Typ
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
High−Level Input Voltage
2.0
3.0
3.6
1.5
2.1
2.4
1.5
2.1
2.4
V
IH
V
V
V
Low−Level Input Voltage
2.0
3.0
3.6
0.5
0.8
0.8
0.5
0.8
0.8
V
V
V
IL
High−Level Output Voltage
I
I
I
= −50 mA
OH
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
OL
(V = V or V )
= −50 mA
= −4 mA
IN
IH
IL
OH
OH
Low−Level Output Voltage
I
I
I
= 50 mA
= 50 mA
= 4 mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
OL
OL
OL
(V = V or V )
IN
IH
IL
I
I
I
3−State Output
Off−State Current
V
V
= V or V
IL
3.6
±0.25
±0.1
4.0
±2.5
±1.0
40.0
mA
mA
mA
OZ
IN
IH
= V or GND
OUT
CC
Input Leakage Current
V
= 5.5 V or GND
0 to
3.6
IN
in
in
Quiescent Supply Current
V
= V or GND
3.6
CC
CC
http://onsemi.com
4
MC74LVX595
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
T
A
= ≤ 85°C
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
= 2.7 V C = 15 pF
Unit
V
90
60
130
110
80
50
f
Maximum Clock
Frequency (50% Duty
Cycle)
MHz
CC
L
max
R = 1 kW
C = 50 pF
L
L
V
= 3.3 V ± 0.3 VC = 15 pF
100
75
150
130
100
90
CC
L
R = 1 kW
C = 50 pF
L
L
V
V
V
V
V
V
V
= 2.7 V
C = 15 pF
C = 50 pF
L
11.0
13.5
14.0
17.5
1.0
1.0
16.0
19.5
t
t
,
Propagation Delay,
SCK to SQH
ns
ns
ns
ns
ns
CC
CC
CC
CC
CC
CC
CC
L
PLH
PHL
= 3.3 V ± 0.3 VC = 15 pF
8.8
11.3
12.0
15.5
1.0
1.0
13.5
17.0
L
C = 50 pF
L
= 2.7 V
C = 15 pF
10.0
13.0
14.0
17.5
1.0
1.0
16.0
19.5
t
Propagation Delay,
CPLR to SQH
L
PHL
C = 50 pF
L
= 3.3 V ± 0.3 VC = 15 pF
8.4
10.9
12.0
15.5
1.0
1.0
13.5
17.0
L
C = 50 pF
L
= 2.7 V
C = 15 pF
9.5
12.0
13.0
16.5
1.0
1.0
15.0
18.5
t
t
,
Propagation Delay,
RCK to QA−QH
L
PLH
PHL
C = 50 pF
L
= 3.3 V ± 0.3 VC = 15 pF
7.7
10.2
11.0
14.5
1.0
1.0
12.5
16.0
L
C = 50 pF
L
= 2.7 V
C = 15 pF
9.5
11.0
12.5
17.0
1.0
1.0
14.5
19.0
t
t
,
Output Enable Time,
OE to QA−QH
L
PZL
PZH
R = 1 kW
C = 50 pF
L
L
V
= 3.3 V ± 0.3 VC = 15 pF
7.5
9.0
10.5
14.0
1.0
1.0
12.0
15.5
CC
L
R = 1 kW
C = 50 pF
L
L
V
= 2.7 V
C = 50 pF
L
14.0
17.0
15.0
10
1.0
19.0
t
t
,
Output Disable Time,
OE to QA−QH
CC
PLZ
PHZ
R = 1 kW
L
V
= 3.3 V ± 0.3 VC = 50 pF
L
12.0
1.0
16.5
CC
R = 1 kW
L
C
C
Input Capacitance
4
6
10
10
pF
pF
IN
Three−State Output
Capacitance (Output in
High−Impedance State),
QA−QH
OUT
Typical @ 25°C, V = 3.3 V
CC
87
C
PD
Power Dissipation Capacitance (Note 1)
pF
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS Input t = t = 3.0 ns, C = 50 pF, V = 3.3 V
r
f
L
CC
T
A
= 25°C
Typ
0.8
Max
1.0
Symbol
Characteristic
Unit
V
Quiet Output Maximum Dynamic V
V
OLP
OLV
IHD
ILD
OL
V
V
V
Quiet Output Minimum Dynamic V
− 0.8
− 1.0
3.5
V
V
V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
1.5
http://onsemi.com
5
MC74LVX595
TIMING REQUIREMENTS Input t = t = 3.0 ns
r
f
T
A
= − 40 to
85°C
T
A
= 25°C
Typ
Limit
3.5
3.0
9.0
7.0
9.0
7.0
2.0
1.0
0
Limit
3.5
3.0
9..5
7.5
8.5
7.5
2.0
1.0
0
Symbol
Parameter
Test Conditions
= 2.7 V
Unit
V
t
Setup Time, SI to SCK
ns
CC
su
V
V
V
V
V
V
V
V
= 3.3 V ± 0.3 V
CC
CC
CC
CC
CC
CC
CC
CC
V
= 2.7 V
t
Setup Time, SCK to RCK
Setup Time, SCLR to RCK
Hold Time, SI to SCK
ns
ns
ns
ns
ns
ns
ns
CC
su(H)
= 3.3 V ± 0.3 V
= 2.7 V
V
t
CC
su(L)
= 3.3 V ± 0.3 V
= 2.7 V
V
t
CC
h
= 3.3 V ± 0.3 V
= 2.7 V
V
t
Hold Time, SCLR to RCK
CC
h(L)
= 3.3 V ± 0.3 V
= 2.7 V
0
0
V
2.5
2.0
4.0
4.0
4.0
4.0
2.5
2.0
4.0
4.0
4.0
4.0
t
Recovery Time, SCLR to
SCK
CC
rec
= 3.3 V ± 0.3 V
= 2.7 V
V
t
Pulse Width, SCK or RCK
Pulse Width, SCLR
CC
w
= 3.3 V ± 0.3 V
= 2.7 V
V
t
CC
w(L)
= 3.3 V ± 0.3 V
http://onsemi.com
6
MC74LVX595
SWITCHING WAVEFORMS
V
t
CC
w
SCK
SQH
50%
V
CC
GND
50%
SCLR
t
w
GND
1/f
t
max
PHL
t
t
PHL
PLH
50% V
CC
SQH
SCK
50% V
t
CC
rec
V
CC
50%
GND
Figure 5.
Figure 6.
V
V
CC
CC
RCK
50%
50%
OE
GND
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
t
t
PHL
PLH
50% V
CC
QA−QH
QA−QH
V
V
+0.3V
QA−QH
OL
t
t
PHZ
PZH
50% V
CC
−0.3V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 7.
Figure 8.
V
V
CC
CC
SCLR
50%
50%
SCK
RCK
GND
GND
VALID
V
t
CC
su(H)
V
50%
CC
SI
50%
GND
t
su
t
h
GND
t
w
V
CC
50%
SCK or RCK
GND
Figure 9.
Figure 10.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kW
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 11.
Figure 12.
http://onsemi.com
7
MC74LVX595
CK
SI
LR
CK
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH
NOTE:
output is in a high−impedance state.
Figure 13. Timing Diagram
INPUT
Figure 14. Input Equivalent Circuit
http://onsemi.com
8
MC74LVX595
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(±0.008”)
P
K
t
0
P
D
2
TOP
COVER
TAPE
E
SEE NOTE 2
A
F
0
W
+
+
+
K
B
0
0
B
1
SEE
NOTE 2
D
1
P
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
EMBOSSMENT
USER DIRECTION OF FEED
CENTER
LINES
OF CAVITY
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B
0
*TOP COVER
TAPE THICKNESS (t )
1
0.10 mm
(0.004”) MAX.
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS “R”
WITHOUT DAMAGE
EMBOSSED
CARRIER
EMBOSSMENT
BENDING RADIUS
100 mm
(3.937”)
MAXIMUM COMPONENT ROTATION
10°
1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE
TAPE
1 mm
(0.039”) MAX
250 mm
(9.843”)
TYPICAL
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
COMPONENT
CENTER LINE
2. A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
Figure 15. Carrier Tape Specifications
http://onsemi.com
9
MC74LVX595
EMBOSSED CARRIER DIMENSIONS (See Notes 3 and 4)
Tape
Size
B
1
Max
D
D
1
E
F
K
P
P
P
2
R
T
W
0
8 mm
4.35 mm
(0.179”)
1.0 mm
Min
3.5 mm
±0.5
2.4 mm
Max
4.0 mm
±0.10
25 mm
(0.98”)
8.3 mm
(0.327)
1.5 mm
+ 0.1
1.75 mm
±0.1
4.0 mm
±0.1
2.0 mm
±0.1
0.6 mm
(0.024)
(0.179”)
(1.38
±0.002”)
(0.094”)
(0.157
±0.004”)
−0.0
(0.069
±0.004”)
(0.157
±0.004”)
(0.079
±0.004”)
(0.059”
+0.004
−0.0)
12 mm
8.2 mm
(0.323”)
5.5 mm
±0.5
6.4 mm
Max
4.0 mm
±0.10
12.0 mm
±0.3
1.5 mm
Min
30 mm
(1.18”)
(0.217
±0.002”)
(0.252”)
(0.157
(0.470
±0.012”)
(0.060)
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
16 mm 12.1 mm
(0.476”)
7.5 mm
±0.10
7.9 mm
Max
4.0 mm
±0.10
16.3 mm
(0.642)
(0.295
(0.311”)
(0.157
±0.004”)
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
12.0 mm
±0.10
(0.472
±0.004”)
24 mm 20.1 mm
(0.791”)
11.5 mm
±0.10
11.9 mm
Max
16.0 mm
±0.10
24.3 mm
(0.957)
(0.453
(0.468”)
(0.63
±0.004”)
±0.004”)
3. Metric Dimensions Govern−English are in parentheses for reference only.
4. A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
http://onsemi.com
10
MC74LVX595
t MAX
13.0 mm ±0.2 mm
(0.512” ±0.008”)
1.5 mm MIN
(0.06”)
20.2 mm MIN
(0.795”)
50 mm MIN
(1.969”)
A
FULL RADIUS
G
Figure 16. Reel Dimensions
REEL DIMENSIONS
Tape Size
T&R Suffix
A Max
G
t Max
8 mm
T1, T2
178 mm
(7”)
8.4 mm, +1.5 mm, −0.0
(0.33” + 0.059”, −0.00)
14.4 mm
(0.56”)
8 mm
T3, T4
R2
330 mm
(13”)
8.4 mm, +1.5 mm, −0.0
(0.33” + 0.059”, −0.00)
14.4 mm
(0.56”)
12 mm
16 mm
24 mm
330 mm
(13”)
12.4 mm, +2.0 mm, −0.0
(0.49” + 0.079”, −0.00)
18.4 mm
(0.72”)
R2
360 mm
(14.173”)
16.4 mm, +2.0 mm, −0.0
(0.646” + 0.078”, −0.00)
22.4 mm
(0.882”)
R2
360 mm
(14.173”)
24.4 mm, +2.0 mm, −0.0
(0.961” + 0.078”, −0.00)
30.4 mm
(1.197”)
DIRECTION OF FEED
BARCODE LABEL
POCKET
HOLE
Figure 17. Reel Winding Direction
http://onsemi.com
11
MC74LVX595
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
CAVITY TOP TAPE
TAPE
DIRECTION OF FEED
Figure 18. Tape Ends for Finished Goods
User Direction of Feed
Figure 19. TSSOP and SOIC R2 Reel Configuration/Orientation
TAPE UTILIZATION BY PACKAGE
SC88A / SOT−353
SC88/SOT−363
Tape Size
8 mm
SOIC
TSSOP
QFN
5−, 6−Lead
12 mm
16 mm
24 mm
8−Lead
8−, 14−, 16−Lead
20−, 24−Lead
48−, 56−Lead
8−, 14−, 16−Lead
20−, 24−Lead
48−, 56−Lead
14−, 16−Lead
18−, 20−, 24−, 28−Lead
http://onsemi.com
12
MC74LVX595
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
−A
−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
1
9
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−B
−
P 8 PL
M
M
B
0.25 (0.010)
G
MILLIMETERS
MIN MAX
9.80 10.00
INCHES
MIN MAX
DIM
A
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
B
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
D
C
F
1.27 BSC
G
J
−T
0.19
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEAT−ING
M
K
0.10
0°
PLANE
Dꢀ16ꢀPL
M
P
0° 7°
0.229 0.244
5.80
0.25
6.20
0.50
M
S
S
0.25 (0.010)
T
B
A
R
0.010 0.019
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE O
16X KREF
M
S
S
V
0.10 (0.004)
T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
0.15 (0.006) T U
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
B
SECTION N−N
L
−U−
0.25 (0.010) PER SIDE.
J
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
M
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
4.90
4.30
−−−
0.193
0.169
−−−
F
C
D
0.05
0.50
0.002
0.020
F
DETAIL E
G
H
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
J
J1
K
−W−
C
K1
L
6.40 BSC
0.252 BSC
0
0.10 (0.004)
M
0
8
8
_
_
_
_
H
DETAIL E
SEATING
PLANE
−T−
D
G
http://onsemi.com
13
MC74LVX595
PACKAGE DIMENSIONS
SOIC EIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
NOTES:
ꢁꢂ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢁꢂ2. CONTROLLING DIMENSION: MILLIMETER.
ꢁꢂ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
16
9
E
Q
1
H
E
E
M
_
ꢁꢂ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
ꢁꢂ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN
A
DIM MIN
MAX
2.05
0.20
0.50
0.27
10.50
5.45
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
−−−
0.05
0.35
0.18
9.90
5.10
−−−
0.002
0.014
0.007
0.390
0.201
A
1
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
0
10
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
−−−
0.90
0.78
0.028
−−−
1
Z
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74LVX595/D
相关型号：
©2020 ICPDF网 联系我们和版权申明