MC74LVXT4052DT [ONSEMI]
Analog Multiplexer Demultiplexer; 模拟多路复用器多路解复用器
| 型号： | MC74LVXT4052DT |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexer Demultiplexer |
| 文件： | 总16页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVXT4052
Analog Multiplexer/
Demultiplexer
High–Performance Silicon–Gate CMOS
The MC74LVXT4052 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
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MARKING DIAGRAMS
(from V to V ).
CC
EE
The LVXT4052 is similar in pinout to the high–speed HC4052A
and the metal–gate MC14052B. The Channel–Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
16
9
LVXT4052
AWLYYWW
SO–16
D SUFFIX
CASE 751B
1
8
The Channel–Select and Enable inputs are compatible with standard
TTL levels.
16
9
This device has been designed so the ON resistance (R ) is more
ON
LVXT
4052
AWLYWW
linear over input voltage than the R of metal–gate CMOS analog
ON
switches and High–Speed CMOS analog switches.
TSSOP–16
DT SUFFIX
CASE 948F
• Select Pins Compatible with TTL Levels
• Fast Switching and Propagation Speeds
1
8
• Low Crosstalk Between Switches
16
9
• Analog Power Supply Range (V – V ) = *3.0 V to )3.0 V
CC
EE
LVXT4052
ALYW
• Digital (Control) Power Supply Range (V – GND) = 2.5 to 6.0 V
CC
SO EIAJ–16
M SUFFIX
CASE 966
• Improved Linearity and Lower ON Resistance Than Metal–Gate,
HSL, or VHC Counterparts
1
8
• Low Noise
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
• Designed to Operate on a Single Supply with V = GND, or Using
EE
Split Supplies up to $ 3.0 V
W, WW = Work Week
• Break–Before–Make Circuitry
ORDERING INFORMATION
Device
Package
Shipping
MC74LVXT4052D
SO–16
SO–16
48 Units/Rail
MC74LVXT4052DR2
2500 Units/Reel
MC74LVXT4052DT
TSSOP–16
96 Units/Rail
MC74LVXT4052DTR2 TSSOP–16 2500 Units/Reel
MC74LVXT4052M
SO EIAJ–16
48 Units/Rail
MC74LVXT4052MEL
SO EIAJ–16 2000 Units/Reel
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
January, 2002 – Rev. 3
MC74LVXT4052/D
MC74LVXT4052
FUNCTION TABLE
V
X2
15
X1
14
X
X0
12
X3
11
A
B
9
CC
Control Inputs
Select
16
13
10
Enable
B
A
ON Channels
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
Y0
Y1
Y2
Y3
X0
X1
X2
X3
1
2
3
4
5
6
7
8
NONE
Y0
Y2
Y
Y3
Y1 Enable
V
EE
GND
X = Don’t Care
Figure 1. Pin Connection and Marking Diagram
(Top View)
Double–Pole, 4–Position Plus Common Off
12
14
15
11
X0
X1
X2
X3
13
X SWITCH
Y SWITCH
X
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
1
5
Y0
Y1
Y2
Y3
A
3
Y
2
4
10
9
CHANNELĆSELECT
INPUTS
PIN 16 = V
CC
PIN 7 = V
B
EE
PIN 8 = GND
6
ENABLE
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls the
Y–Switch.
Figure 2. Logic Diagram
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2
MC74LVXT4052
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
EE
V
CC
Negative DC Supply Voltage
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
*7.0 to )0.5
*0.5 to )7.0
*0.5 to )7.0
V
(Referenced to V
)
EE
V
V
I
Analog Input Voltage
V
EE *0.5 to V )0.5
V
V
IS
CC
Digital Input Voltage
(Referenced to GND)
*0.5 to 7.0
$20
IN
DC Current, Into or Out of Any Pin
Storage Temperature Range
mA
_C
T
*65 to )150
260
STG
L
T
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
_C
)150
_C
J
q
SOIC
TSSOP
143
164
°C/W
JA
P
D
Power Dissipation in Still Air,
SOIC
TSSOP
500
450
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% – 35%
UL–94–VO (0.125 in)
V
ESD
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
u1000
V
I
Latch–Up Performance
Above V and Below GND at 125°C (Note 5)
$300
mA
LATCH–UP
CC
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated
conditions is not implied.
2. Tested to EIA/JESD22–A114–A.
3. Tested to EIA/JESD22–A115–A.
4. Tested to JESD22–C101–A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
V
EE
CC
Negative DC Supply Voltage
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
*6.0
GND
V
2.5
2.5
6.0
6.0
V
(Referenced to V
)
EE
V
V
T
Analog Input Voltage
Digital Input Voltage
V
V
CC
V
V
IS
EE
(Note 6) (Referenced to GND)
0
6.0
IN
Operating Temperature Range, All Package Types
*55
125
_C
ns/V
A
t , t
r
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
V
= 3.0 V $ 0.3 V
= 5.0 V $ 0.5 V
0
0
100
20
f
CC
CC
6. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
1
100
110
120
130
140
20.4
9.4
1
10
100
1000
37,000
4.2
TIME, YEARS
17,800
2.0
Figure 3. Failure Rate vs. Time Junction Temperature
8,900
1.0
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3
MC74LVXT4052
DC CHARACTERISTICS – Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
*55 to 25°C v85°C v125°C
V
Symbol
Parameter
Condition
Unit
V
IH
Minimum High–Level Input Voltage,
Channel–Select or Enable Inputs
3.0
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low–Level Input Voltage,
Channel–Select or Enable Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
I
I
Maximum Input Leakage Current,
Channel–Select or Enable Inputs
V
= 6.0 or GND
0 V to 6.0 V
$0.1
$1.0
$1.0
m A
m A
IN
IN
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
= V or GND
6.0
4.0
40
80
CC
V
IS
CC
DC ELECTRICAL CHARACTERISTICS – Analog Section
Guaranteed Limit
V
CC
V
EE
*55 to 25°C v85_C v125_C
V
V
Symbol
Parameter
Test Conditions
= V or V
Unit
R
Maximum “ON” Resistance
V
V
S
3.0
4.5
0
0
86
37
26
108
46
120
55
W
ON
IN
IS
IL
IH
= ½ (V – V
)
CC
EE
|I | = 2.0 mA
(Figure 4)
3.0 *3.0
33
37
∆R
Maximum Difference in “ON”
Resistance Between Any
Two Channels in the Same
Package
V
V
= V or V
IH
3.0
4.5
0
0
15
13
10
20
18
15
20
18
15
W
ON
IN
IS
IL
= ½ (V – V
)
CC
EE
|I | = 2.0 mA
S
3.0 *3.0
I
off
Maximum Off–Channel
Leakage Current, Any One
Channel
V
V
= V or V ;
IH
5.5
+3.0
0
–3.0
0.1
0.1
0.5
0.5
1.0
1.0
m
A
in
IL
= V or GND;
IO
CC
Switch Off (Figure 3)
Maximum Off–Channel
Leakage Current,
V
V
= V or V ;
IH
5.5
+3.0
0
–3.0
0.2
0.2
2.0
2.0
4.0
4.0
in
IL
= V or GND;
IO
CC
Common Channel
Switch Off (Figure 4)
I
on
Maximum On–Channel
Leakage Current,
Channel–to–Channel
V
= V or V
;
IH
5.5
+3.0
0
–3.0
0.2
0.2
2.0
2.0
4.0
4.0
m
A
in
IL
Switch–to–Switch =
V or GND; (Figure 5)
CC
AC CHARACTERISTICS (Input t = t = 3 ns)
r
f
Guaranteed Limit
*55 to 25_C
V
V
V
EE
V
CC
Min
Typ*
Symbol
Parameter
Test Conditions
v85_C v125_C Unit
t
Minimum Break–Before–Make
Time
V
V
= V or V
3.0
4.5
3.0
0.0
0.0
*3.0
1.0
1.0
1.0
6.5
5.0
3.5
–
–
–
–
–
–
ns
BBM
IN
IS
IL
IH
= V
CC
R = 300 WC, = 35 pF
L
L
(Figures 12 and 13)
*Typical Characteristics are at 25_C.
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MC74LVXT4052
AC CHARACTERISTICS (C = 50 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
*55 to 25°C
v85°C
v125°C
V
V
V
EE
V
CC
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Unit
t
t
,
Maximum Propagation Delay,
Channel–Select to Analog
Output
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
ns
PLH
PHL
(Figures 16 and 17)
*3.0
t
t
,
Maximum Propagation Delay,
Enable to Analog Output (Fig-
ures 14 and 15)
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
ns
ns
PLZ
PHZ
*3.0
t
t
,
Maximum Propagation Delay,
Enable to Analog Output (Fig-
ures 14 and 15)
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
PZL
PZH
*3.0
Typical @ 25°C, V = 5.0 V, V = 0V
CC
EE
45
pF
pF
C
C
Power Dissipation Capacitance (Figure 18) (Note 7)
Maximum Input Capacitance, Channel–Select or Enable Inputs
PD
IN
10
10
10
1.0
C
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I
Feedthrough
I/O
pF
2
7. Used to determine the no–load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Typ
V
CC
V
EE
V
V
25°C
Symbol
Parameter
Condition
Unit
BW
Maximum On–Channel
Bandwidth or Minimum
Frequency Response
V
= ½ (V – V )
EE
3.0
4.5
6.0
3.0
0.0
0.0
0.0
80
80
80
80
MHz
IS
CC
Ref and Test Attn = 10 dB
Source Amplitude = 0 dB
(Figure 7)
*3.0
V
V
Off–Channel Feedthrough
Isolation
f = 1 MHz; V = ½ (V – V )
EE
3.0
4.5
6.0
3.0
0.0
0.0
0.0
*70
*70
*70
*70
dB
dB
ISO
IS
CC
Adjust Network Analyzer output to 10 dBm on each
output from the power splitter.
(Figures 8 and 9)
*3.0
Maximum Feedthrough
On Loss
V
IS
= ½ (V – V )
EE
3.0
4.5
6.0
3.0
0.0
0.0
0.0
*2
*2
*2
*2
ONL
CC
Adjust Network Analyzer output to 10 dBm on each
output from the power splitter.
(Figure 11)
*3.0
Q
Charge Injection
V
R
= V to V
f
= 1 kHz, t = t = 3 ns
5.0
3.0
0.0
*3.0
9.0
12
pC
%
IN
CC
EE, IS
r
f
= 0 W, C = 1000 pF, Q = C * ∆V
OUT
IS
L
L
(Figure 10)
THD
Total Harmonic Distortion
THD + Noise
f
IS
= 1 MHz, R = 10 KW, C = 50 pF,
L
L
V
V
= 5.0 V sine wave
6.0
3.0
0.0
*3.0
0.10
0.05
IS
PP
= 6.0 V sine wave
IS
PP
(Figure 19)
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5
MC74LVXT4052
PLOTTER
PROGRAMMABLE
POWER
MINI
COMPUTER
DC ANALYZER
SUPPLY
*
)
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 4. On Resistance, Test Set–Up
V
CC
V
CC
V
CC
16
A
V
CC
ON
16
V
EE
N/C
COMMON O/I
V
EE
OFF
OFF
OFF
A
A
V
V
CC
V
CC
ANALOG I/O
NC
COMMON O/I
V
IL
6
7
8
V
EE
6
7
8
IH
V
EE
Figure 5. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 6. Maximum On Channel Leakage Current,
Channel to Channel, Test Set–Up
HP4195A
Network Anl
S1 R1 T1
0.1 m F
V
IS
HP11667B
Pwr Splitter
V
CC
100 KW
0.1 m F
ON
All untested Analog I/O pins
OFF
50 KW
Channel Selects
V
EE
6
7
8
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
9 – 11
Figure 7. Maximum On Channel Bandwidth, Test Set–Up
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6
MC74LVXT4052
HP4195A
Network Anl
S1 R1 T1
0.1 m F
HP11667B
Pwr Splitter
0.1 m F
V
IS
V
CC
100 KW
16
OFF
ON
All untested Analog I/O pins
50 KW
Channel Selects
V
EE
6
7
8
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
9 – 11
Config = Network
Format = T/R (dB)
CAL = Trans Cal
V
ISO
(dB) = 20 log (V /V
)
T1 R1
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 0 dB
Figure 8. Maximum Off Channel Feedthrough Isolation, Test Set–Up
HP4195A
Network Anl
S1 R1 T1
0.1 m F
V
IS
HP11667B
Pwr Splitter
V
CC
100 KW
0.1 m F
16
OFF
ON
50 KW
All untested Analog I/O pins
Channel Selects
V
EE
50 W
6
7
8
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
9 – 11
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
V
(dB) = 20 log (V /V
)
ISOC
T1 R1
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 0 dB
Figure 9. Maximum Common–Channel Feedthrough Isolation, Test Set–Up
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MC74LVXT4052
V
CC
16
ON/OFF
OFF/ON
V
OUT
C *
L
Enable
6
V
EE
Bias Channel Selects to
test each combination of
analog inputs to common
analog output.
7
8
R
9 – 11
V
IN
IS
*Includes all probe and jig capacitance.
V
V
IH
V
IS
IL
Q = C * D V
L
OUT
D V
OUT
V
OUT
Figure 10. Charge Injection, Test Set–Up
HP4195A
Network Anl
S1 R1 T1
0.1 m F
HP11667B
Pwr Splitter
0.1 m F
V
IS
V
CC
100 KW
16
ON
All untested Analog I/O pins
OFF
50 W
Channel Selects
V
EE
6
7
8
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
9 – 11
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
V
ONL
(dB) = 20 log (V /V
)
T1 R1
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 20 dB
Figure 11. Maximum On Channel Feedthrough On Loss, Test Set–Up
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MC74LVXT4052
Tek 11801B
DSO
V
CC
COM INPUT
V
CC
V
IN
V
OH
16
80%
OFF
ON
80% of
C
V
OH
L
R
L
Channel Selects connected
V
EE
to V and appropriately
configured to test each switch.
IN
6
7
8
9 – 11
GND
t
BBM
V
IN
50 W
Figure 12. Break–Before–Make, Test Set–Up
Figure 13. Break–Before–Make Time
V
CC
V
CC
16
COMMON
O/I
V
CC
ON/OFF
OFF/ON
TEST
POINT
ANALOG I/O
CHANNEL
SELECT
50%
GND
C *
L
6
7
8
t
t
PHL
PLH
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance.
Figure 14. Propagation Delays, Channel Select
to Analog Out
Figure 15. Propagation Delay, Test Set–Up
Channel Select to Analog Out
GND
t
f
t
r
POSITION 1 WHEN TESTING t
POSITION 2 WHEN TESTING t
AND t
AND t
PHZ
PLZ
PZH
PZL
V
CC
1
2
90%
50%
10%
ENABLE
V
CC
GND
1 KΩ
V
CC
t
t
t
16
PZL
PLZ
HIGH
IMPEDANCE
1
2
ANALOG I/O
TEST
POINT
ON/OFF
ANALOG
OUT
50%
50%
10%
V
OL
C *
L
t
PHZ
PZH
ENABLE
6
V
OH
90%
ANALOG
OUT
7
8
HIGH
IMPEDANCE
Figure 16. Propagation Delays, Enable to
Analog Out
Figure 17. Propagation Delay, Test Set–Up
Enable to Analog Out
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MC74LVXT4052
V
CC
A
V
CC
ON/OFF
OFF/ON
NC
V
IL
15
10 – 11,
13 – 14
12
Channel
Select
Figure 18. Power Dissipation Capacitance, Test Set–Up
HP3466
)V
DMM
COM
HP3466
DMM
)V
COM
HP E3630A
HP 339
DC Pwr Supply
Distortion Measurement Set
COM )20 V
*20 V
Analyzer
Oscillator
Input COM Output COM
16
ON
R
C
L
L
OFF
50 KW
Channel Selects connected
to DC bias supply or ground
and appropriately configured
to test each switch.
6
7
8
9 – 11
Figure 19. Total Harmonic Distortion, Test Set–Up
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MC74LVXT4052
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
or GND logic levels. V being recognized as a logic
outputs to V or GND through a low value resistor helps
CC
minimize crosstalk and feedthrough noise that may be
V
CC
CC
high and GND being recognized as a logic low. In this
example:
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
V
CC
= )5 V = logic high
GND = 0 V = logic low
V
V
V
– GND = 0 to *6 volts
– GND = 2.5 to 6 volts
EE
The maximum analog voltage swing is determined by the
CC
supply voltages V and V . The positive peak analog
CC
EE
– V = 2.5 to 6 volts
CC
EE
voltage should not exceed V . Similarly, the negative peak
CC
and V v GND
EE
analog voltage should not go below V . In this example,
EE
the difference between V and V is five volts. Therefore,
When voltage transients above V and/or below V are
CC EE
CC
EE
using the configuration of Figure 21, a maximum analog
signal of five volts peak–to–peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
anticipated on the analog channels, external Germanium or
Schottky diodes (D ) are recommended as shown in
x
Figure 22. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
+3.0 V
+5 V
+5 V
+3.0 V
16
16
+3.0 V
+5 V
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
ON
–3.0 V
GND
–3.0 V
GND
TO EXTERNAL CMOS
CIRCUITRY 0 to 3.0 V
DIGITAL SIGNALS
TO EXTERNAL CMOS
CIRCUITRY 0 to 5 V
DIGITAL SIGNALS
6
7
8
11
10
9
6
7
8
11
10
9
–3.0 V
Figure 20. Application Example
Figure 21. Application Example
V
CC
V
CC
V
CC
D
D
x
16
ON/OFF
x
D
D
x
x
V
EE
V
EE
7
8
V
EE
Figure 22. External Germanium or Schottky Clipping Diodes
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11
MC74LVXT4052
10
12
14
15
LEVEL
SHIFTER
A
B
X0
X1
X2
9
LEVEL
SHIFTER
11
13
1
X3
X
6
LEVEL
SHIFTER
ENABLE
Y0
5
2
4
3
Y1
Y2
Y3
Y
Figure 23. Function Diagram, LVXT4052
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12
MC74LVXT4052
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45
K
_
C
G
J
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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13
MC74LVXT4052
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T
U
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
U
0.15 (0.006) T
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
B
–U–
SECTION N–N
L
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.
S
0.15 (0.006) T
U
A
M
MILLIMETERS
INCHES
MIN
–V–
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
4.90
4.30
---
0.193
0.169
---
F
C
D
0.05
0.50
0.002
0.020
F
DETAIL E
G
H
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
J
J1
K
–W–
C
K1
L
6.40 BSC
0.252 BSC
0
0.10 (0.004)
M
0
8
8
_
_
_
_
H
DETAIL E
SEATING
PLANE
–T–
D
G
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14
MC74LVXT4052
PACKAGE DIMENSIONS
SOIC EIAJ–16
M SUFFIX
CASE 966–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
L
E
Q
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
1
H
E
M
_
E
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
---
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
---
0.05
0.35
0.18
9.90
5.10
2.05
A
A
1
1
0.20 0.002
0.50 0.014
0.27 0.007
b
0.13 (0.005)
b
c
0.10 (0.004)
M
D
E
10.50 0.390
5.45 0.201
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
0
10
0.90 0.028
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
---
1
Z
0.78
---
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15
MC74LVXT4052
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