MC74LVXT4066 [ONSEMI]
Quad Analog Switch/Multiplexer/Demultiplexer; 四路模拟开关/多路复用器/多路解复用器
| 型号： | MC74LVXT4066 |
| 厂家： | 
ONSEMI |
| 描述： | Quad Analog Switch/Multiplexer/Demultiplexer |
| 文件： | 总12页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High–Performance Silicon–Gate CMOS
The MC74LVXT4066 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
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OFF–channel
leakage
current.
This
bilateral
switch/multiplexer/demultiplexer controls analog and digital voltages
that may vary across the full power–supply range (from V to GND).
CC
The LVXT4066 is identical in pinout to the metal–gate CMOS
MC14066 and the high–speed CMOS HC4066A. Each device has four
independent switches. The device has been designed so that the ON
14–LEAD SOIC
D SUFFIX
CASE 751A
14–LEAD TSSOP
DT SUFFIX
resistances (R ) are much more linear over input voltage than R
ON
ON
of metal–gate CMOS analog switches.
CASE 948G
The ON/OFF control inputs are compatible with standard LSTTL
outputs. The input protection circuitry on this device allows
overvoltage tolerance on the ON/OFF control inputs, allowing the
device to be used as a logic–level translator from 3.0V CMOS logic to
5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic
while operating at the higher–voltage power supply.
The MC74LVXT4066 input structure provides protection when voltages
up to 7V are applied, regardless of the supply voltage. This allows the
MC74LVXT4066 to be used to interface 5V circuits to 3V circuits.
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
V
X
A
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
A ON/OFF
CONTROL
Y
A
D ON/OFF
CONTROL
Y
B
X
B
X
D
• Fast Switching and Propagation Speeds
• High ON/OFF Output Voltage Ratio
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
B ON/OFF
CONTROL
Y
D
C ON/OFF
CONTROL
Y
C
8
X
C
GND
• Wide Power–Supply Voltage Range (V
– GND) = 2.0 to 6.0 Volts
CC
For detailed package marking information, see the Marking
Diagram section on page 10 of this data sheet.
• Analog Input Voltage Range (V
CC
– GND) = 2.0 to 6.0 Volts
• Improved Linearity and Lower ON Resistance over Input Voltage
than the MC14016 or MC14066
• Low Noise
FUNCTION TABLE
LOGIC DIAGRAM
On/Off Control
Input
State of
Analog Switch
1
2
X
A
Y
A
13
4
L
H
Off
On
A ON/OFF CONTROL
3
X
B
Y
B
5
ANALOG
OUTPUTS/INPUTS
B ON/OFF CONTROL
8
9
X
C
Y
C
ORDERING INFORMATION
6
C ON/OFF CONTROL
Device
Package
Shipping
55 Units/Rail
2500 Units/Reel
96 Units/Rail
11
12
10
X
D
Y
D
MC74LVXT4066D
MC74LVXT4066DR2
MC74LVXT4066DT
SOIC
SOIC
D ON/OFF CONTROL
TSSOP
ANALOG INPUTS/OUTPUTS = X , X , X , X
B C D
A
PIN 14 = V
CC
MC74LVXT4066DTR2 TSSOP 2500 Units/Reel
PIN 7 = GND
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
March, 2000 – Rev. 1
MC74LVXT4066/D
MC74LVXT4066
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
CC
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
DC Current Into or Out of Any Pin
– 0.5 to + 7.0
V
IS
– 0.5 to V
+ 0.5
V
CC
V
in
– 0.5 to V
+ 0.5
V
CC
I
–20
mA
mW
cuit. For proper operation, V and
in
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
in out
T
stg
Storage Temperature
– 65 to + 150
260
C
C
Unused inputs must always be
tied to an appropriate logic voltage
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
level (e.g., either GND or V
).
CC
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/ C from 65 to 125 C
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
Max
Unit
V
V
CC
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
Input Rise and Fall Time, ON/OFF Control
5.5
V
IS
GND
GND
—
V
V
V
CC
V
in
V
CC
V
IO
*
1.2
V
T
A
– 55
+ 85
C
t , t
r f
ns/V
Inputs (Figure 10)
V
CC
V
CC
= 3.3 V ± 0.3 V
= 5.0 V ± 0.5 V
0
0
100
20
*Forvoltagedropsacrosstheswitchgreaterthan1.2V(switchon), excessiveV
be drawn; i.e., the current out of the switch may contain both V
CC
currentmay
and switch input
CC
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
– 55 to
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
Minimum High–Level Voltage
ON/OFF Control Inputs
(Note 1)
R
R
= Per Spec
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
IH
on
on
V
Maximum Low–Level Voltage
ON/OFF Control Inputs
(Note 1)
= Per Spec
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
IL
I
Maximum Input Leakage Current
ON/OFF Control Inputs
V
= V
or GND
or GND
5.5
± 0.1
± 1.0
± 1.0
µA
µA
in
in
CC
CC
I
Maximum Quiescent Supply
Current (per Package)
V
V
= V
= 0 V
5.5
4.0
40
160
CC
in
IO
1. Specifications are for design target only. Not final specification limits.
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2
MC74LVXT4066
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
Test Conditions
25 C
Unit
85 C
125 C
R
Maximum “ON” Resistance
Ω
V
V
= V
= V
2.0†
3.0
4.5
5.5
—
40
25
20
—
45
28
25
—
50
35
30
on
in
IS
IH
to GND
CC
2.0 mA (Figures 1, 2)
I
S
V
V
= V
2.0
3.0
4.5
5.5
—
30
25
20
—
35
28
25
—
40
35
30
in
IS
IH
= V
or GND (Endpoints)
CC
2.0 mA (Figures 1, 2)
I
S
∆R
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
= V
= 1/2 (V
2.0 mA
3.0
4.5
5.5
15
10
10
20
12
12
25
15
15
Ω
on
in
IS
IH
– GND)
CC
I
S
I
Maximum Off–Channel Leakage
Current, Any One Channel
V
V
= V
5.5
0.1
0.5
1.0
µA
µA
off
in
IL
= V
or GND
CC
IO
Switch Off (Figure 3)
I
on
Maximum On–Channel Leakage
Current, Any One Channel
V
V
= V
IH
= V
5.5
0.1
0.5
1.0
in
IS
or GND
CC
(Figure 4)
†At supply voltage (V ) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage
CC
operation, it is recommended that these devices only be used to control digital signals.
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, ON/OFF Control Inputs: t = t = 6 ns)
L
r
f
Guaranteed Limit
V
CC
V
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)
2.0
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
PLH
PHL
t
t
,
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 11)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
ns
pF
PLZ
PHZ
t
t
,
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 1 1)
2.0
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
PZL
PZH
C
Maximum Capacitance
ON/OFF Control Input
—
10
10
10
Control Input = GND
Analog I/O
—
—
35
1.0
35
1.0
35
1.0
Feedthrough
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Switch) (Figure 13)*
pF
15
PD
2
* Used to determine the no–load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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3
MC74LVXT4066
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
V
CC
V
Limit*
25 C
Symbol
Parameter
Test Conditions
= 1 MHz Sine Wave
Unit
BW
Maximum On–Channel Bandwidth
or Minimum Frequency Response
(Figure 5)
f
in
4.5
5.5
150
160
MHz
Adjust f Voltage to Obtain 0 dBm at V
in
OS
Increase f Frequency Until dB Meter Reads – 3 dB
in
R
= 50 Ω, C = 10 pF
L
L
—
—
Off–Channel Feedthrough Isolation
(Figure 6)
4.5
5.5
– 50
– 50
dB
f
Sine Wave
in
Adjust f Voltage to Obtain 0 dBm at V
in IS
f
in
= 10 kHz, R = 600 Ω, C = 50 pF
L L
f
in
= 1.0 MHz, R = 50 Ω, C = 10 pF
4.5
5.5
– 37
– 37
L
L
Feedthrough Noise, Control to
Switch
(Figure 7)
V
1 MHz Square Wave (t = t = 3 ns)
4.5
5.5
100
200
mV
PP
in
r
f
Adjust R at Setup so that I = 0 A
L
S
R = 600 Ω, C = 50 pF
L L
R
= 10 kΩ, C = 10 pF
4.5
5.5
50
100
L
L
—
Crosstalk Between Any Two
Switches
(Figure 12)
4.5
5.5
– 70
– 70
dB
%
f
Sine Wave
in
Adjust f Voltage to Obtain 0 dBm at V
in IS
f
in
= 10 kHz, R = 600 Ω, C = 50 pF
L L
f
in
= 1.0 MHz, R = 50 Ω, C = 10 pF
4.5
5.5
– 80
– 80
L
L
THD
Total Harmonic Distortion
(Figure 14)
f
= 1 kHz, R = 10 kΩ, C = 50 pF
in
THD = THD
L
L
– THD
Measured
Source
V
IS
V
IS
= 4.0 V
sine wave
sine wave
4.5
5.5
0.10
0.06
PP
PP
= 5.0 V
*Guaranteed limits not tested. Determined by design and verified by qualification.
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MC74LVXT4066
400
350
300
250
200
150
100
50
250
200
150
100
I = 1mA
–55°C
25°C
s
85°C
I = 5mA
s
125°C
I = 9mA
s
50
0
I = 15mA
s
0
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
Vin (Volts)
Vin (Volts)
Figure 1a. Typical On Resistance, V
= 2.0 V, T = 25°C
Figure 1b. Typical On Resistance, V
= 2.0 V
CC
CC
35
30
25
20
15
10
5
25
20
15
10
125°C
85°C
25°C
125°C
85°C
25°C
–55°C
–55°C
5
0
0
0
1
2
3
4
0
1
2
3
4
5
Vin (Volts)
Vin (Volts)
Figure 1c. Typical On Resistance, V
CC
= 3.0 V
Figure 1d. Typical On Resistance, V
= 4.5 V
CC
18
16
PLOTTER
125°C
85°C
14
12
10
8
PROGRAMMABLE
POWER
25°C
MINI COMPUTER
DC ANALYZER
SUPPLY
–55°C
–
+
V
CC
DEVICE
UNDER TEST
6
4
2
ANALOG IN
COMMON OUT
0
0
1
2
3
4
5
6
GND
Vin (Volts)
Figure 2. On Resistance Test Set–Up
Figure 1e. Typical On Resistance, V
CC
= 5.5 V
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MC74LVXT4066
V
CC
V
CC
V
CC
V
CC
14
14
GND
N/C
A
ON
A
OFF
GND
V
CC
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
IL
V
IH
7
7
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 4. Maximum On Channel Leakage Current,
Test Set–Up
V
OS
V
OS
V
CC
14
V
CC
14
V
IS
f
in
f
in
ON
OFF
dB
METER
dB
METER
0.1µF
0.1µF
C *
L
C *
L
R
L
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
CC
7
7
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 5. Maximum On–Channel Bandwidth
Test Set–Up
Figure 6. Off–Channel Feedthrough Isolation,
Test Set–Up
V
CC
V
CC/2
V
CC/2
14
R
R
L
L
V
OS
I
S
OFF/ON
V
CC
C *
L
50%
ANALOG IN
SELECTED
CONTROL
INPUT
GND
7
V ≤ 1 MHz
t
t
PHL
in
PLH
t = t = 3 ns
r
f
V
V
IL
IH
CONTROL
50%
ANALOG OUT
*Includes all probe and jig capacitance.
Figure 7. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set–Up
Figure 8. Propagation Delays, Analog In to
Analog Out
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MC74LVXT4066
V
CC
t
r
t
f
14
V
CC
90%
50%
10%
CONTROL
ANALOG IN
ANALOG OUT
C *
TEST
POINT
ON
GND
L
t
t
PLZ
PZL
HIGH
IMPEDANCE
50%
SELECTED
CONTROL
INPUT
V
IH
10%
90%
V
OL
ANALOG
OUT
7
t
t
PHZ
PZH
V
OH
50%
HIGH
*Includes all probe and jig capacitance.
IMPEDANCE
Figure 9. Propagation Delay Test Set–Up
Figure 10. Propagation Delay, ON/OFF Control
to Analog Out
V
IS
1
2
POSITION
POSITION
WHEN TESTING t
PHZ
AND t
PZH
V
CC
WHEN TESTING t
AND t
1
2
PLZ
PZL
14
R
L
V
OS
V
CC
f
in
ON
V
CC
0.1 µF
1 kΩ
14
1
2
TEST
POINT
OFF
ON/OFF
V
IH
OR V
IL
R
L
C *
L
R
L
C *
L
C *
L
R
L
SELECTED
CONTROL
INPUT
V
V
IL
SELECTED
CONTROL
INPUT
IH
V
CC/2
V
CC/2
7
7
V
CC/2
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 11. Propagation Delay Test Set–Up
Figure 12. Crosstalk Between Any Two Switches,
Test Set–Up
V
CC
A
V
IS
V
CC
V
OS
14
0.1 µF
TO
N/C
N/C
OFF/ON
f
in
ON
DISTORTION
METER
C *
L
R
L
V
SELECTED
CONTROL
INPUT
CC/2
7
SELECTED
CONTROL
INPUT
V
IH
7
V
V
IL
IH
ON/OFF CONTROL
*Includes all probe and jig capacitance.
Figure 13. Power Dissipation Capacitance
Test Set–Up
Figure 14. Total Harmonic Distortion, Test Set–Up
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MC74LVXT4066
0
–10
–20
–30
–40
FUNDAMENTAL FREQUENCY
–50
–60
–70
–80
–90
DEVICE
SOURCE
1.0
2.0
FREQUENCY (kHz)
3.0
Figure 15. Plot, Harmonic Distortion
APPLICATION INFORMATION
The ON/OFF Control pins should be at V or V logic
IH IL
Therefore, using the configuration in Figure 16, a maximum
analog signal of six volts peak–to–peak can be controlled.
levels, V being recognized as logic high and V being
IH IL
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is
When voltage transients above V and/or below GND
CC
are anticipated on the analog channels, external diodes (Dx)
are recommended as shown in Figure 17. These diodes
should be small signal, fast turn–on types able to absorb the
maximum anticipated current surges during clipping. An
alternate method would be to replace the Dx diodes with
Mosorbs (Mosorb is an acronym for high current surge
protectors). Mosorbs are fast turn–on devices ideally suited
for precise DC protection with no inherent wear out
mechanism.
advisable to tie unused analog inputs and outputs to V
or
CC
GND through a low value resistor. This minimizes crosstalk
and feedthrough noise that may be picked–up by the unused
I/O pins.
The maximum analog voltage swings are determined by
thesupplyvoltagesV andGND.Thepositivepeakanalog
CC
voltageshouldnotexceedV .Similarly,thenegativepeak
CC
analog voltage should not go below GND. In the example
below, the difference between V
and GND is six volts.
CC
V
CC
V
CC
V
CC
= 6.0 V
D
D
14
x
16
x
+ 6.0 V
0 V
+ 6.0 V
ANALOG I/O
ANALOG O/I
ON
ON
0 V
D
x
D
x
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
IH
V
IH
OTHER CONTROL
OTHER CONTROL
INPUTS
INPUTS
7
7
(V OR V )
(V OR V )
IH
IL
IH
IL
Figure 16. 6.0 V Application
Figure 17. Transient Suppressor Application
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MC74LVXT4066
+3 V
+5 V
+3V
+3V
14
14
ANALOG
SIGNALS
ANALOG
SIGNALS
ANALOG
SIGNALS
ANALOG
SIGNALS
GND
GND
LVXT4066
LVXT4066
LSTTL/
NMOS/
ABT/
5
6
5
6
1.8 – 2.5V
CIRCUITRY
CONTROL
INPUTS
CONTROL
INPUTS
ALS
14
15
14
15
7
7
R* = 2 TO 10 kΩ
a. Low Voltage Logic Level Shifting Control
b. Using LVXT4066
Figure 18. Low Voltage CMOS Interface
1 OF 4
SWITCHES
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
1 OF 4
SWITCHES
COMMON I/O
1 OF 4
SWITCHES
–
1 OF 4
SWITCHES
OUTPUT
1 OF 4
INPUT
+
LF356 OR
EQUIVALENT
SWITCHES
0.01 µF
1
2
3
4
CONTROL INPUTS
Figure 19. 4–Input Multiplexer
Figure 20. Sample/Hold Amplifier
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MC74LVXT4066
MARKING DIAGRAMS
(Top View)
14 13 12 11 10
9
6
8
7
14
13
12
11
10
9
6
8
7
LVXT
4066
LVXT4066
AWLYWW*
ALYW*
1
2
3
4
5
1
2
3
4
5
14–LEAD SOIC
D SUFFIX
14–LEAD TSSOP
DT SUFFIX
CASE 751A
CASE 948G
*See Applications Note #AND8004/D for date code and traceability information.
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
P 7 PL
–B–
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
MIN MAX
G
F
R X 45°
DIM MIN
MAX
8.75
4.00
1.75
0.49
1.25
C
A
B
C
D
F
G
J
K
M
P
8.55
3.80
1.35
0.35
0.40
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
J
M
SEATING
PLANE
K
D 14 PL
1.27 BSC
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
M
S
S
0.25 (0.010)
T
B
A
0°
7°
5.80
0.25
6.20
0.50
0.228 0.244
0.010 0.019
R
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10
MC74LVXT4066
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.10 (0.004)
T U
V
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
–U–
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
L
N
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
K
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
–V–
A
B
C
4.90
4.30
–––
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
––– 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N–N
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
0.19
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
SEATING
PLANE
–T–
H
G
DETAIL E
D
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11
MC74LVXT4066
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MC74LVXT4066/D
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