MC74LVXT8053DR2G [ONSEMI]
Analog Multiplexer / Demultiplexer High−Performance Silicon−Gate CMOS; 模拟多路复用器/多路解复用器高性能硅栅CMOS
| 型号： | MC74LVXT8053DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexer / Demultiplexer High−Performance Silicon−Gate CMOS |
| 文件： | 总12页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVXT8053
Analog Multiplexer /
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT8053 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
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MARKING
DIAGRAMS
(from V to GND).
CC
The LVXT8053 is similar in pinout to the high−speed HC4053A,
and the metal−gate MC14053B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected by means
of an analog switch to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with
TTL−type input thresholds. The input protection circuitry on this
device allows overvoltage tolerance on the input, allowing the device
to be used as a logic−level translator from 3.0 V CMOS logic to 5.0 V
CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while
operating at the higher−voltage power supply.
16
SOIC−16
D SUFFIX
CASE 751B
LVXT8053
AWLYWW
1
16
LVXT
8053
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
The MC74LVXT8053 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74LVXT8053 to be used to interface 5.0 V circuits to
3.0 V circuits.
1
This device has been designed so that the ON resistance (R ) is
on
more linear over input voltage than R of metal−gate CMOS analog
switches.
on
16
1
SOEIAJ−16
M SUFFIX
CASE 966
LVXT8053
ALYW
Features
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (V − GND) = 2.0 V to 6.0 V
CC
A
=
=
=
=
Assembly Location
Wafer Lot
Year
• Digital (Control) Power Supply Range (V − GND) = 2.0 V to 6.0 V
WL or L
Y
WW or W
CC
• Improved Linearity and Lower ON Resistance Than Metal−Gate
Work Week
Counterparts
• Low Noise
• In Compliance With the Requirements of JEDEC Standard No. 7A
• Pb−Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
March, 2005 − Rev. 4
MC74LVXT8053/D
MC74LVXT8053
FUNCTION TABLE − MC74LVXT8053
Control Inputs
V
Y
X
X1
13
X0
12
A
B
C
9
CC
16
15
14
11
10
Select
Enable
C
B
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
Z0
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
X1
X0
X1
X0
X1
X0
X1
L
1
2
3
4
Z
5
6
7
8
H
H
H
H
X
L
Y1
Y0
Z1
Z0 Enable NC GND
H
H
X
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
X = Don’t Care
12
13
X0
X1
14
X
Y
Z
X SWITCH
2
1
Y0
Y1
15
ANALOG
COMMON
OUTPUTS/INPUTS
Y SWITCH
Z SWITCH
INPUTS/OUTPUTS
5
3
Z0
Z1
4
11
10
9
A
B
C
CHANNEL-SELECT
INPUTS
PIN 16 = V
CC
PIN 8 = GND
6
ENABLE
NOTE: This device allows independent control of each switch. Channel−Select Input A
controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch
Figure 1. LOGIC DIAGRAM
Triple Single−Pole, Double−Position Plus Common Off
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVXT8053DR2
MC74LVXT8053DR2G
SOIC−16
2500 Tape & Reel
2500 Tape & Reel
SOIC−16
(Pb−Free)
MC74LVXT8053DTR2
MC74LVXT8053M
TSSOP−16*
SOEIAJ−16
2500 Tape & Reel
50 Units / Rail
50 Units / Rail
MC74LVXT80531MG
SOEIAJ−16
(Pb−Free)
MC74LVXT8053MEL
MC74LVXT8053MELG
SOEIAJ−16
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVXT8053
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage
–0.5 to + 7.0
CC
V
−0.5 to V + 0.5
V
IS
CC
V
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
–0.5 to V + 0.5
V
in
CC
I
−20
mA
mW
cuit. For proper operation, V and
in
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
V
out
should be constrained to the
range GND v (V or V ) v V
.
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
T
stg
Storage Temperature Range
–65 to + 150
260
°C
°C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Package: – 7 mW/°C from 65°C to 125°C
TSSOP Package: − 6.1 mW/°C from 65°C to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
Max
Unit
V
V
CC
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage
6.0
V
IS
0.0
V
CC
V
CC
V
V
in
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
GND
V
V *
IO
1.2
V
T
A
–55
+ 85
°C
ns/V
t , t
Input Rise/Fall Time
r
f
(Channel Select or Enable Inputs)
V
CC
V
CC
= 3.3 V ± 0.3 V
= 5.0 V ± 0.5 V
0
0
100
20
*For voltage drops across switch greater than 1.2 V (switch on), excessive V current may be
CC
drawn; i.e., the current out of the switch may contain both V and switch input components. The
CC
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
−55 to 25°C ≤85°C ≤125°C
V
Symbol
Parameter
Condition
= Per Spec
Unit
V
IH
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
R
R
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
on
on
V
IL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
= Per Spec
3.0
4.5
5.5
0.53
0.8
0.53
0.8
0.53
0.8
V
0.8
0.8
0.8
I
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
V
= V or GND,
5.5
± 0.1
± 1.0
± 1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
= V or GND; V = 0 V
5.5
4
40
160
CC
V
IS
CC
IO
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3
MC74LVXT8053
DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit
v
v
V
V
CC
85°C
125°C
−55 to 25°C
Symbol
Parameter
Test Conditions
= V or V
Unit
R
Maximum “ON” Resistance
W
V
V
3.0
4.5
5.5
40
30
25
45
32
28
50
37
30
on
in
IL
IH
= V to GND
IS
CC
|I | v 10.0 mA (Figures 1, 2)
S
V
V
= V or V
IH
3.0
4.5
5.5
30
25
20
35
28
25
40
35
30
in
IL
= V or GND (Endpoints)
IS
CC
|I | v 10.0 mA (Figures 1, 2)
S
DR
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
= V or V
IH
3.0
4.5
5.5
15
8.0
8.0
20
12
12
25
15
15
W
on
in
IL
= 1/2 (V − GND)
IS
CC
|I | v 10.0 mA
S
mA
I
off
Maximum Off−Channel Leakage
Current, Any One Channel
V
V
= V or V ;
IH
5.5
5.5
5.5
0.1
0.1
0.1
0.5
1.0
1.0
1.0
2.0
2.0
in
IL
= V or GND;
IO
CC
Switch Off (Figure 3)
Maximum Off−Channel
Leakage Current,
Common Channel
V
V
= V or V ;
IL IH
in
= V or GND;
IO
CC
Switch Off (Figure 4)
I
on
Maximum On−Channel
Leakage Current,
Channel−to−Channel
V
in
= V or V
;
IH
mA
IL
Switch−to−Switch =
V or GND; (Figure 5)
CC
AC CHARACTERISTICS (C = 50 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
−55 to 25°C ≤85°C ≤125°C
V
V
CC
Symbol
Parameter
Unit
t
t
t
t
,
Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 9)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
PLH
t
PHL
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
PLZ
t
PHZ
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
PZL
t
PZH
C
Maximum Input Capacitance, Channel−Select or Enable Inputs
10
35
50
1.0
10
35
50
1.0
10
35
50
1.0
pF
pF
in
C
Maximum Capacitance
(All Switches Off)
Analog I/O
I/O
Common O/I
Feedthrough
Typical @ 25°C, V = 5.0 V
CC
C
45
PD
Power Dissipation Capacitance (Figure 13)*
pF
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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4
MC74LVXT8053
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Limit*
V
CC
25°C
V
Symbol
Parameter
Condition
= 1MHz Sine Wave; Adjust f Voltage to Obtain 0dBm
Unit
BW
Maximum On−Channel Bandwidth
f
in
MHz
in
or Minimum Frequency Response at V ; Increase f Frequency Until dB Meter Reads −3
OS
in
120
120
120
3.0
4.5
5.5
(Figure 6)
dB;
R = 50 W, C = 10 pF
L
L
−
−
Off−Channel Feedthrough
Isolation (Figure 7)
f
V
= Sine Wave; Adjust f Voltage to Obtain 0 dBm at
−50
−50
−50
dB
3.0
4.5
5.5
in
in
IS
f
in
= 10kHz, R = 600 W, C = 50 pF
L L
3.0
4.5
5.5
−37
−37
−37
f
in
= 1.0MHz, R = 50W, C = 10pF
L L
Feedthrough Noise.
Channel−Select Input to Common Setup so that I = 0A;
I/O (Figure 8)
V
≤ 1MHz Square Wave (t = t = 3 ns); Adjust R at
25
105
135
mV
3.0
4.5
5.5
in
r
f
L
PP
S
Enable = GND
R = 600 W, C = 50pF
L L
3.0
4.5
5.5
35
145
190
R = 10 kW, C = 10pF
L
L
−
Crosstalk Between Any Two
Switches (Figure 12)
f
in
= Sine Wave; Adjust f Voltage to Obtain 0dBm at V
IS
−50
−50
−50
dB
3.0
4.5
5.5
in
f
in
= 10 kHz, R = 600W, C = 50pF
L L
3.0
4.5
5.5
−60
−60
−60
f
in
= 1.0MHz, R = 50W, C = 10pF
L L
THD
Total Harmonic Distortion
(Figure 14)
f
= 1kHz, R = 10 kW, C = 50pF
%
in
L
L
THD = THD
− THD
measured
source
V
= 2.0V sine wave
3.0
4.5
5.5
0.10
0.08
0.05
IS
PP
V
IS
V
IS
= 4.0V sine wave
PP
= 5.0V sine wave
PP
*Limits not tested. Determined by design and verified by qualification.
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5
MC74LVXT8053
45
40
35
30
25
20
15
10
5
125°C
85°C
25°C
−ꢀ55°C
0
0
1.0
2.0
3.0
4.0
V , INPUT VOLTAGE (VOLTS)
IN
Figure 1a. Typical On Resistance, VCC = 3.0 V
35
30
25
20
15
30
25
125°C
85°C
25°C
125°C
20
85°C
25°C
−ꢀ55°C
15
−ꢀ55°C
10
10
5
5
0
0
0
1.0
2.0
3.0
4.0
5.0
0
1.0
2.0
3.0
4.0
5.0
6.0
V , INPUT VOLTAGE (VOLTS)
IN
V , INPUT VOLTAGE (VOLTS)
IN
Figure 1b. Typical On Resistance, VCC = 4.5 V
Figure 1c. Typical On Resistance, VCC = 5.5 V
PLOTTER
PROGRAMMABLE
POWER
SUPPLY
MINI COMPUTER
DC ANALYZER
−
+
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 1. On Resistance Test Set−Up
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6
MC74LVXT8053
V
CC
V
CC
V
V
CC
CC
16
16
GND
GND
ANALOG I/O
OFF
OFF
OFF
OFF
A
V
V
CC
V
CC
COMMON O/I
NC
COMMON O/I
V
IH
6
8
6
8
IH
Figure 2. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 3. Maximum Off Channel Leakage Current,
Common Channel, Test Set−Up
V
CC
V
OS
V
CC
V
CC
16
16
0.1 mF
A
dB
METER
f
in
ON
ON
N/C
R
L
GND
C *
L
COMMON O/I
OFF
V
CC
ANALOG I/O
V
IL
6
8
6
8
*Includes all probe and jig capacitance
Figure 4. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
Figure 5. Maximum On Channel Bandwidth,
Test Set−Up
V
CC
V
CC
V
IS
V
OS
16
16
0.1 mF
dB
METER
R
L
f
in
OFF
ON/OFF
OFF/ON
COMMON O/I
TEST
POINT
ANALOG I/O
R
L
R
L
C *
L
R
L
C *
L
R
L
6
8
6
8
V
CC
V
≤ 1 MHz
11
in
t = t = 3 ns
r
f
V
IH
CHANNEL SELECT
*Includes all probe and jig capacitance
CHANNEL SELECT
*Includes all probe and jig capacitance
V
IL
or V
V
IL
IH
Figure 6. Off Channel Feedthrough Isolation,
Test Set−Up
Figure 7. Feedthrough Noise, Channel Select to
Common Out, Test Set−Up
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7
MC74LVXT8053
V
CC
V
CC
16
V
CC
ON/OFF
OFF/ON
COMMON O/I
C *
CHANNEL
SELECT
TEST
POINT
50%
ANALOG I/O
GND
L
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set−Up Channel
Select to Analog Out
V
CC
16
COMMON O/I
C *
ANALOG I/O
TEST
POINT
V
CC
ON
ANALOG
IN
50%
L
GND
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In
to Analog Out
Figure 10b. Propagation Delay, Test Set−Up
Analog In to Analog Out
t
t
POSITION 1 WHEN TESTING t
AND t
PZH
POSITION 2 WHEN TESTING t AND t
f
r
PHZ
1
2
PLZ
PZL
V
CC
90%
50%
10%
ENABLE
V
CC
GND
1kW
V
CC
16
t
t
PLZ
PZL
HIGH
IMPEDANCE
1
2
ANALOG I/O
ENABLE
TEST
POINT
ON/OFF
ANALOG
OUT
50%
t
C *
L
10%
V
OL
t
V
IH
PZH
PHZ
V
IL
6
8
V
OH
90%
ANALOG
OUT
50%
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set−Up
Enable to Analog Out
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8
MC74LVXT8053
V
CC
V
IS
A
V
CC
16
16
R
L
V
OS
ON/OFF
OFF/ON
COMMON O/I
f
in
ON
NC
ANALOG I/O
0.1mF
OFF
R
L
R
L
C *
L
C *
L
V
CC
R
L
6
8
6
8
11
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 12. Crosstalk Between Any Two
Switches, Test Set−Up
Figure 13. Power Dissipation Capacitance,
Test Set−Up
0
−ꢀ10
−ꢀ20
−ꢀ30
−ꢀ40
V
IS
FUNDAMENTAL FREQUENCY
V
CC
V
OS
16
0.1mF
TO
DISTORTION
METER
f
in
ON
R
L
C *
L
−ꢀ50
−ꢀ60
DEVICE
SOURCE
6
8
−ꢀ70
−ꢀ80
−ꢀ90
*Includes all probe and jig capacitance
−100
1.0
2.0
3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set−Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at connected). However, tying unused analog inputs and
V
CC
or GND logic levels. V being recognized as a logic
outputs to V or GND through a low value resistor helps
CC
CC
high and GND being recognized as a logic low. In this
example:
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
V
= +5V = logic high
CC
GND = 0V = logic low
The maximum analog voltage swing is determined by the
supply voltages V . The positive peak analog voltage
V
CC
− GND = 2 to 6 volts
CC
should not exceed V . Similarly, the negative peak analog
When voltage transients above V and/or below GND
CC
CC
voltage should not go below GND. In this example, the
are anticipated on the analog channels, external Germanium
difference between V and GND is five volts. Therefore,
or Schottky diodes (D ) are recommended as shown in
CC
x
using the configuration of Figure 15, a maximum analog
signal of five volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
Figure 16. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
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9
MC74LVXT8053
V
CC
V
CC
+5V
V
CC
D
D
16
x
16
ON/OFF
x
+5V
0V
+5V
0V
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
D
x
D
x
GND
GND
TO EXTERNAL LSTTL COMPATIBLE
CIRCUITRY 0 to V
DIGITAL SIGNALS
6
8
11
10
9
IH
8
Figure 15. Application Example
Figure 16. External Germanium or
Schottky Clipping Diodes
+3V
+5V
16
16
+3V
+5V
+3V
+5V
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ON/OFF
ON/OFF
GND
GND
GND
GND
1.8 − 2.5V
6
8
11
10
9
6
8
11
10
9
1.8 − 2.5V
CIRCUITRY
1.8 − 2.5V
CIRCUITRY
MC74VHC1GT50 BUFFERS
= 3.0V
V
CC
a. Low Voltage Logic Level Shifting Control
b. 2−Stage Logic Level Shifting Control
Figure 17. Interfacing Low Voltage CMOS Inputs
11
10
9
13
LEVEL
SHIFTER
A
X1
12
14
1
X0
X
LEVEL
SHIFTER
B
Y1
2
15
3
Y0
Y
LEVEL
SHIFTER
C
Z1
5
4
Z0
Z
6
LEVEL
SHIFTER
ENABLE
Figure 18. Function Diagram, LVXT8053
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10
MC74LVXT8053
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
G
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
7
0
_
_
_
_
M
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
NOTES:
16X KREF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
D
F
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
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11
MC74LVXT8053
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
L
E
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
Q
1
H
E
M
_
E
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
−−−
0.05
0.35
0.18
9.90
5.10
2.05
A
A
1
0.20 0.002
0.50 0.014
0.27 0.007
1
b
0.13 (0.005)
b
c
0.10 (0.004)
M
D
E
10.50
5.45 0.201
0.390
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
_
0.035
0.031
0
_
_
_
0.70
−−−
1
Z
0.78
−−−
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