MC74VHC125DR2G [ONSEMI]
Quad Bus Buffer with 3âState Control Inputs;
| 型号： | MC74VHC125DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad Bus Buffer with 3âState Control Inputs 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC125
Quad Bus Buffer
with 3−State Control Inputs
The MC74VHC125 is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
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The MC74VHC125 requires the 3−state control input (OE) to be set
High to place the output into the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
14−LEAD SOIC
14−LEAD TSSOP
DT SUFFIX
D SUFFIX
CASE 751A
CASE 948G
• High Speed: t = 3.8ns (Typ) at V = 5 V
PD
CC
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V
= 28% V
NIH
NIL CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
14−LEAD SOIC EIAJ
M SUFFIX
CASE 965
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V
= 0.8 V (Max)
OLP
PIN CONNECTION AND
MARKING DIAGRAM
(Top View)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
OE1
A1
1
2
14
13 OE4
12
V
CC
Machine Model; > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
Y1
3
4
A4
OE2
11 Y4
A2
Y2
5
6
7
10 OE3
9
8
A3
Y3
GND
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC125DG
SOIC
55 Units/Rail
2500 Units/Reel
50 Units/Rail
MC74VHC125DTR2G TSSOP
MC74VHC125MG
SOIC EIAJ
SOIC
MC74VHC125DR2G
2500 Units/Reel
2000 Units/Reel
MC74VHC125MELG SOEIAJ
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 6
MC74VHC125/D
MC74VHC125
LOGIC DIAGRAM
Active−Low Output Enables
2
1
3
6
A1
Y1
OE1
5
4
A2
Y2
Y3
OE2
9
8
A3
10
OE3
12
13
11
A4
Y4
OE4
FUNCTION TABLE
VHC125
Inputs Output
A
OE
Y
H
L
L
L
H
L
X
H
Z
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or elec-
tric fields. However, precautions
must be taken to avoid applications
of any voltage higher than maxim-
um rated voltages to this high−im-
pedance circuit. For proper opera-
V
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to +7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
–0.5 to V +0.5
V
out
IK
CC
I
− 20
$ 20
$ 25
$ 50
mA
mA
mA
mA
mW
I
OK
tion, V and V should be con-
in
out
strained to the range GND v (V
I
DC Output Current, per Pin
in
out
or V ) v V
.
out
CC
I
DC Supply Current, V and GND Pins
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
500
450
level (e.g., either GND or V ). Un-
CC
used outputs must be left open.
T
stg
Storage Temperature
–65 to +150
°C
** Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute−maximum−rated conditions is
not implied.
†Derating
−
SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
V
in
DC Input Voltage
5.5
V
V
out
DC Output Voltage
0
V
CC
V
T
Operating Temperature, All Package Types
−55
+125
°C
ns/V
A
t , t
r
Input Rise and Fall Time
V
CC
= 3.3 V $0.3 V
=5.0 V $0.5 V
0
0
100
20
f
V
CC
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2
MC74VHC125
DC ELECTRICAL CHARACTERISTICS
V
CC
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
Symbol
Parameter
Test Conditions
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
V
V
V
Minimum High−Level
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
IH
Input Voltage
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
IL
Minimum High−Level
V
OH
= V or V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
V
V
OH
IN
IH
IL
IL
IL
IL
IL
Output Voltage
I
= −50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OH
OH
IH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum Low−Level
V
OL
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
IN
IH
Output Voltage
I
= 50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
IH
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum 3−State
Leakage Current
V
V
= V or V
5.5
$0.2
$2.5
$1.0
40
$2.5
$1.0
40
mA
mA
mA
OZ
IN
OUT
IH
= V or GND
5
CC
I
IN
Maximum Input
Leakage Current
V
= 5.5V or GND
0 to
5.5
$0.1
IN
IN
I
Maximum Quiescent
Supply Current
V
= V or GND
5.5
4.0
CC
CC
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3
MC74VHC125
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
= ≤
A
125°C
T
A
= 25°C
T = ≤ 85°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Maximum Propagation Delay,
A to Y
V
V
V
= 3.3 $ 0.3V C = 15 pF
5.6
8.1
8.0
1.0
1.0
9.5
1.0
1.0
12.0
16.0
ns
PLH
CC
CC
CC
L
t
11.5
13.0
C = 50 pF
L
PHL
= 5.0 $ 0.5V C = 15 pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
8.5
10.5
L
C = 50 pF
L
,
Maximum Output Enable TIme,
OE to Y
= 3.3 $ 0.3V C = 15 pF
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
1.0
1.0
11.5
15.0
ns
ns
ns
PZL
t
L
R = 1 kW
C = 50 pF
PZH
L
L
V
CC
= 5.0 $ 0.5V C = 15 pF
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
1.0
1.0
7.5
9.5
L
R = 1 kW
C = 50 pF
L
L
,
Maximum Output Disable Time,
OE to Y
V
CC
= 3.3 $ 0.3V C = 50 pF
9.5
13.2
8.8
1.5
1.0
10
1.0
15.0
10.0
1.5
1.0
18.0
12.0
1.5
PLZ
t
L
R = 1 kW
PHZ
L
V
CC
= 5.0 $ 0.5V C = 50 pF
6.1
1.0
1.0
L
R = 1 kW
L
t
,
Output−to−Output Skew
V
CC
= 3.3 $ 0.3V C = 50 pF
OSLH
L
t
(Note 1)
OSHL
V
CC
= 5.0 $ 0.5V C = 50 pF
1.0
1.0
L
(Note 1)
C
Maximum Input Capacitance
4
6
10
10
pF
pF
in
C
Maximum Three−State Output
Capacitance (Output in High
Impedance State)
out
Typical @ 25°C, V = 5.0 V
CC
14
C
Power Dissipation Capacitance (Note 2)
= |t
pF
PD
1. Parameter guaranteed by design. t
− t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /4 (per buffer). C is used to determine the
CC(OPR
CC
PD CC in CC PD
2
ꢀ f + I ꢀ V
in
.
D
PD
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
0.8
Symbol
Characteristic
Quiet Output Maximum Dynamic V
Unit
V
V
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−0.3
−0.8
3.5
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
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4
MC74VHC125
SWITCHING WAVEFORMS
V
CC
OE
50%
V
CC
GND
50%
t
t
PZL
PLZ
A
Y
GND
HIGH
t
PHL
t
IMPEDANCE
PLH
50% V
Y
CC
V
V
+ 0.3V
OL
50% V
CC
t
t
PZH
PHZ
- 0.3V
OH
50% V
Y
CC
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST POINT
1 kW
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
TESTING t AND t
PLZ
OUTPUT
PZL.
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
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5
MC74VHC125
MARKING DIAGRAMS
(Top View)
14 13 12 11 10
9
8
14
13
12
11
10
9
6
8
VHC
125
VHC125
AWLYWW*
ALYW*
1
2
3
4
5
7
1
2
3
4
5
6
7
14−LEAD SOIC
D SUFFIX
14−LEAD TSSOP
DT SUFFIX
CASE 751A
CASE 948G
14
13
12
11
10
9
6
8
7
VHC125
AWLYWW*
1
2
3
4
5
14−LEAD SOIC EIAJ
M SUFFIX
CASE 965
*See Applications Note AND8004/D for date code and traceability information.
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6
MC74VHC125
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
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7
MC74VHC125
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
J1
K
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
D
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
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8
MC74VHC125
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
14
8
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
---
VIEW P
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
e
A
---
0.05
0.35
0.10
9.90
5.10
2.05
c
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
D
E
e
10.50 0.390
5.45 0.201
A
b
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
0.13 (0.005)
E
L
0.10 (0.004)
L
E
M
0
10
0.90 0.028
10
_
0.035
0.056
0
_
_
_
Q
0.70
---
1
Z
1.42
---
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MC74VHC125/D
相关型号：
MC74VHC125MELG
AHC/VHC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, EIAJ, PLASTIC, SOIC-14
ONSEMI
MC74VHC125MR2
Bus Driver, AHC/VHC Series, 4-Func, 1-Bit, True Output, CMOS, PDSO14, EIAJ, PLASTIC, SOIC-14
MOTOROLA
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