MC74VHC1G05DFT2G-L22038 [ONSEMI]
单逆变器，开漏;
| 型号： | MC74VHC1G05DFT2G-L22038 |
| 厂家： | 
ONSEMI |
| 描述： | 单逆变器，开漏 栅 栅极 |
| 文件： | 总6页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1G05
Single Inverter with Open
Drain Output
The MC74VHC1G05 is an advanced high speed CMOS inverter with
open drain output fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including an open
drain output which provides the capability to set output switching level.
This allows the MC74VHC1G05 to be used to interface 5 V circuits to
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MARKING
DIAGRAMS
circuits of any voltage between V and 7 V using an external resistor
CC
and power supply.
The MC74VHC1G05 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage.
5
SC−88A / SOT−353 / SC−70
DF SUFFIX
VF M G
Features
G
CASE 419A
• High Speed: t = 3.8 ns (Typ) at V = 5 V
PD
CC
1
5
• Low Internal Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
• Power Down Protection Provided on Inputs
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FET = 105
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
VF M G
CASE 483
G
• Pb−Free Packages are Available
1
VF
M
G
= Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
V
NC
IN A
GND
1
2
5
CC
*Date Code orientation and/or position may
vary depending upon manufacturing location.
OVT
PIN ASSIGNMENT
OUT Y
3
4
1
2
3
4
5
NC
IN A
GND
OUT Y
Figure 1. Pinout (Top View)
V
CC
FUNCTION TABLE
1
IN A
OUT Y
A Input
Y Output
L
Z
L
Figure 2. Logic Symbol
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
February, 2007 − Rev. 14
MC74VHC1G05/D
MC74VHC1G05
MAXIMUM RATINGS
Symbol
Characteristics
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
−20
Unit
V
V
DC Supply Voltage
DC Input Voltage
CC
V
V
IN
V
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
V
OUT
I
mA
mA
mA
mA
°C
IK
I
V
< GND; V
> V
CC
+20
OK
OUT
OUT
I
+25
OUT
I
DC Supply Current, V and GND
+50
CC
CC
T
Storage Temperature Range
*65 to )150
260
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
°C
L
T
)150
°C
J
q
Thermal Resistance
SC70−5/SC−88A/SOT−353 (Note 1)
SOT23−5/TSOP−5/SC59−5
350
230
°C/W
JA
P
Power Dissipation in Still Air at 85°C
SC70−5/SC−88A/SOT−353
SOT23−5/TSOP−5/SC59−5
150
200
mW
D
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
R
V
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
V
ESD
I
Latchup Performance
Above V and Below GND at 125°C (Note 5)
$500
mA
LATCHUP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0.0
0.0
−55
Max
5.5
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
V
5.5
V
IN
V
7.0
V
OUT
T
A
Operating Temperature Range
Input Rise and Fall Time
+125
°C
ns/V
t , t
r
V
V
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
f
CC
CC
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1G05
DC ELECTRICAL CHARACTERISTICS
V
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
CC
Symbol
Parameter
Test Conditions
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
V
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
IH
V
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
IL
V
= V
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
Maximum Low−Level
Output Voltage
IN
IH
OL
I
OL
V
= V or V
IN
IH IL
V
= V
IH
= 4 mA
= 8 mA
IN
OL
OL
I
I
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Z−State Output Leakage
Current
V
V
= V
IL
5.5
$0.25
$2.5
$5.0
1.0
40
mA
mA
mA
mA
LKG
IN
= V or GND
OUT
CC
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
IN
IN
I
Maximum Quiescent
Supply Current
V
= V or GND
5.5
1.0
20
CC
IN
CC
I
Power Off−Output
Leakage Current
V
V
= 5.5 V
= 5.5 V
0
0.25
2.5
5
OFF
OUT
IN
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
= 3.3 0.3 V C = 15 pF
5.0
7.5
7.1
10.6
8.5
12.0
10.0
14.5
ns
t
Maximum Output
Enable Time,
Input A to Y
CC
L
PZL
R = R = 500 W
C = 50 pF
L
L
I
V
= 5.0 0.5 V C = 15 pF
3.8
5.3
5.5
7.5
6.5
8.5
8.0
10.0
CC
L
R = R = 500 W
C = 50 pF
L
L
I
V
= 3.3 0.3 V C = 50 pF
I
7.5
5.3
4
10.6
7.5
10
12.0
8.5
10
14.5
10.0
10
ns
t
Maximum Output
Disable Time
CC
L
PLZ
R = R = 500 W
L
V
= 5.0 0.5 V C = 50 pF
L
CC
R = R = 500 W
L
I
C
Maximum Input
Capacitance
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
18
C
Power Dissipation Capacitance (Note 6)
PD
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1G05
V
− 7 V
CC
V
CC
V
A
CC
50%
R
L
OVT
GND
A
t
t
PLZ
PZL
HIGH
IMPEDANCE
50% V
Y
CC
V
+0.3 V
OL
Figure 4. Output Voltage Mismatch Application
Figure 5. Switching Waveforms
V
CC
V
x 2
R
1
CC
PULSE
GENERATOR
DUT
R
T
C
L
R
L
C = 50 pF equivalent (Includes jig and probe capacitance)
L
R = R = 500 W or equivalent
L
1
R = Z
T
of pulse generator (typically 50 W)
OUT
Figure 6. Test Circuit
V
CC
MC74VHC1G01
A
B
2.2 kW
V
V
CC
CC
MC74VHC1G03
MC74VHC1G05
1
2
5
4
MC74VHC1G05
3.3 V
C
D
1.5 V
R
LED
A
F = (A • B) + (C+D) + E
220 W
3
A
E
GTL
Figure 7. Complex Boolean Functions
Figure 8. LED Driver
Figure 9. GTL Driver
ORDERING INFORMATION
†
Device
MC74VHC1G05DFT1
MC74VHC1G05DFT1G
Package
Shipping
SC70−5 / SC−88A / SOT−353
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G05DFT2
MC74VHC1G05DFT2G
SC70−5 / SC−88A / SOT−353
3000/Tape & Reel
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G05DTT1
MC74VHC1G05DTT1G
SOT23−5 / TSSOP−5 / SC59−5
SOT23−5 / TSSOP−5 / SC59−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G05
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
G
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
D 5 PL
0.2 (0.008)
B
−−−
0.004
0.004
0.004
0.010
0.012
−−−
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74VHC1G05
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
C
D
G
H
J
K
L
M
S
0.90
0.25
0.95 BSC
1.10
0.50
C
SEATING
PLANE
0.05
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
T
10
3.00
_
_
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC1G05/D
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